专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US06643919B1 Method of fabricating a semiconductor device package having a core-hollowed portion without causing resin flash on lead frame 有权
标题翻译：制造具有芯 - 中空部分而不引起引线框架上的树脂闪光的半导体器件封装的方法
公开(公告)号：US06643919B1
公开(公告)日：2003-11-11
申请号：US09574869
申请日：2000-05-19
申请人： Chien-Ping Huang
发明人： Chien-Ping Huang
IPC分类号： H01R4300
CPC分类号： H01L23/49861 , B29C33/0044 , B29C39/10 , B29C45/14655 , B29L2031/3061 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L2224/32245 , H01L2224/45144 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01079 , Y10T29/49121 , Y10T29/49144 , Y10T29/49169 , Y10T29/49172 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor device package fabrication method is proposed, which is used for the fabrication of a semiconductor device package of the type having a core-hollowed portion that is typically used to house an optically-sensitive semiconductor device such as an image sensor or an ultraviolet-sensitive EPROM (Electrically-Programmable Read-Only Memory) device. The proposed method is characterized in the use of a support pillar, which is positioned beneath the lead frame when the lead frame is clamped between a top inserted mold and a bottom cavity mold, to help prevent resin flash on the lead frame during the molding of the core-hollowed portion. As a result, the proposed method can help strengthen the bonding of the semiconductor device on the die pad as well as the wire bonding on the inner end of the finger portion of the lead frame, Moreover, since the making of the support pillar would be significantly cheaper and easier to implement than the use of an organic high-molecule coating and a solvent as in the case of the prior art flash prevention, the proposed method is more cost-effective and environmentally-friendly to use than the prior art.
摘要翻译：提出了一种半导体器件封装制造方法，其用于制造具有芯空心部分的类型的半导体器件封装，该芯 - 中空部分通常用于容纳诸如图像传感器或紫外线照射的光敏半导体器件，灵敏的EPROM（电可编程只读存储器）器件。所提出的方法的特征在于当引线框架被夹持在顶部插入的模具和底部空腔模具之间时，位于引线框架下方的支撑柱的使用，以帮助防止在成型期间引线框架上的树脂闪光芯 - 中空部分。结果，所提出的方法可以有助于加强半导体器件在芯片焊盘上的接合以及引线框架的指状部分的内端上的引线接合。此外，由于支撑柱的制造将是与使用现有技术闪光灯防止的情况相比，使用有机高分子涂层和溶剂显着地便宜且易于实现，所提出的方法比现有技术更具成本效益和使用环境友好性。

52. 发明授权

US06621150B1 Lead frame adaptable to the trend of IC packaging 有权
标题翻译：引线框架适应IC封装的趋势
公开(公告)号：US06621150B1
公开(公告)日：2003-09-16
申请号：US10193530
申请日：2002-07-10
申请人： Yvonne Lee , Chien-Ping Huang , Han-Ping Pu
发明人： Yvonne Lee , Chien-Ping Huang , Han-Ping Pu
IPC分类号： H01L23495
CPC分类号： H01L23/4951 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： Conventional configuration of a lead frame, particularly a lead frame in a Lead-on-Chip package, is substituted by one having inward ends of leads thereof arranged in unprecedented ways, resulting in bigger gap between any two adjacent inward ends of inner leads, leading to bigger Inner Lead Pitch of a lead frame in which the space available is inherently limited. It is by the new configuration that an IC packaging process can be immunized against the difficulty resulting from too small Inner Lead Pitch of a lead frame, and the bottle neck in the process of packaging an IC subject to the tendency of minimizing the size of an IC can thus be overcome.
摘要翻译：引线框架，特别是芯片上封装的引线框架的传统结构被以前所未有的方式布置的引线框架的内端置换为引线框架，导致内引线的任何两个相邻内端之间的间隙较大到引脚框架的较大的内引脚间距，其中可用的空间固有地受到限制。通过新的配置，IC封装过程可以免受针脚引起的内部引线间距太小的困难，并且在封装IC的过程中瓶颈处于使IC的尺寸最小化的趋势因此可以克服IC。

53. 发明授权

US06583499B2 Quad flat non-leaded package and leadframe for use in a quad flat non-leaded package 有权
标题翻译：四面扁平无铅封装和引线框架，用于四方扁平无铅封装
公开(公告)号：US06583499B2
公开(公告)日：2003-06-24
申请号：US09861757
申请日：2001-05-21
申请人： Chien-Ping Huang , Tzong-Dar Her
发明人： Chien-Ping Huang , Tzong-Dar Her
IPC分类号： H01L23495
CPC分类号： H01L23/3114 , H01L23/49503 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/85399 , H01L2924/00014 , H01L2924/181 , H05K3/341 , H05K2201/0373 , H05K2201/10689 , H05K2201/10969 , Y02P70/613 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A quad flat non-leaded package comprises: a die pad having a first upper surface and a corresponding first lower surface thereon a plurality of interlacing slots are formed, each of the interlacing slots extending to the edges of the die pad to form a plurality of island-like blocks; a plurality of leads disposed at the periphery of the die pad, wherein each of the leads has respectively a second upper surface and a corresponding second lower surface coplanar to the surface of the island-like blocks; a chip having an active surface and a corresponding back surface adhered onto the first upper surface of the die pad; and a molding compound encapsulating the chip, the second upper surface, the first upper surface and the interlacing slots while exposing the surface of the island-like blocks and the second lower surface of the leads.
摘要翻译：四边形无铅包装包括：形成具有第一上表面和其上的对应的第一下表面的管芯焊盘，其上形成有多个交缠槽，每个交缠槽延伸到管芯焊盘的边缘以形成多个岛状块多个引线设置在管芯焊盘的周边，其中每个引线分别具有与岛状块的表面共面的第二上表面和相应的第二下表面; 芯片，其具有粘附到芯片焊盘的第一上表面上的活性表面和对应的背面; 以及在使岛状块的表面和引线的第二下表面暴露的同时封装芯片，第二上表面，第一上表面和交织槽的模塑料。

54. 发明授权

US06541854B2 Super low profile package with high efficiency of heat dissipation 有权
公开(公告)号：US06541854B2
公开(公告)日：2003-04-01
申请号：US09894884
申请日：2001-06-29
申请人： Chien-Ping Huang , Tzong-Dar Her
发明人： Chien-Ping Huang , Tzong-Dar Her
IPC分类号： H01L2334
CPC分类号： H01L21/568 , H01L23/4334 , H01L23/49816 , H01L23/49827 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/85001 , H01L2924/00014 , H01L2924/01079 , H01L2924/15173 , H01L2924/15311 , H01L2924/1532 , H01L2924/18165 , Y10T29/49146 , Y10T29/49171 , H01L2924/00 , H01L2224/45099
摘要： A super low profile package with high efficiency of heat dissipation comprises the substrate, the heat sink, the die, the wires and the plastic mold. The heat sink adheres to the ground ring by the extending part of the heat sink, and the first surface of the die adheres to the heat sink. In addition, the die is connected to the substrate by the wires, and the plastic mold encapsulates the die, the heat sink and the wires. The chip package according to the invention possesses the small size and high efficiency of heat dissipation; besides, it also decreases the production cost for eliminating the conventional procedures of taping and de-taping.

55. 发明授权

US06507121B2 Array structure of solder balls able to control collapse 有权
公开(公告)号：US06507121B2
公开(公告)日：2003-01-14
申请号：US09756086
申请日：2001-01-08
申请人： Chien-Ping Huang
发明人： Chien-Ping Huang
IPC分类号： H01L2348
CPC分类号： H01L21/4853 , H01L23/3128 , H01L23/49816 , H01L24/48 , H01L25/0657 , H01L2224/05599 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/85399 , H01L2225/0651 , H01L2225/06517 , H01L2225/06586 , H01L2924/00014 , H01L2924/01322 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H05K3/3436 , H05K3/3463 , H05K2201/094 , H05K2201/10234 , H05K2201/10477 , H05K2201/10992 , H05K2201/2036 , H05K2203/041 , Y02P70/613 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A solder ball array type package structure is able to control collapse. The package includes a substrate, a carrier, a plurality of dies, a molding compound and a plurality of solder balls. The substrate has at least one active surface. Pads are located on the first surface of the substrate. The carrier has at least an active surface and a back surface opposite the active surface. A plurality of dies are located on the back surface and the active surface of the carrier. The dies arranged on the active surface are electrically connected to the carrier by flip chip technology. A molding compound encapsulates on the back surface of the carrier to cover the dies on the back surface of the carrier. Solder balls having a base material are provided on the active surface of the carrier in array. At least three solder balls coated with the base material having a high melting-temperature core are further provided in the periphery of the array. The carrier is arranged such that the active surface faces the first surface of the substrate to allow each solder ball correspond to the one of the pads, respectively.

56. 发明授权

US06498391B1 Dual-chip integrated circuit package with unaligned chip arrangement and method of manufacturing the same 有权
标题翻译：具有未对准芯片布置的双芯片集成电路封装及其制造方法
公开(公告)号：US06498391B1
公开(公告)日：2002-12-24
申请号：US09473308
申请日：1999-12-28
申请人： Chien-Ping Huang , Lian-Cherng Chiang , Michael Chang
发明人： Chien-Ping Huang , Lian-Cherng Chiang , Michael Chang
IPC分类号： H01L23495
CPC分类号： H01L23/4951 , H01L23/3107 , H01L23/49575 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/32014 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48639 , H01L2224/48739 , H01L2224/48839 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/85439 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01079 , H01L2924/10161 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A dual-chip integrated circuit package with unaligned chip arrangement and a method of manufacturing such a dual-chip integrated circuit package are provided. The dual-chip integrated circuit package includes a leadframe having a first set of leads and a second set of leads. The dual-chip integrated circuit package is used to pack two integrated circuit chips in an unaligned chip arrangement, in which the first integrated circuit chip is mounted to one side of the inner part of the first set of leads, and the second integrated circuit chip is mounted to the other side of the same in such a manner as to allow the bonding pads on the second integrated circuit chip to be positioned in the spacing formed between the two sets of leads. This unaligned chip arrangement can help facilitate the wire-bonding process for the bonding pads are the second integrated circuit chip. An encapsulant is used for encapsulating the first integrated circuit chip, the second integrated circuit chip, the set of bonding wires, the second set of bonding wires, the inner part of the first set of leads, and the inner part of the second set of leads. The particular structure of the dual-chip integrated circuit package allows no restriction to the relative size between first two integrated circuit chips, thus allowing flexible selection for the combination of the two integrated circuit chips. Moreover, the dual-chip integrated circuit package are help save layout space on the circuit board and offers more functionality and storage capacity.
摘要翻译：提供了具有未对准芯片布置的双芯片集成电路封装以及制造这种双芯片集成电路封装的方法。双芯片集成电路封装包括具有第一组引线和第二组引线的引线框架。双芯片集成电路封装用于以未对准的芯片布置来封装两个集成电路芯片，其中第一集成电路芯片安装在第一组引线的内部的一侧，第二集成电路芯片以这样的方式安装到其另一侧，即允许第二集成电路芯片上的接合焊盘定位在两组引线之间形成的间隔中。这种未对准的芯片布置可以帮助便于焊接工艺的焊盘是第二个集成电路芯片。密封剂用于封装第一集成电路芯片，第二集成电路芯片，一组接合线，第二组接合线，第一组引线的内部和第二组引线的内部领导。双芯片集成电路封装的特定结构不限制前两个集成电路芯片之间的相对尺寸，从而允许灵活地选择两个集成电路芯片的组合。此外，双芯片集成电路封装有助于节省电路板上的布局空间，并提供更多的功能和存储容量。

57. 发明授权

US06437447B1 Dual-sided chip package without a die pad 有权
标题翻译：双面芯片封装，无芯片
公开(公告)号：US06437447B1
公开(公告)日：2002-08-20
申请号：US09697296
申请日：2000-10-27
申请人： Chien-Ping Huang , Chin-Yuan Hung , Chang-Fu Chen , Jenn-Shyh Yu , Jui-Hsiang Hung
发明人： Chien-Ping Huang , Chin-Yuan Hung , Chang-Fu Chen , Jenn-Shyh Yu , Jui-Hsiang Hung
IPC分类号： H01L2348
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L2924/00014 , H01L2924/10162 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： In a dual-sided chip package without a die pad according to the invention, a first die can be fixed directly on the lead fingers of a leadframe, a support bar, or bus bars, while a second die is attached to the first die. Without a die pad, the distance between the surfaces of the dies and the plastic surface of the package therefore gets longer. Thus, the invention enables a large decrease in the probability of generating voids in the plastic and there is no need to grind the dies. Besides, it improves the vibration and floating characteristics of the dies in the manufacturing process and thus prevents the exposure of the bonding wires and the shelling off or breaking of the dies. The invention can raise the yield of chip packages.
摘要翻译：在根据本发明的没有芯片焊盘的双面芯片封装中，第一裸片可以直接固定在引线框架，支撑杆或汇流条的引线上，而第二裸片附接到第一裸片。没有管芯焊盘，因此，模具表面与封装的塑料表面之间的距离变长。因此，本发明能够大大降低在塑料中产生空隙的可能性，并且不需要研磨模具。此外，在制造过程中，提高了模具的振动和浮动特性，防止了接合线的暴露和模具脱壳或断裂。本发明可以提高芯片封装的产量。

58. 发明授权

US06396707B1 Ball grid array package 有权
标题翻译：球栅阵列封装
公开(公告)号：US06396707B1
公开(公告)日：2002-05-28
申请号：US09454006
申请日：1999-12-03
申请人： Chien-Ping Huang , Grace Yang
发明人： Chien-Ping Huang , Grace Yang
IPC分类号： H05K702
CPC分类号： H01L23/49816 , H01L2924/0002 , H05K3/3452 , H05K3/3457 , H05K2201/0989 , H01L2924/00
摘要： A ball grid array package comprises a substrate having a first surface and a second surface, a chip, an insulating material, and a solder ball. The surface of the substrate comprises ball pads, conducting traces, and solder masks wherein the conducting traces are disposed in between the adjacent ball pads, and are covered by the solder mask, in addition, a portion of each of the ball pads is also covered by the solder mask. The solder mask includes an opening positioned in the area corresponding to the ball pads wherein the opening exposes a portion of the surface the ball pad and a portion of the side wall of the ball pad. The chip is disposed on the second surface of the substrate, and is sealed and encapsulated by the insulated material. The solder balls are disposed on the first surface of the substrate, and are positioned at the openings of the ball pads. Additionally, the solder balls are electrically connected to a portion of the surface of the ball pads and a portion of the side wall of the ball pads disposed at the ball pad openings.
摘要翻译：球栅阵列封装包括具有第一表面和第二表面的衬底，芯片，绝缘材料和焊球。衬底的表面包括球垫，导电迹线和焊接掩模，其中导电迹线设置在相邻的球垫之间，并被焊接掩模覆盖，此外，每个球垫的一部分也被覆盖通过焊接面罩。焊接掩模包括位于对应于球垫的区域中的开口，其中开口暴露表面的一部分球垫和球垫的侧壁的一部分。芯片设置在基板的第二表面上，并被绝缘材料密封和封装。焊球设置在基板的第一表面上，并且位于球垫的开口处。此外，焊球与电极焊盘表面的一部分电连接，球垫侧壁的一部分设置在球垫开口处。

59. 发明授权

US06350669B1 Method of bonding ball grid array package to circuit board without causing package collapse 有权
标题翻译：将球栅阵列封装焊接到电路板而不会导致封装崩溃的方法
公开(公告)号：US06350669B1
公开(公告)日：2002-02-26
申请号：US09699888
申请日：2000-10-30
申请人： Han-Ping Pu , Chien-Ping Huang
发明人： Han-Ping Pu , Chien-Ping Huang
IPC分类号： H01L2144
CPC分类号： H01L24/11 , H01L21/4846 , H01L2224/05571 , H01L2224/05573 , H01L2224/11334 , H01L2224/13099 , H01L2224/14505 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H05K3/3436 , H05K3/3463 , H05K2201/094 , H05K2201/10234 , H05K2201/10992 , H05K2203/041 , Y02P70/613 , H01L2224/05599
摘要： A method is proposed for bonding a BGA (Ball Grid Array) package to a circuit board without causing the collapsing of the BGA package against the circuit board. The proposed method is characterized in the use of two groups of solder balls of different reflow collapse degrees, which are arranged in an interspersed manner among each other in the ball grid array. In one embodiment, the first group of solder balls are homogenously made of a solder material of a specific melting point; and the second group of solder balls each include an outer portion and a core portion, with the outer portion having substantially the same melting point as the first group of solder balls, and the core portion being greater in melting point than the outer portion. In another embodiment, the second group of solder balls are greater in melting point than the first group of solder balls. During the solder-reflow process, when the first group of solder balls are entirely melted, the second group of solder balls are only partly melted or entirely unmelted and thus are capable of providing a solid support to the BGA package to prevent the collapsing of BGA package against circuit board.
摘要翻译：提出了一种用于将BGA（球栅阵列）封装结合到电路板而不引起BGA封装相对于电路板折叠的方法。所提出的方法的特征在于使用不同回流塌陷度的两组焊球，其在球栅阵列中以散布的方式相互排列。在一个实施例中，第一组焊球由具有特定熔点的焊料均质地制成; 并且第二组焊球各自包括外部部分和芯部分，外部部分具有与第一组焊球基本相同的熔点，并且芯部分的熔点大于外部部分。在另一个实施例中，第二组焊球的熔点高于第一组焊球。在焊料回流工艺期间，当第一组焊球完全熔化时，第二组焊球仅部分熔化或完全未熔化，因此能够为BGA封装提供固体支撑以防止BGA的塌陷封装电路板。

60. 发明授权

US06306682B1 Method of fabricating a ball grid array integrated circuit package having an encapsulating body 有权
标题翻译：制造具有封装体的球栅阵列集成电路封装的方法
公开(公告)号：US06306682B1
公开(公告)日：2001-10-23
申请号：US09547157
申请日：2000-04-11
申请人： Chien-Ping Huang , Randy H. Y. Lo , Tzong-Da Ho , Eric Ko , Jui-Meng Jao
发明人： Chien-Ping Huang , Randy H. Y. Lo , Tzong-Da Ho , Eric Ko , Jui-Meng Jao
IPC分类号： H01L2144
CPC分类号： H01L21/56 , H01L23/3128 , H01L24/48 , H01L2224/05599 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2224/92247 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A method of fabricating a BGA (Ball Grid Array) IC package of the type having an encapsulating body is proposed, which allows the BGA IC package to be manufactured without having to use conventional organic substrate and encapsulating-body mold having cavity, so that the manufacture process can be more cost-effective to carry out than the prior art. The proposed method is characterized in the use of a copper piece which is selectively removed to form an encapsulating-body cavity for the forming of an encapsulating body therein. The proposed method requires no use of mold with cavity for the forming of the encapsulating body, allowing the same mold to be used for the fabrication of various BGA IC packages of different sizes. Moreover, the proposed method allows fan-in design as well as fan-out design, thus allowing the number of I/O ports to be increased while making the overall package configuration compact in size, and also allows the implantation of the electrically-conductive balls to be easier to carry out and more precisely controlled than the prior art, making the ball implantation more assured in quality than the prior art. Therefore, the proposed method is more advantageous and cost-effective to use than the prior art.
摘要翻译：提出了一种制造具有封装体的BGA（球栅阵列）IC封装的方法，其允许制造BGA IC封装，而不必使用传统的有机衬底和具有空腔的封装体模具，制造工艺比现有技术更具成本效益。所提出的方法的特征在于使用铜片，其被选择性地去除以形成用于在其中形成封装体的封装体腔体。所提出的方法不需要使用具有空腔的模具来形成封装体，允许相同的模具用于制造不同尺寸的各种BGA IC封装。此外，所提出的方法允许风扇设计以及扇出式设计，从而允许增加I / O端口的数量，同时使整个封装结构的尺寸紧凑，并且还允许将导电球比现有技术更容易实施和更精确地控制，使得球注入在质量上比现有技术更加确保。因此，所提出的方法比现有技术更有利且成本有效。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式