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1. 发明授权

US08058100B2 Method for fabricating chip scale package structure with metal pads exposed from an encapsulant 有权
标题翻译：用于制造具有从密封剂暴露的金属焊盘的芯片级封装结构的方法
公开(公告)号：US08058100B2
公开(公告)日：2011-11-15
申请号：US12788772
申请日：2010-05-27
申请人： Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
IPC分类号： H01L21/60
CPC分类号： H01L21/561 , H01L21/568 , H01L23/3114 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/20 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/18161 , H01L2924/18162 , H01L2924/351 , H01L2224/82 , H01L2924/00
摘要： A chip scale package structure and a method for fabricating the same are disclosed. The method includes forming metal pads on a predetermined part of a carrier; mounting chips on the carrier, each of the chips having a plurality of conductive bumps soldered to the metal pads; forming an encapsulant on the carrier to encapsulate the chips and the conductive bumps; removing the carrier to expose the metal pads and even the metal pads with a surface of the encapsulant; forming on the encapsulant a plurality of first conductive traces electrically connected to the metal pads; applying a solder mask on the first conductive traces, and forming a plurality of openings on the solder mask to expose a predetermined part of the first conductive traces; forming a plurality of conductive elements on the predetermined part; and cutting the encapsulant to form a plurality of chip scale package structures.
摘要翻译：公开了一种芯片级封装结构及其制造方法。该方法包括在载体的预定部分上形成金属垫; 在载体上安装芯片，每个芯片具有焊接到金属焊盘的多个导电凸块; 在载体上形成密封剂以封装芯片和导电凸块; 移除载体以暴露金属垫和甚至具有密封剂表面的金属垫; 在所述密封剂上形成电连接到所述金属焊盘的多个第一导电迹线; 在所述第一导电迹线上施加焊接掩模，以及在所述焊接掩模上形成多个开口以暴露所述第一导电迹线的预定部分; 在所述预定部分上形成多个导电元件; 以及切割所述密封剂以形成多个芯片级封装结构。

2. 发明授权

US07993967B2 Semiconductor package fabrication method 有权
标题翻译：半导体封装制造方法
公开(公告)号：US07993967B2
公开(公告)日：2011-08-09
申请号：US12616834
申请日：2009-11-12
申请人： Yih-Jenn Jiang , Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Yih-Jenn Jiang , Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/3121 , H01L21/561 , H01L21/6835 , H01L24/48 , H01L24/97 , H01L2221/68345 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15747 , H01L2924/181 , H01L2924/18161 , H01L2924/351 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2224/0401 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in each through hole; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and conductive metallic layer to allow the conductive metallic layer to protrude from the insulation layer. In the present invention, the distance between the semiconductor package and the external device is increased, and thermal stress caused by difference between the thermal expansion coefficients is reduced, so as to enhance the reliability of the product.
摘要翻译：公开了半导体封装和制造方法。制造方法包括在金属载体的一个表面上施加牺牲层，在牺牲层上施加绝缘层，以及在牺牲层和绝缘层中形成通孔以露出金属载体; 在每个通孔中形成导电金属层; 在所述绝缘层上形成图案化电路层，以电连接到所述导电金属层; 将至少一个芯片安装在所述绝缘层上并将所述芯片电连接到所述图案化电路层; 形成密封剂以封装所述芯片和所述图案化电路层; 并且去除金属载体和牺牲层以暴露绝缘层和导电金属层，以允许导电金属层从绝缘层突出。在本发明中，半导体封装和外部器件之间的距离增加，由于热膨胀系数之差导致的热应力降低，从而提高了产品的可靠性。

3. 发明申请

US20100151631A1 FABRICATION METHOD OF SEMICONDUCTOR PACKAGE HAVING HEAT DISSIPATION DEVICE 有权
标题翻译：具有热消散装置的半导体封装的制造方法
公开(公告)号：US20100151631A1
公开(公告)日：2010-06-17
申请号：US12710450
申请日：2010-02-23
申请人： Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
IPC分类号： H01L21/60
CPC分类号： H01L23/473 , H01L21/563 , H01L23/3157 , H01L2224/16225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253
摘要： A semiconductor package with a heat dissipating device and a fabrication method of the semiconductor package are provided. A chip is mounted on a substrate. The heat dissipating device is mounted on the chip, and includes an accommodating room, and a first opening and a second opening that communicate with the accommodating room. An encapsulant is formed between the heat dissipating device and the substrate to encapsulate the chip. A cutting process is performed to remove a non-electrical part of structure and expose the first and second openings from the encapsulant. A cooling fluid is received in the accommodating room to absorb and dissipate heat produced by the chip. The heat dissipating device covers the encapsulant and the chip to provide a maximum heat transfer area for the semiconductor package.
摘要翻译：提供了具有散热装置的半导体封装和半导体封装的制造方法。芯片安装在基板上。散热装置安装在芯片上，并且包括容纳室，以及与容纳室连通的第一开口和第二开口。在散热装置和衬底之间形成密封剂以封装芯片。执行切割处理以去除结构的非电气部分并且从密封剂暴露第一和第二开口。冷却流体容纳在容纳室中以吸收和散发由芯片产生的热量。散热装置覆盖密封剂和芯片，以为半导体封装提供最大的传热面积。

4. 发明授权

US07671466B2 Semiconductor package having heat dissipating device with cooling fluid 有权
标题翻译：具有冷却液的散热装置的半导体封装
公开(公告)号：US07671466B2
公开(公告)日：2010-03-02
申请号：US11647832
申请日：2006-12-29
申请人： Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
IPC分类号： H01L23/34 , H05K7/20 , H01L21/00
CPC分类号： H01L23/473 , H01L21/563 , H01L23/3157 , H01L2224/16225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253
摘要： A semiconductor package with a heat dissipating device and a fabrication method of the semiconductor package are provided. A chip is mounted on a substrate. The heat dissipating device is mounted on the chip, and includes an accommodating room, and a first opening and a second opening that communicate with the accommodating room. An encapsulant is formed between the heat dissipating device and the substrate to encapsulate the chip. A cutting process is performed to remove a non-electrical part of structure and expose the first and second openings from the encapsulant. A cooling fluid is received in the accommodating room to absorb and dissipate heat produced by the chip. The heat dissipating device covers the encapsulant and the chip to provide a maximum heat transfer area for the semiconductor package.
摘要翻译：提供了具有散热装置的半导体封装和半导体封装的制造方法。芯片安装在基板上。散热装置安装在芯片上，并且包括容纳室，以及与容纳室连通的第一开口和第二开口。在散热装置和衬底之间形成密封剂以封装芯片。执行切割处理以去除结构的非电气部分，并使第一和第二开口与密封剂暴露。冷却流体容纳在容纳室中以吸收和散发由芯片产生的热量。散热装置覆盖密封剂和芯片，以为半导体封装提供最大的传热面积。

5. 发明申请

US20070296079A1 Heat dissipating structure and method for fabricating the same 审中-公开
标题翻译：散热结构及其制造方法
公开(公告)号：US20070296079A1
公开(公告)日：2007-12-27
申请号：US11818225
申请日：2007-06-12
申请人： Chien-Ping Huang , Han-Ping Pu , Ho-Yi Tsai
发明人： Chien-Ping Huang , Han-Ping Pu , Ho-Yi Tsai
IPC分类号： H01L23/34 , H01L21/58
CPC分类号： H01L23/4334 , H01L23/3121 , H01L24/48 , H01L2224/4824 , H01L2224/73204 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/1815 , H01L2924/18165 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A heat sink package structure and a method for fabricating the same are disclosed. The method includes mounting and electrically connecting a semiconductor chip to a chip carrier, forming an interface layer or a second heat dissipating element having the interface layer on the semiconductor chip and installing a first heat dissipating element having a heat dissipating portion and a supporting portion onto the chip carrier. The method further includes forming openings corresponding to the semiconductor chip in the heat dissipating portion, and forming an encapsulant for covering the semiconductor chip, the interface layer or the second heat dissipating element, and the first heat dissipating element. A height is reserved on top of the interface layer for the formation of the encapsulant for covering the interface layer. The method further includes cutting the encapsulant along edges of the interface layer, and removing the redundant encapsulant on the interface layer. Therefore, the drawbacks of the prior art of the burrs caused by a cutting tool for cutting the heat dissipating element and wearing of the cutting tool are overcome.
摘要翻译：公开了一种散热器封装结构及其制造方法。该方法包括将半导体芯片安装并电连接到芯片载体，在半导体芯片上形成具有界面层的界面层或第二散热元件，并将具有散热部分和支撑部分的第一散热元件安装到芯片载体。该方法还包括形成对应于散热部分中的半导体芯片的开口，以及形成用于覆盖半导体芯片，界面层或第二散热元件的密封剂和第一散热元件。在接口层顶部保留一个高度，用于形成覆盖界面层的密封剂。该方法还包括沿着界面层的边缘切割密封剂，以及去除界面层上的冗余密封剂。因此，克服了用于切割散热元件的切削工具和切削工具的磨损引起的毛刺现有技术的缺陷。

6. 发明申请

US20060097402A1 Semiconductor device having flip-chip package and method for fabricating the same 审中-公开
标题翻译：具有倒装芯片封装的半导体器件及其制造方法
公开(公告)号：US20060097402A1
公开(公告)日：2006-05-11
申请号：US11267707
申请日：2005-11-03
申请人： Han-Ping Pu , Chien-Ping Huang
发明人： Han-Ping Pu , Chien-Ping Huang
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L25/03 , H01L23/3128 , H01L23/3135 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00012 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2224/0401
摘要： A semiconductor device having a flip-chip package and a method for fabricating the same are provided. A flip-chip package after being tested to be functionally workable is mounted on a carrier and is electrically connected to the carrier by a plurality of first conductive elements, the flip-chip package having a first chip mounted on a substrate in a flip-chip manner. At least a second chip is mounted on the flip-chip package and is electrically connected to the carrier by a plurality of second conductive elements. An encapsulant is formed on the carrier for encapsulating the flip-chip package and the second chip. A plurality of solder balls are implanted on a bottom surface of the carrier, such that the first and second chips can be electrically connected to an external device via the solder balls. The above arrangement can effectively improve the yield of a fabricated product and reduce packaging costs.
摘要翻译：提供了一种具有倒装芯片封装的半导体器件及其制造方法。被测试在功能上可操作的倒装芯片封装安装在载体上并且通过多个第一导电元件与载体电连接，该倒装芯片封装具有安装在基板上的倒装芯片方式。至少第二芯片安装在倒装芯片封装上，并通过多个第二导电元件与载体电连接。在载体上形成密封剂，用于封装倒装芯片封装和第二芯片。在载体的底面上注入多个焊球，使得第一芯片和第二芯片可以经由焊球电连接到外部装置。上述布置可以有效地提高制成品的产量并降低包装成本。

7. 发明授权

US06943439B2 Substrate and fabrication method of the same 失效
标题翻译：基板及其制造方法相同
公开(公告)号：US06943439B2
公开(公告)日：2005-09-13
申请号：US10116204
申请日：2002-04-04
申请人： Chien-Ping Huang , Han-Ping Pu , Chih-Chin Liao
发明人： Chien-Ping Huang , Han-Ping Pu , Chih-Chin Liao
IPC分类号： H01L21/48 , H01L23/498 , H01L23/544 , H05K1/02 , H05K3/24 , H05K3/28 , H05K3/34 , H01L23/02 , H01L23/48 , H01L23/495 , H01L23/52 , H01L29/40
CPC分类号： H01L24/85 , H01L21/4846 , H01L22/34 , H01L23/49816 , H01L24/48 , H01L2224/48 , H01L2224/8501 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H05K1/0269 , H05K3/242 , H05K3/28 , H05K3/3489 , H05K2201/09781 , H01L2224/45099 , H01L2224/05599
摘要： A substrate and a fabrication method thereof are proposed, with at least a check point being formed on the substrate. Prior to wire bonding and/or molding processes, cleanness of the substrate (cleaned by plasma) is determined according to color variation of the check point, so as to allow only cleaned and contamination-free substrates to be subsequently formed with bonding wires and encapsulants thereon. Thereby, qualities of wire-bonded electrical connection and encapsulant adhesion for the substrate can be assured, which helps prevent the occurrence of delamination between the encapsulant and the substrate. Moreover, the check point formed on the substrate is made during general substrate fabrication by using current equipment and technique, and in a manner as not to interfere with trace routability on the substrate; thereby, costs and complexity of substrate fabrication would not undesirably increased.
摘要翻译：提出了一种基板及其制造方法，至少在基板上形成检查点。在引线接合和/或模制工艺之前，根据检查点的颜色变化确定基材的清洁度（通过等离子体清洁），以便仅使用清洁和无污染的基材随后用接合线和密封剂形成上。因此，可以确保线接合电连接的质量和用于衬底的密封剂附着性，这有助于防止密封剂和衬底之间的分层的发生。此外，通过使用当前的设备和技术，在通常的基板制造中形成的检查点，并且以不干扰基板上的迹线布线性的方式进行; 因此，衬底制造的成本和复杂性将不会不期望地增加。

8. 发明申请

US20050040524A1 Chip carrier for semiconductor chip 有权
标题翻译：半导体芯片芯片载体
公开(公告)号：US20050040524A1
公开(公告)日：2005-02-24
申请号：US10909029
申请日：2004-07-30
申请人： Han-Ping Pu , Chang-Fu Lin , Chien-Ping Huang
发明人： Han-Ping Pu , Chang-Fu Lin , Chien-Ping Huang
IPC分类号： H01L23/498 , H01L23/48
CPC分类号： H01L23/49816 , H01L23/49838 , H01L2224/16 , H01L2924/01079 , H01L2924/15311
摘要： A chip carrier for a semiconductor chip is provided. A plurality of solder pads for bump soldering are formed on a chip mounting surface of the chip carrier, to allow a flip chip to be mounted and electrically connected to the chip carrier. A solder mask layer is formed on the chip carrier, wherein a plurality of openings are provided in the solder mask layer to expose the solder pads, and an outwardly opening extended portion is formed respectively from the openings corresponding to the solder pads having a relatively narrower pitch therebetween, so as to prevent formation of voids during an underfill process for filing a gap between the flip chip and the chip carrier.
摘要翻译：提供了一种用于半导体芯片的芯片载体。在芯片载体的芯片安装表面上形成用于凸块焊接的多个焊盘，以允许倒装芯片安装并电连接到芯片载体。在芯片载体上形成焊料掩模层，其中在焊料掩模层中设置多个开口以露出焊盘，并且从对应于具有相对较窄的焊盘的开口分别形成向外开口的延伸部分间隔，以防止在底部填充过程中形成空隙，以便在倒装芯片和芯片载体之间填充间隙。

9. 发明授权

US06830957B2 Method of fabricating BGA packages 有权
标题翻译：球栅阵列半导体封装的制作方法
公开(公告)号：US06830957B2
公开(公告)日：2004-12-14
申请号：US10452488
申请日：2003-05-30
申请人： Han-Ping Pu , Chien-Ping Huang , Chih-Ming Huang
发明人： Han-Ping Pu , Chien-Ping Huang , Chih-Ming Huang
IPC分类号： H01L2144
CPC分类号： H01L24/97 , H01L21/565 , H01L23/3128 , H01L2224/16 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/81 , H01L2924/00 , H01L2224/0401
摘要： A method of fabricating BGA (Ball Grid Array) packages is proposed, which utilizes a specially-designed carrier to serve as an auxiliary tool to package semiconductor chips on substrates. The carrier is formed with a plurality of cavities respective for receiving a substrate and in communication with an injection gate, such that no injection gate is required on the substrate, thereby not restricting the trace routability on the substrate. Moreover, a two-piece type of mold is allowed being used to form a number of encapsulation bodies at one time, making the fabrication more productive and cost-effective. Furthermore, the proposed BGA fabrication method can be implemented without having to provide an air outlet in the substrate but allows the resulted encapsulation body to be free of voids to assure the quality of the packages. The proposed BGA fabrication method is therefore more advantageous to use than the prior art.
摘要翻译：提出了一种制造BGA（球栅阵列）封装的方法，该封装采用专门设计的载体作为将半导体芯片封装在衬底上的辅助工具。载体形成有多个腔体，分别用于接收衬底并与注入栅极连通，使得在衬底上不需要注入栅极，从而不限制衬底上的迹线布线性。此外，允许两件式的模具一次用于形成多个包封体，使得制造更加生产和成本有效。此外，可以实现所提出的BGA制造方法，而不必在衬底中提供空气出口，但是允许所得到的封装体没有空隙以确保包装的质量。因此，提出的BGA制造方法比现有技术更有利于使用。

10. 发明授权

US06621150B1 Lead frame adaptable to the trend of IC packaging 有权
标题翻译：引线框架适应IC封装的趋势
公开(公告)号：US06621150B1
公开(公告)日：2003-09-16
申请号：US10193530
申请日：2002-07-10
申请人： Yvonne Lee , Chien-Ping Huang , Han-Ping Pu
发明人： Yvonne Lee , Chien-Ping Huang , Han-Ping Pu
IPC分类号： H01L23495
CPC分类号： H01L23/4951 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： Conventional configuration of a lead frame, particularly a lead frame in a Lead-on-Chip package, is substituted by one having inward ends of leads thereof arranged in unprecedented ways, resulting in bigger gap between any two adjacent inward ends of inner leads, leading to bigger Inner Lead Pitch of a lead frame in which the space available is inherently limited. It is by the new configuration that an IC packaging process can be immunized against the difficulty resulting from too small Inner Lead Pitch of a lead frame, and the bottle neck in the process of packaging an IC subject to the tendency of minimizing the size of an IC can thus be overcome.
摘要翻译：引线框架，特别是芯片上封装的引线框架的传统结构被以前所未有的方式布置的引线框架的内端置换为引线框架，导致内引线的任何两个相邻内端之间的间隙较大到引脚框架的较大的内引脚间距，其中可用的空间固有地受到限制。通过新的配置，IC封装过程可以免受针脚引起的内部引线间距太小的困难，并且在封装IC的过程中瓶颈处于使IC的尺寸最小化的趋势因此可以克服IC。

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