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1. 发明授权

US06753206B2 Dual-chip integrated circuit package with unaligned chip arrangement and method of manufacturing the same 失效
标题翻译：具有未对准芯片布置的双芯片集成电路封装及其制造方法
公开(公告)号：US06753206B2
公开(公告)日：2004-06-22
申请号：US10289796
申请日：2002-11-07
申请人： Chien-Ping Huang , Lian-Cherng Chiang , Michael Chang
发明人： Chien-Ping Huang , Lian-Cherng Chiang , Michael Chang
IPC分类号： H01L2144
CPC分类号： H01L23/4951 , H01L23/3107 , H01L23/49575 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/32014 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48639 , H01L2224/48739 , H01L2224/48839 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/85439 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01079 , H01L2924/10161 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A dual-chip integrated circuit package with unaligned chip arrangement and a method of manufacturing such a dual-chip integrated circuit package are provided. The dual-chip integrated circuit package includes a leadframe having a first set of leads and a second set of leads. The dual-chip integrated circuit package is used to pack two integrated circuit chips in an unaligned chip arrangement, in which the first integrated circuit chip is mounted to one side of the inner part of the first set of leads, and the second integrated circuit chip is mounted to the other side of the same in such a manner as to allow the bonding pads on the second integrated circuit chip to be positioned in the spacing formed between the two sets of leads. This unaligned chip arrangement can help facilitate the wire-bonding process for the bonding pads on the second integrated circuit chip. An encapsulant is used for encapsulating the first integrated circuit chip, the second integrated circuit chip, the first set of bonding wires, the second set of bonding wires, the inner part of the first set of leads, and the inner part of the second set of leads. The particular structure of the dual-chip integrated circuit package allows no restriction to the relative size between the two integrated circuit chips, thus allowing flexible selection for the combination of the two integrated circuit chips. Moreover, the dual-chip integrated circuit package can help save layout space on the circuit board and offers more functionality and storage capacity.
摘要翻译：提供了具有未对准芯片布置的双芯片集成电路封装以及制造这种双芯片集成电路封装的方法。双芯片集成电路封装包括具有第一组引线和第二组引线的引线框架。双芯片集成电路封装用于以未对准的芯片布置来封装两个集成电路芯片，其中第一集成电路芯片安装在第一组引线的内部的一侧，第二集成电路芯片以这样的方式安装到其另一侧，即允许第二集成电路芯片上的接合焊盘定位在两组引线之间形成的间隔中。这种未对准的芯片布置可以帮助促进第二集成电路芯片上的焊盘的引线接合工艺。密封剂用于封装第一集成电路芯片，第二集成电路芯片，第一组接合线，第二组接合线，第一组引线的内部和第二组的内部的领导。双芯片集成电路封装的特定结构不会限制两个集成电路芯片之间的相对尺寸，因此允许灵活选择两个集成电路芯片的组合。此外，双芯片集成电路封装可以帮助节省电路板上的布局空间，并提供更多功能和存储容量。

2. 发明授权

US06498391B1 Dual-chip integrated circuit package with unaligned chip arrangement and method of manufacturing the same 有权
标题翻译：具有未对准芯片布置的双芯片集成电路封装及其制造方法
公开(公告)号：US06498391B1
公开(公告)日：2002-12-24
申请号：US09473308
申请日：1999-12-28
申请人： Chien-Ping Huang , Lian-Cherng Chiang , Michael Chang
发明人： Chien-Ping Huang , Lian-Cherng Chiang , Michael Chang
IPC分类号： H01L23495
CPC分类号： H01L23/4951 , H01L23/3107 , H01L23/49575 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/32014 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48639 , H01L2224/48739 , H01L2224/48839 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/85439 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01079 , H01L2924/10161 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A dual-chip integrated circuit package with unaligned chip arrangement and a method of manufacturing such a dual-chip integrated circuit package are provided. The dual-chip integrated circuit package includes a leadframe having a first set of leads and a second set of leads. The dual-chip integrated circuit package is used to pack two integrated circuit chips in an unaligned chip arrangement, in which the first integrated circuit chip is mounted to one side of the inner part of the first set of leads, and the second integrated circuit chip is mounted to the other side of the same in such a manner as to allow the bonding pads on the second integrated circuit chip to be positioned in the spacing formed between the two sets of leads. This unaligned chip arrangement can help facilitate the wire-bonding process for the bonding pads are the second integrated circuit chip. An encapsulant is used for encapsulating the first integrated circuit chip, the second integrated circuit chip, the set of bonding wires, the second set of bonding wires, the inner part of the first set of leads, and the inner part of the second set of leads. The particular structure of the dual-chip integrated circuit package allows no restriction to the relative size between first two integrated circuit chips, thus allowing flexible selection for the combination of the two integrated circuit chips. Moreover, the dual-chip integrated circuit package are help save layout space on the circuit board and offers more functionality and storage capacity.
摘要翻译：提供了具有未对准芯片布置的双芯片集成电路封装以及制造这种双芯片集成电路封装的方法。双芯片集成电路封装包括具有第一组引线和第二组引线的引线框架。双芯片集成电路封装用于以未对准的芯片布置来封装两个集成电路芯片，其中第一集成电路芯片安装在第一组引线的内部的一侧，第二集成电路芯片以这样的方式安装到其另一侧，即允许第二集成电路芯片上的接合焊盘定位在两组引线之间形成的间隔中。这种未对准的芯片布置可以帮助便于焊接工艺的焊盘是第二个集成电路芯片。密封剂用于封装第一集成电路芯片，第二集成电路芯片，一组接合线，第二组接合线，第一组引线的内部和第二组引线的内部领导。双芯片集成电路封装的特定结构不限制前两个集成电路芯片之间的相对尺寸，从而允许灵活地选择两个集成电路芯片的组合。此外，双芯片集成电路封装有助于节省电路板上的布局空间，并提供更多的功能和存储容量。

3. 发明授权

US06307257B1 Dual-chip integrated circuit package with a chip-die pad formed from leadframe leads 失效
标题翻译：双芯片集成电路封装，带引线框引线形成的芯片焊盘
公开(公告)号：US06307257B1
公开(公告)日：2001-10-23
申请号：US09473310
申请日：1999-12-28
申请人： Chien-Ping Huang , Lian-Cherng Chiang , Wen-Ta Tsai
发明人： Chien-Ping Huang , Lian-Cherng Chiang , Wen-Ta Tsai
IPC分类号： H01L23495
CPC分类号： H01L23/49575 , H01L23/4951 , H01L24/45 , H01L24/48 , H01L2224/32145 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/73265 , H01L2924/00014 , H01L2924/01047 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： A dual-chip integrated circuit (IC) package is provided, which is characterized in the use of a an extending portion formed from the leads of a leadframe to provide firm support to the bonding pads on the chips. The dual-chip integrated circuit package utilizes a leadframe having a first leads and a second leads, with a spacing being defined between the first and second leads; and the first leads is extended toward the spacing to form the extending portion at a downset position with respect to the second plane where the leadframe positions leads. A first integrated circuit chip is mounted on the extending portion in such a manner that the front side thereof is attached to the extending portion; and a second integrated circuit chip is attached to the first integrated circuit chip in a back-to-back manner. The bonding pads on the two integrated circuit chips are electrically connected to the first and second leads via a plurality of bonding wires. The use of the extending portion for the attachment of the two integrated circuit chips can help prevent delamination of the chips and can provide firm support to the bonding pads on the chips so that the chips can be prevented from being cracked during the wire-bonding process. The manufactured integrated circuit package can therefore be more assured in reliability and quality.
摘要翻译：提供了一种双芯片集成电路（IC）封装，其特征在于使用由引线框的引线形成的延伸部分，为芯片上的焊盘提供坚固的支撑。双芯片集成电路封装采用具有第一引线和第二引线的引线框架，间隔限定在第一和第二引线之间; 并且第一引线朝向间隔延伸，以在相对于引线框架位置引导的第二平面处于下降位置处形成延伸部分。第一集成电路芯片以其前侧附接到延伸部分的方式安装在延伸部分上; 并且第二集成电路芯片以背靠背的方式附接到第一集成电路芯片。两个集成电路芯片上的接合焊盘经由多根接合线电连接到第一和第二引线。使用用于连接两个集成电路芯片的延伸部分可以帮助防止芯片的分层，并且可以为芯片上的焊盘提供牢固的支撑，使得可以防止芯片在引线接合过程中被破裂。因此，制造的集成电路封装在可靠性和质量方面可以更加确保。

4. 发明授权

US06777266B2 Dual-chip integrated circuit package and method of manufacturing the same 失效
标题翻译：双芯片集成电路封装及其制造方法相同
公开(公告)号：US06777266B2
公开(公告)日：2004-08-17
申请号：US10441778
申请日：2003-05-19
申请人： Chieh-Ping Huang , Lian-Cherng Chiang , Wen-Ta Tsai
发明人： Chieh-Ping Huang , Lian-Cherng Chiang , Wen-Ta Tsai
IPC分类号： H01L2160
CPC分类号： H01L24/27 , H01L23/49513 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/32014 , H01L2224/32145 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2224/78301 , H01L2224/83192 , H01L2224/85181 , H01L2224/92147 , H01L2224/92247 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/3512 , H01L2924/00015 , H01L2924/00012
摘要： A dual-chip integrated circuit package and a method for manufacturing such a dual-chip integrated circuit package are proposed, which can help prevent the occurrence of cracking and delamination in the chips and the occurrence of voids in the encapsulant during the manufacture process. The dual-chip integrated circuit package is constructed on a leadframe having a plurality of first leads and a plurality of second leads and at least a pair of support members between the first and second leads. Further, the dual-chip integrated circuit package includes at least one support member attached to the front side of the first integrated circuit chip for providing a support to the bonding pads on the second integrated circuit chip; the support member being not smaller in dimension than the area where the bonding pads on the second integrated circuit chip are located. An encapsulant is used for encapsulating the first integrated circuit chip, the second integrated circuit chip, the support members, and inner parts of the first and second leads of the leadframe. Since the support members can provide good support to the bonding pads on the second integrated circuit chip, it can help prevent the chips from being cracked during the manufacture process. The manufactured dual-chip integrated circuit package can be thus reliable in quality.
摘要翻译：提出了一种双芯片集成电路封装和制造这种双芯片集成电路封装的方法，可以帮助防止芯片中的开裂和分层的发生以及制造过程中密封剂中空隙的发生。双芯片集成电路封装构造在具有多个第一引线和多个第二引线的引线框架上，以及在第一和第二引线之间的至少一对支撑构件。此外，双芯片集成电路封装包括附接到第一集成电路芯片的前侧的至少一个支撑构件，用于向第二集成电路芯片上的焊盘提供支撑; 支撑构件的尺寸不小于第二集成电路芯片上的接合焊盘所在的区域。密封剂用于封装第一集成电路芯片，第二集成电路芯片，支撑构件以及引线框架的第一引线和第二引线的内部部分。由于支撑构件可以为第二集成电路芯片上的接合焊盘提供良好的支撑，所以可以帮助防止芯片在制造过程中破裂。制造的双芯片集成电路封装的质量可靠可靠。

5. 发明授权

US06590279B1 Dual-chip integrated circuit package and method of manufacturing the same 有权
公开(公告)号：US06590279B1
公开(公告)日：2003-07-08
申请号：US09470515
申请日：1999-12-22
申请人： Chieh-Ping Huang , Lian-Cherng Chiang , Wen-Ta Tsai
发明人： Chieh-Ping Huang , Lian-Cherng Chiang , Wen-Ta Tsai
IPC分类号： H01L2302
CPC分类号： H01L24/27 , H01L23/49513 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/32014 , H01L2224/32145 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2224/78301 , H01L2224/83192 , H01L2224/85181 , H01L2224/92147 , H01L2224/92247 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/3512 , H01L2924/00015 , H01L2924/00012
摘要： A dual-chip integrated circuit package and a method for manufacturing such a dual-chip integrated circuit package are proposed, which can help prevent the occurrence of cracking and delamination in the chips and the occurrence of voids in the encapsulant during the manufacture process. The dual-chip integrated circuit package is constructed on a leadframe having a plurality of first leads and a plurality of second leads and at least a pair of support members between the first and second leads. Further, the dual-chip integrated circuit package includes at least one support member attached to the front side of the first integrated circuit chip for providing a support to the bonding pads on the second integrated circuit chip; the support member being not smaller in dimension than the area where the bonding pads on the second integrated circuit chip are located. An encapsulant is used for encapsulating the first integrated circuit chip, the second integrated circuit chip, the support members, and inner parts of the first and second leads of the leadframe. Since the support members can provide good support to the bonding pads on the second integrated circuit chip, it can help prevent the chips from being cracked during the manufacture process. The manufactured dual-chip integrated circuit package can be thus reliable in quality.

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