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51. 发明授权

US06779049B2 Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism 有权
标题翻译：具有附加处理单元的对称多处理系统能够访问共享存储器而不在结构上配置地址转换机制
公开(公告)号：US06779049B2
公开(公告)日：2004-08-17
申请号：US09736585
申请日：2000-12-14
申请人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman , Masakazu Suzuoki , Takeshi Yamazaki
发明人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman , Masakazu Suzuoki , Takeshi Yamazaki
IPC分类号： G06F1328
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.
摘要翻译：用于在SMP系统中访问共享存储器的附加处理单元的方法和系统。在一个实施例中，系统包括共享存储器。该系统还包括耦合到共享存储器的多个处理元件。多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。

52. 发明授权

US09043194B2 Method and system for efficient emulation of multiprocessor memory consistency 有权
标题翻译：多处理器内存一致性高效仿真的方法和系统
公开(公告)号：US09043194B2
公开(公告)日：2015-05-26
申请号：US10244434
申请日：2002-09-17
申请人： Ravi Nair , John Kevin O'Brien , Kathryn Mary O'Brien , Peter Howland Oden , Daniel Arthur Prener
发明人： Ravi Nair , John Kevin O'Brien , Kathryn Mary O'Brien , Peter Howland Oden , Daniel Arthur Prener
IPC分类号： G06F9/455 , G06F12/10
CPC分类号： G06F12/1072 , G06F12/1027 , G06F2212/656 , G06F2212/682
摘要： A method (and system) of emulation in a multiprocessor system, includes performing an emulation in which a host multiprocessing system of the multiprocessor system supports a weak consistency model, and the target multiprocessing system of the multiprocessor system supports a strong consistency model.
摘要翻译：多处理器系统中的仿真的方法（和系统）包括执行仿真，其中多处理器系统的主机多处理系统支持弱一致性模型，并且多处理器系统的目标多处理系统支持强一致性模型。

53. 发明授权

US08719548B2 Method and system for efficient emulation of multiprocessor address translation on a multiprocessor 有权
标题翻译：多处理器上多处理器地址转换的高效仿真方法和系统
公开(公告)号：US08719548B2
公开(公告)日：2014-05-06
申请号：US13085873
申请日：2011-04-13
申请人： Erik Richter Altman , Ravi Nair , John Kevin O'Brien , Kathryn Mary O'Brien , Peter Howland Oden , Daniel Arthur Prener , Sumeda Wasudeo Sathaye
发明人： Erik Richter Altman , Ravi Nair , John Kevin O'Brien , Kathryn Mary O'Brien , Peter Howland Oden , Daniel Arthur Prener , Sumeda Wasudeo Sathaye
IPC分类号： G06F9/455 , G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F9/45537 , G06F12/10
摘要： A method (and structure) of mapping a memory addressing of a multiprocessing system when it is emulated using a virtual memory addressing of another multiprocessing system includes accessing a local lookaside table (LLT) on a target processor with a target virtual memory address. Whether there is a “miss” in the LLT is determined and, with the miss determined in the LLT, a lock for a global page table is obtained.
摘要翻译：当使用另一多处理系统的虚拟存储器寻址来仿真多处理系统的存储器寻址时，映射多处理系统的存储器寻址的方法（和结构）包括使用目标虚拟存储器地址访问目标处理器上的本地后视表（LLT）。确定LLT中是否存在“未命中”，并且在LLT中确定的未命中，获得全局页表的锁。

54. 发明授权

US08578351B2 Hybrid mechanism for more efficient emulation and method therefor 有权
标题翻译：用于更高效仿真的混合机制及其方法
公开(公告)号：US08578351B2
公开(公告)日：2013-11-05
申请号：US13311858
申请日：2011-12-06
申请人： Ravi Nair , John Kevin O'Brien , Kathryn Mary O'Brien , Peter Howland Oden , Daniel Arthur Prener
发明人： Ravi Nair , John Kevin O'Brien , Kathryn Mary O'Brien , Peter Howland Oden , Daniel Arthur Prener
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F9/45504
摘要： In a host system, a method for using instruction scheduling to efficiently emulate the operation of a target computing system includes preparing, on the host system, an instruction sequence to interpret an instruction written for execution on the target computing system. An instruction scheduling on the instruction sequence is performed, to achieve an efficient instruction level parallelism, for the host system. A separate and independent instruction sequence is inserted, which, when executed simultaneously with the instruction sequence, performs to copy to a separate location a minimum instruction sequence necessary to execute an intent of an interpreted target instruction, the interpreted target instruction being a translation; and modifies the interpreter code such that a next interpretation of the target instruction results in execution of the translated version, thereby removing execution of interpreter overhead.
摘要翻译：在主机系统中，使用指令调度来有效地模拟目标计算系统的操作的方法包括在主机系统上准备指令序列以解释为了在目标计算系统上执行而写入的指令。执行指令序列上的指令调度，以实现主机系统的有效指令级并行性。插入独立且独立的指令序列，当与指令序列同时执行时，执行将执行解释目标指令的意图所必需的最小指令序列复制到单独的位置，解释的目标指令是转换; 并修改解释器代码，使得目标指令的下一个解释导致翻译版本的执行，从而消除解释器开销的执行。

55. 发明授权

US08201165B2 Virtualizing the execution of homogeneous parallel systems on heterogeneous multiprocessor platforms 有权
标题翻译：虚拟化异构多处理器平台上的并行并行系统的执行
公开(公告)号：US08201165B2
公开(公告)日：2012-06-12
申请号：US11618944
申请日：2007-01-02
申请人： Ravi Nair
发明人： Ravi Nair
IPC分类号： G06F9/455
CPC分类号： G06F9/5077 , G06F9/45533 , G06F9/4856 , G06F9/505 , G06F11/1484 , G06F11/203 , G06F11/2043 , Y02D10/22 , Y02D10/24 , Y02D10/26 , Y02D10/28 , Y02D10/32 , Y02D10/36
摘要： A method of virtual processing includes running a virtual processor (1), which when the virtual processor (1) encounters a faulting instruction unmaps the virtual processor (1) from the physical processor (A), and generates a list of other of the physical processors that could execute the instruction. Then determines if one of the other of the physical processors in the list is currently idle, and when one of the other of the physical processors in the list is determined to be currently idle, maps the virtual processor (1) to a physical processor (B) which is the one of the other of the physical processors in the list that was determined to be currently idle.
摘要翻译：一种虚拟处理方法包括：运行虚拟处理器（1），当虚拟处理器（1）遇到故障指令从物理处理器（A）解除虚拟处理器（1）时，虚拟处理器（1）产生一个物理可执行指令的处理器。然后确定列表中的另一个物理处理器当前是否处于空闲状态，并且当列表中的另一个物理处理器中的一个被确定为当前空闲时，将虚拟处理器（1）映射到物理处理器 B）是列表中被确定为当前空闲的另一个物理处理器之一。

56. 发明授权

US08108843B2 Hybrid mechanism for more efficient emulation and method therefor 有权
标题翻译：用于更高效仿真的混合机制及其方法
公开(公告)号：US08108843B2
公开(公告)日：2012-01-31
申请号：US10244682
申请日：2002-09-17
申请人： Ravi Nair , John Kevin O'Brien , Kathryn Mary O'Brien , Peter Howland Oden , Daniel Arthur Prener
发明人： Ravi Nair , John Kevin O'Brien , Kathryn Mary O'Brien , Peter Howland Oden , Daniel Arthur Prener
IPC分类号： G06F9/45
CPC分类号： G06F9/45504
摘要： A method (and system) for performing an emulation of an operation of a target computing system, includes interpreting a target instruction, recognizing an unused capacity of a host system when the host system is interpreting the instruction, and performing a translation of the instruction without increasing a time of interpreting the instruction.
摘要翻译：一种用于执行目标计算系统的操作的仿真的方法（和系统）包括解释目标指令，当主机系统解释指令时识别主机系统的未使用容量，并且在没有增加解释说明的时间。

57. 发明授权

US07844446B2 Method and system for multiprocessor emulation on a multiprocessor host system 失效
标题翻译：多处理器主机系统上多处理器仿真的方法和系统
公开(公告)号：US07844446B2
公开(公告)日：2010-11-30
申请号：US12388728
申请日：2009-02-19
申请人： Erik Richter Altman , Ravi Nair , John Kevin O'Brien , Kathryn Mary O'Brien , Peter Howland Oden , Daniel Arthur Prener , Sumedh Wasudeo Sathaye
发明人： Erik Richter Altman , Ravi Nair , John Kevin O'Brien , Kathryn Mary O'Brien , Peter Howland Oden , Daniel Arthur Prener , Sumedh Wasudeo Sathaye
IPC分类号： G06F9/455
CPC分类号： G06F9/4881 , G06F9/45537 , G06F2209/483
摘要： A method (and system) for executing a multiprocessor program written for a target instruction set architecture on a host computing system having a plurality of processors designed to process instructions of a second instruction set architecture, includes representing each portion of the program designed to run on a processor of the target computing system as one or more program threads to be executed on the host computing system.
摘要翻译：一种用于执行在具有设计成处理第二指令集架构的指令的多个处理器的主机计算系统上针对目标指令集架构编写的多处理器程序的方法（和系统），包括表示程序的每个部分被设计为运行目标计算系统的处理器作为要在主机计算系统上执行的一个或多个程序线程。

58. 发明授权

US07725692B2 Compact representation of instruction execution path history 失效
标题翻译：指令执行路径历史的紧密表示
公开(公告)号：US07725692B2
公开(公告)日：2010-05-25
申请号：US11743457
申请日：2007-05-02
申请人： Ravi Nair
发明人： Ravi Nair
IPC分类号： G06F7/38
CPC分类号： G06F9/3844 , G06F9/322 , G06F9/3804
摘要： A method of representing instruction execution path history is provided. The method in one aspect may include gathering information associated with a current instruction, the information including at least a target address. Previously computed bits representing execution path history is modified and hashed based on the target address, to compute current execution path history.
摘要翻译：提供了一种表示指令执行路径历史的方法。一方面的方法可以包括收集与当前指令相关联的信息，所述信息至少包括目标地址。先前计算的表示执行路径历史的比特根据目标地址进行修改和散列，以计算当前执行路径历史。

59. 发明授权

US07627742B2 Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system 失效
标题翻译：当处理器在信息处理系统中遇到低置信度分支时，通过节流指令获取来节省功率的方法和装置
公开(公告)号：US07627742B2
公开(公告)日：2009-12-01
申请号：US11733589
申请日：2007-04-10
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Michael Karl Gschwind , Ravi Nair , Robert Alan Philhower , Wolfram Sauer , Raymond Cheung Yeung
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Michael Karl Gschwind , Ravi Nair , Robert Alan Philhower , Wolfram Sauer , Raymond Cheung Yeung
IPC分类号： G06F1/32
CPC分类号： G06F9/3844 , G06F1/3203 , G06F9/3802 , G06F9/3806
摘要： An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions.
摘要翻译：一种信息处理系统包括处理器，每当对分支指令队列中存储的分支指令的分支预测中的不准确性或缺乏置信度的不准确性或缺乏置信度超过预定的不准确度或误差的阈值置信水平时，可以节制指令获取器。以这种方式，当处理器可能会错误地预测分支指令的结果时，获取操作减慢以节省处理器功率。当处理器可能正确预测分支指令的结果时，获取操作将返回全速。

60. 发明申请

US20080294944A1 PROCESSOR BUS FOR PERFORMANCE MONITORING WITH DIGESTS 失效
标题翻译：处理器总线，用于与DIGESTS进行性能监控
公开(公告)号：US20080294944A1
公开(公告)日：2008-11-27
申请号：US12186481
申请日：2008-08-05
申请人： HILLERY C. HUNTER , Ravi Nair
发明人： HILLERY C. HUNTER , Ravi Nair
IPC分类号： G06F11/00 , G06F9/30
CPC分类号： G06F11/3409 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A method for monitoring event occurrences from a plurality of processor units at a centralized location via a dedicated bus coupled between the plurality of processor units and the centralized location. In particular, the method comprises receiving, at the centralized location, data indicative of cumulative events occurring at one of the processor units, and storing the data in a first temporary memory. The data is then stored in a register based on a tag identifier affixed to the data in an instance where the tag identifier provides indicia of one of the plurality of processor units.
摘要翻译：一种用于经由耦合在所述多个处理器单元和所述集中位置之间的专用总线来监视来自集中位置的多个处理器单元的事件发生的方法。特别地，该方法包括在集中位置处接收指示在一个处理器单元处发生的累积事件的数据，以及将数据存储在第一临时存储器中。然后，在标签标识符提供多个处理器单元之一的标记的情况下，将数据基于附加到数据的标签标识符存储在寄存器中。

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