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51. 发明授权

US07577882B2 Semiconductor integrated circuit including memory macro 有权
标题翻译：半导体集成电路包括内存宏
公开(公告)号：US07577882B2
公开(公告)日：2009-08-18
申请号：US11998602
申请日：2007-11-30
申请人： Marefusa Kurumada , Hironori Akamatsu
发明人： Marefusa Kurumada , Hironori Akamatsu
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C29/812
摘要： The present invention provides a semiconductor integrated circuit having area efficiency and repair efficiency improved by sharing a redundant memory macro among a plurality of SRAM macros. Each of the plurality of memory macros 1A1 and 1A2 includes a memory cell array 1A-3 connected to word lines WL1 to WL32 and bit lines and a redundant circuit that replaces a defective bit line of the memory cell array to a normal bit line and a redundant bit line BLA65 and outputs defect information to a redundant signal line RA. The redundant memory macro 2A includes a redundant memory cell array connected to redundant word lines and the redundant bit line, and a first word line connection circuit that connects a word line corresponding to a memory macro to be repaired and disconnects a word line corresponding to a normal memory macro from the redundant word line.
摘要翻译：本发明提供了一种通过在多个SRAM宏中共享冗余存储器宏来提高区域效率和修复效率的半导体集成电路。多个存储器宏1A1和1A2中的每一个包括连接到字线WL1至WL32的存储单元阵列1A-3和位线，以及将存储单元阵列的有缺陷位线替换为正常位线的冗余电路，以及冗余位线BLA65，并将缺陷信息输出到冗余信号线RA。冗余存储器宏2A包括连接到冗余字线和冗余位线的冗余存储单元阵列，以及第一字线连接电路，其连接对应于要修复的存储器宏的字线，并断开对应于来自冗余字线的正常内存宏。

52. 发明申请

US20060050586A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060050586A1
公开(公告)日：2006-03-09
申请号：US11218601
申请日：2005-09-06
申请人： Hirohisa Ohtsuki , Kazuo Itoh , Katsuji Satomi , Hironori Akamatsu
发明人： Hirohisa Ohtsuki , Kazuo Itoh , Katsuji Satomi , Hironori Akamatsu
IPC分类号： G11C7/02
CPC分类号： G11C7/065 , G11C7/08 , G11C7/14 , G11C7/227 , G11C11/419 , H01L27/1104
摘要： A memory array, a sense amplifier circuit, a replica circuit and a dummy cell are disposed. The replica circuit has the same elements as memory cells, and includes plural replica cells which output a signal whose level corresponds to the number of stages provided to a common replica bit line. The dummy cell is connected as a load with the common replica bit line. The source of a drive transistor of the dummy cell is connected with a power source which is at the High level. This suppresses a leak current flowing from a replica bit line to the dummy cell.
摘要翻译：存储器阵列，读出放大器电路，复制电路和虚设单元。复制电路具有与存储单元相同的元件，并且包括输出其电平对应于提供给公共复制位线的级数的信号的多个复制单元。虚拟单元作为负载与公共副本位线连接。虚拟单元的驱动晶体管的源极与处于高电平的电源连接。这抑制了从复制位线流向虚拟电池的泄漏电流。

53. 发明授权

US06831356B2 Memory macro and semiconductor integrated circuit 有权
公开(公告)号：US06831356B2
公开(公告)日：2004-12-14
申请号：US10701422
申请日：2003-11-06
申请人： Yutaka Terada , Hironori Akamatsu
发明人： Yutaka Terada , Hironori Akamatsu
IPC分类号： H01L2352
CPC分类号： H01L27/0203 , G11C5/025 , H01L27/105
摘要： A memory array portion, a connection circuit serving as an interface of the memory array portion and a signal wiring connecting the memory array portion to the connection circuit are provided. Mesh wirings comprising first and second wiring layers are provided on the memory array portion. The connection circuit is connected to a plurality of signal lines comprising a third wiring layer provided on the memory array portion, the connection circuit or the signal wiring, through an intermediate wiring comprising the second wiring layer. The region where the intermediate wiring is provide on the memory array portion or on the signal wiring, and the mesh wiring comprising the second wiring layer is not present on the region where the intermediate wiring is provided.

54. 发明授权

US06473873B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06473873B1
公开(公告)日：2002-10-29
申请号：US09206534
申请日：1998-12-07
申请人： Hironori Akamatsu , Toru Iwata
发明人： Hironori Akamatsu , Toru Iwata
IPC分类号： G06F1100
CPC分类号： G11C29/10 , G11C29/36 , H01L27/10897
摘要： A semiconductor memory device includes: a memory block including a plurality of memory cells; and a test pattern generation circuit for generating at least one test pattern for use in testing the memory block. A first bus line for coupling the memory block and the test pattern generation circuit has a larger width than that of a second bus line for coupling the memory block to the exterior of the semiconductor memory device.
摘要翻译：半导体存储器件包括：包括多个存储器单元的存储器块; 以及测试图案生成电路，用于生成用于测试存储块的至少一个测试图案。用于耦合存储块和测试图案生成电路的第一总线具有比用于将存储块耦合到半导体存储器件的外部的第二总线的宽度大的宽度。

55. 发明授权

US06417700B1 Voltage level detection circuit and voltage level detection method 失效
标题翻译：电压电平检测电路和电压电平检测方法
公开(公告)号：US06417700B1
公开(公告)日：2002-07-09
申请号：US09978676
申请日：2001-10-18
申请人： Takashi Hirata , Hironori Akamatsu , Satoshi Takahashi , Yoshihide Komatsu , Yutaka Terada , Hirokazu Sugimoto
发明人： Takashi Hirata , Hironori Akamatsu , Satoshi Takahashi , Yoshihide Komatsu , Yutaka Terada , Hirokazu Sugimoto
IPC分类号： H03K5153
CPC分类号： H03M1/0626 , H03M1/0872 , H03M1/145 , H03M1/34 , H03M1/36
摘要： In the circuit for detecting the voltage level of an analog signal, a conversion circuit converts an analog signal to digital signals by comparing the voltage level of the analog signal with a plurality of reference potentials. A filter circuit matches timings of at least either rising edges or falling edges of the digital signals with each other. This prevents malfunction in the voltage level detection.
摘要翻译：在用于检测模拟信号的电压电平的电路中，转换电路通过将模拟信号的电压电平与多个参考电位进行比较来将模拟信号转换成数字信号。滤波器电路将数字信号的上升沿或下降沿的至少任一个彼此的定时相匹配。这可以防止电压电平检测中的故障。

56. 发明授权

US06400637B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06400637B1
公开(公告)日：2002-06-04
申请号：US09673419
申请日：2000-10-18
申请人： Hironori Akamatsu , Toru Iwata , Makoto Kojima
发明人： Hironori Akamatsu , Toru Iwata , Makoto Kojima
IPC分类号： G11C800
CPC分类号： G11C8/14 , G11C8/12 , G11C11/4087
摘要： Four memory banks (10 to 13), each having a hierarchical word line structure, are provided. If a particular mode for one of the memory banks is specified by a control packet (PKT), a mode recognizer (15) produces the leading edges of change-of-sub-word enable (SEN0-3) and change-of-column enable (CEN-3) signals with the logical level of change-of-main-word enable (MEN0-3) signal fixed. This is done to make activated ones of sub-word and column select lines changeable in each of the memory banks with the same main word line still selected. In this manner, the row access speeds increase for the respective memory banks.
摘要翻译：提供四个具有分层字线结构的存储体（10至13）。如果通过控制分组（PKT）指定存储器组中的一个的特定模式，则模式识别器（15）产生子字改变使能（SEN0-3）和列更改的前沿使能（CEN-3）信号与主字使能（MEN0-3）信号的逻辑电平固定。这样做是为了使具有相同主字线仍被选择的每个存储体中的子字和列选择线的激活的一个可变。以这种方式，各存储体的行访问速度增加。

57. 发明授权

US6118309A Semiconductor circuit 失效
标题翻译：半导体电路
公开(公告)号：US6118309A
公开(公告)日：2000-09-12
申请号：US121191
申请日：1998-07-23
申请人： Hironori Akamatsu , Toru Iwata
发明人： Hironori Akamatsu , Toru Iwata
IPC分类号： G11C8/10 , H03K19/00 , H03K19/0948 , H03K19/096
CPC分类号： H03K19/0963 , G11C8/10 , H03K19/0016 , H03K19/0948
摘要： A semiconductor circuit includes an input, an output, and a first transistor and a second transistor coupled in series to a power source. The first transistor is coupled closer to the power source than the second transistor is, and the first transistor has a higher threshold voltage than a threshold voltage of the second transistor. The semiconductor circuit further includes a capacitor which is coupled between the first transistor and the second transistor.
摘要翻译：半导体电路包括输入，输出以及串联耦合到电源的第一晶体管和第二晶体管。第一晶体管比第二晶体管更靠近电源耦合，并且第一晶体管具有比第二晶体管的阈值电压更高的阈值电压。半导体电路还包括耦合在第一晶体管和第二晶体管之间的电容器。

58. 发明授权

US5970018A Semiconductor integrated circuit and decode circuit for memory 失效
标题翻译：半导体集成电路和存储器解码电路
公开(公告)号：US5970018A
公开(公告)日：1999-10-19
申请号：US974560
申请日：1997-11-19
申请人： Toru Iwata , Hironori Akamatsu
发明人： Toru Iwata , Hironori Akamatsu
IPC分类号： G11C8/10 , G11C8/00
CPC分类号： G11C8/10
摘要： In plural internal logic circuits, plural transistors having the same function are merged into a single merged transistor. This merged transistor is interposed between a ground and a virtual ground line connected with a ground node of an inverter included in each of the internal logic circuits, and has a threshold voltage higher than a threshold voltage of a transistor included in each inverter. The merged transistor is controlled in accordance with a block selecting signal. Since the merged transistor is merged among the internal logic circuits, its gate width can be set larger, resulting in attaining a high speed operation of each inverter. During a standby, a leakage current can be suppressed since the merged transistor is in an off-state. During an operation, a leakage current can be suppressed in an unselected circuit block since the merged transistor is in an off-state. Accordingly, while suppressing increase of the circuit area, the internal logic circuits can attain a high speed operation and a leakage current can be minimized during both a standby and an operation.
摘要翻译：在多个内部逻辑电路中，具有相同功能的多个晶体管被合并成单个合并晶体管。该合并后的晶体管被插入在与各内部逻辑电路中包含的逆变器的接地节点连接的地与虚拟地线之间，并且具有比每个逆变器所包含的晶体管的阈值电压高的阈值电压。合并晶体管根据块选择信号进行控制。由于合并的晶体管在内部逻辑电路之间合并，所以其栅极宽度可以设定得更大，从而达到每个逆变器的高速运行。在待机期间，由于合并晶体管处于截止状态，所以可以抑制泄漏电流。在操作期间，由于合并晶体管处于截止状态，所以在未选择的电路块中可以抑制漏电流。因此，在抑制电路面积增加的同时，内部逻辑电路能够实现高速运转，并且在备用和运转两者期间可以使漏电流最小化。

59. 发明授权

US5933050A Semiconductor circuit 失效
标题翻译：半导体电路
公开(公告)号：US5933050A
公开(公告)日：1999-08-03
申请号：US862017
申请日：1997-05-22
申请人： Hironori Akamatsu , Toru Iwata
发明人： Hironori Akamatsu , Toru Iwata
IPC分类号： G11C8/10 , H03K19/00 , H03K19/0948 , H03K19/096
CPC分类号： H03K19/0963 , G11C8/10 , H03K19/0016 , H03K19/0948
摘要： A semiconductor circuit includes an input, an output, and a first transistor and a second transistor coupled in series to a power source. The first transistor is coupled closer to the power source than the second transistor is, and the first transistor has a higher threshold voltage than a threshold voltage of the second transistor. The semiconductor circuit further includes a capacitor which in coupled between the first transistor and the second transistor.
摘要翻译：半导体电路包括输入，输出以及串联耦合到电源的第一晶体管和第二晶体管。第一晶体管比第二晶体管更靠近电源耦合，并且第一晶体管具有比第二晶体管的阈值电压更高的阈值电压。半导体电路还包括耦合在第一晶体管和第二晶体管之间的电容器。

60. 发明授权

US5150327A Semiconductor memory and video signal processing circuit having the same 失效
标题翻译：半导体存储器和视频信号处理电路具有相同的功能
公开(公告)号：US5150327A
公开(公告)日：1992-09-22
申请号：US752919
申请日：1991-08-29
申请人： Junko Matsushima , Hironori Akamatsu
发明人： Junko Matsushima , Hironori Akamatsu
IPC分类号： G11C7/10
CPC分类号： G11C7/1018
摘要： A semiconductor memory includes a writing circuit for dividing data continuously supplied to a serial data input circuit into a plurality of bits, a serial data output circuit for continuously providing data read out a plurality of bits a a time by a reading circuit, a memory cell array including a column decoder and a row decoder, column and row address buffers for instructing addresses for a plurality of bits at a time to the respective column and row decoders, an address generator, and a circuit provided between the address generator and column decoder and including a read column address generator, a write column address generator and a column address control circuit for switching read and write column address generated from the read and write column address generators, wherein address identity data are simultaneously inputted and outputted through switching of internal column addresses for reading and writing.
摘要翻译：半导体存储器包括用于将连续提供给串行数据输入电路的数据分割为多个位的写入电路，用于通过读取电路连续提供读出多个位的数据的串行数据输出电路，存储单元阵列包括列解码器和行解码器，列和行地址缓冲器，用于一次指示针对各个列和行解码器的多个位的地址，地址生成器和设置在地址生成器和列解码器之间的电路，并且包括读列地址发生器，写列地址发生器和用于切换从读和列列地址生成器生成的读和写列地址的列地址控制电路，其中，通过切换内部列地址来同时输入和输出地址标识数据，读写。

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