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51. 发明授权

US06611473B2 Power-saving modes for memories 失效
公开(公告)号：US06611473B2
公开(公告)日：2003-08-26
申请号：US10061620
申请日：2002-02-01
申请人： Ali Al-Shamma , Takao Akaogi , Lee Cleveland
发明人： Ali Al-Shamma , Takao Akaogi , Lee Cleveland
IPC分类号： G11C700
CPC分类号： G11C7/00 , G11C7/1006 , G11C7/1072 , G11C2207/2263
摘要： A system and a method are disclosed for providing a power saving mode during reading a memory device. A new memory content is read from the memory and, before being put at the memory output bus, is compared with the previously read memory content, which is currently on the output bus of the memory device. If the result of the comparison indicates that more than half of the memory output bits have to be toggled in order to put the new memory content on the memory output bus, the new data is inverted internally in order to reduce the number of output pins toggles. Then, the memory device sends a signal to the microprocessor or microcontroller indicating that the new data is inverted, and that the new data has to be inverted back before being put on the memory output bus.

52. 发明授权

US06550028B1 Array VT mode implementation for a simultaneous operation flash memory device 失效
标题翻译：阵列VT模式实现用于同时运行的闪存设备
公开(公告)号：US06550028B1
公开(公告)日：2003-04-15
申请号：US09421470
申请日：1999-10-19
申请人： Takao Akaogi , Tiao-Hua Kuo , Fan W. Lai
发明人： Takao Akaogi , Tiao-Hua Kuo , Fan W. Lai
IPC分类号： G11C2900
CPC分类号： G11C29/028 , G11C16/04 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C2029/0403
摘要： An array threshold voltage test mode for a flash memory device is disclosed. During the test mode, a test voltage is routed directly to the gates of the flash memory transistors selected by a given address. If the test voltage causes the selected transistors to change state by crossing their threshold voltage level, the change will be reflected in the data outputs of the device. By varying the test voltages and the addresses and monitoring the data outputs, the array threshold voltage distribution can be determined for the entire device.
摘要翻译：公开了一种用于闪存器件的阵列阈值电压测试模式。在测试模式期间，测试电压直接路由到由给定地址选择的闪存晶体管的栅极。如果测试电压导致所选择的晶体管通过交叉其阈值电压电平来改变状态，则该变化将反映在器件的数据输出中。通过改变测试电压和地址并监视数据输出，可以为整个器件确定阵列阈值电压分布。

53. 发明授权

US06400638B1 Wordline driver for flash memory read mode 有权
标题翻译：用于闪存读取模式的字线驱动程序
公开(公告)号：US06400638B1
公开(公告)日：2002-06-04
申请号：US09680344
申请日：2000-10-05
申请人： Shigekazu Yamada , Takao Akaogi , Colin S. Bill
发明人： Shigekazu Yamada , Takao Akaogi , Colin S. Bill
IPC分类号： G11C800
CPC分类号： G11C16/08 , G11C8/08
摘要： The present invention discloses a wordline voltage regulation method and system that provides a predetermined voltage as a wordline voltage to a plurality of wordlines during read mode. A supply voltage (Vcc) is regulated and temperature compensated by a wordline driver circuit to provide the predetermined voltage that is lower in magnitude than the magnitude of the supply voltage (Vcc). The wordline driver circuit is activated by an activation circuit when the read operation is initiated. During the read operation, the wordline driver circuit maintains the predetermined voltage during variations in the supply voltage (Vcc) as well as variations in a process load supplied by the wordline driver circuit.
摘要翻译：本发明公开了一种在读取模式期间向多个字线提供预定电压作为字线电压的字线电压调节方法和系统。电源电压（Vcc）由字线驱动器电路调节和温度补偿，以提供比电源电压（Vcc）的幅度更低的预定电压。当启动读取操作时，字线驱动器电路由激活电路激活。在读取操作期间，字线驱动器电路在电源电压（Vcc）的变化期间维持预定电压以及由字线驱动器电路提供的工艺负载的变化。

54. 发明授权

US06353566B1 System and method for tracking sensing speed by an equalization pulse for a high density flash memory device 有权
标题翻译：用于通过高密度闪存器件的均衡脉冲跟踪感测速度的系统和方法
公开(公告)号：US06353566B1
公开(公告)日：2002-03-05
申请号：US09663552
申请日：2000-09-18
申请人： Takao Akaogi , Kazuhiro Kurihara , Thomas T. Shieh
发明人： Takao Akaogi , Kazuhiro Kurihara , Thomas T. Shieh
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C16/24 , G11C16/26
摘要： A sense amplifier output equalization circuit for a variable operating voltage high density flash memory device is disclosed. The equalization circuit compensates for the varying sensing speeds due to the varying operating voltages by variably adjusting the duration of an equalization pulse which is used to equalize the output stage of the sense amplifier to the input stage.
摘要翻译：公开了一种用于可变工作电压高密度闪速存储器件的读出放大器输出均衡电路。均衡电路通过可变地调节用于均衡感测放大器的输出级与输入级的均衡脉冲的持续时间来补偿由于变化的工作电压引起的变化的感测速度。

55. 发明授权

US06307787B1 Burst read incorporating output based redundancy 失效
标题翻译：突发读取并入基于输出的冗余
公开(公告)号：US06307787B1
公开(公告)日：2001-10-23
申请号：US09724669
申请日：2000-11-28
申请人： Ali K. Al-Shamma , Takao Akaogi
发明人： Ali K. Al-Shamma , Takao Akaogi
IPC分类号： G11C1604
CPC分类号： G11C16/26 , G11C15/00 , G11C15/046
摘要： A device for performing redundant reading in a flash memory is provided. The device includes arrays of regular memory cells and arrays of redundant memory cells. Some of the regular memory cells may be defective and those will have defective addresses. A regular sense amplifier will read the regular memory cells at their accessed address while at a time no later a redundant sense amplifier will read the redundant memory cells. A first array of CAM's will store the defective addresses of the defective memory cells while a second array of CAM's will store the input/output designators of the defective memory cells. Address matching circuitry will compare the accessed addresses with the defective addresses to determine whether the accessed address is defective. Before the end of the reading intervals of the sense amplifiers, decoding circuitry will decode the input/output designators of both the defective and non-defective memory cells. A multi-bit multiplexer stage will output either the contents of the regular memory cell or, if the address is defective, the contents of the redundant memory cell. The contents will be applied to the multiplexer output corresponding to the input/output designator of the memory cell.
摘要翻译：提供了一种用于在闪存中执行冗余读取的设备。该器件包括常规存储单元阵列和冗余存储单元阵列。一些常规存储单元可能是有缺陷的，并且那些存储单元将具有缺陷地址。常规读出放大器将在其访问地址读取常规存储单元，而不久之后，冗余读出放大器将读取冗余存储单元。 CAM的第一阵列将存储缺陷存储单元的缺陷地址，而CAM的第二阵列将存储有缺陷存储单元的输入/输出指示符。地址匹配电路将比较访问的地址与缺陷地址，以确定访问的地址是否有缺陷。在读出放大器的读取间隔结束之前，解码电路将解码有缺陷和无缺陷存储单元的输入/输出指示符。多位复用器级将输出常规存储单元的内容，或者如果地址有缺陷，则会输出冗余存储单元的内容。内容将应用于与存储单元的输入/输出指示符相对应的多路复用器输出。

56. 发明授权

US5870337A Flash-erasable semiconductor memory device having an improved reliability 失效
标题翻译：闪存可擦除半导体存储器件具有改进的可靠性
公开(公告)号：US5870337A
公开(公告)日：1999-02-09
申请号：US986575
申请日：1997-12-05
申请人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
发明人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on the floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
摘要翻译：闪存可擦除半导体存储器件具有存储单元阵列，其包括多个存储单元晶体管，每个存储单元晶体管具有用于存储信息的绝缘浮动栅极和设置在浮置栅极上的控制电极，其中闪存可擦除半导体存储器件包括写入控制电路提供写入控制信号时，写入信息。写入控制电路产生控制信号，使得漏极控制信号的前沿出现在栅极控制信号的前沿之后。此外，栅极控制电路关闭栅极控制信号，使得栅极控制信号的后沿出现在漏极控制信号的后沿之后。

57. 发明授权

US5867430A Bank architecture for a non-volatile memory enabling simultaneous reading and writing 失效
标题翻译：用于非易失性存储器的银行体系结构，可同时读写
公开(公告)号：US5867430A
公开(公告)日：1999-02-02
申请号：US772131
申请日：1996-12-20
申请人： Johnny C. Chen , Chung K. Chang , Tiao-Hua Kuo , Takao Akaogi
发明人： Johnny C. Chen , Chung K. Chang , Tiao-Hua Kuo , Takao Akaogi
IPC分类号： G11C16/02 , G11C16/06 , G11C16/10 , G06F12/00 , G11C7/00
CPC分类号： G11C16/10 , G11C2216/22
摘要： A flash memory device is divided into two or more banks. Each bank includes a number of sectors. Each sector includes flash memory cells. Each bank has a decoder that selectively receives an address from an input address buffer or from an internal address sequencer controlled by an internal state machine. The output data for each bank can be communicated to a read sense amplifier or a verify sense amplifier. The read sense amplifier connects to the output buffer while the verify sense amplifier connects to the state machine. When one bank receives a write command, the internal state machine takes control and starts the program or erase operation. While one bank is busy with a program or erase operation, the other bank can be accessed for a read operation. Power is supplied for each of the read and write operations via an internal multiplexed multi power supply source that provides an amount of power needed based on the memory operation being performed.
摘要翻译：闪存器件分为两个或更多个存储体。每个银行都包括一些行业。每个扇区包括闪存单元。每个存储体都有一个解码器，可选择性地从输入地址缓冲区或由内部状态机控制的内部地址排序器接收地址。每个存储体的输出数据可以传送到读出读出放大器或校验读出放大器。读出放大器连接到输出缓冲器，而验证放大器连接到状态机。当一个银行收到一个写入命令时，内部状态机将进行控制并启动程序或擦除操作。当一个银行忙于编程或擦除操作时，可以访问另一个存储体进行读取操作。通过内部复用多电源提供每个读取和写入操作的电源，该内部复用多电源提供基于正在执行的存储器操作所需的功率量。

58. 发明授权

US5761127A Flash-erasable semiconductor memory device having an improved reliability 失效
公开(公告)号：US5761127A
公开(公告)日：1998-06-02
申请号：US978976
申请日：1992-11-20
申请人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
发明人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

59. 发明授权

US5590074A Nonvolatile semiconductor memory 失效
公开(公告)号：US5590074A
公开(公告)日：1996-12-31
申请号：US466732
申请日：1995-06-06
申请人： Takao Akaogi , Masanobu Yoshida , Yasushige Ogawa , Yasushi Kasa , Shouichi Kawamura
发明人： Takao Akaogi , Masanobu Yoshida , Yasushige Ogawa , Yasushi Kasa , Shouichi Kawamura
IPC分类号： G11C16/26 , G11C16/30 , G11C29/04 , G11C11/34
CPC分类号： G11C16/30 , G11C16/26 , G11C29/04 , G06F2201/81
摘要： A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors. The semiconductor memory employs an arrangement for effectively using a plurality of source voltages and applying a verify voltage to sense amplifiers and word lines, a write verify arrangement for detecting an output of the sense amplifiers, an arrangement for comparing an output of the sense amplifiers with a reference value to determine whether or not a written state of the memory cell transistors is acceptable, an arrangement for adjusting an output of the sense amplifiers with use of inverters and transistors in response to a current flowing to the memory cell transistors, to improve a drive speed of the sense amplifiers, an internal source voltage generating arrangement using an n-channel depletion transistor connected to an external source voltage (Vcc), the gate of the transistor being connected to a low source voltage (Vss) to provide an internal source voltage (Vci), a combination of an arrangement for dropping the external source voltage (Vcc) for read to a predetermined value to drive a read circuit in the memory and an arrangement for dropping an external voltage (Vpp) for write, to generate a word line potential for a verify-after-write operation, an arrangement for setting a reference voltage (Vref) as a lower threshold (Vth) allowed for cell transistors (11.sub.00 to 11.sub.22), and comparing the voltage of a data bus (13) with the reference voltage (Vref), to simultaneously carry out an erase-verify operation on all memory cell transistors, and a pre-read arrangement for accessing the next address during a read time of the sense amplifiers, to improve a read speed.

60. 发明授权

US5428580A Nonvolatile semiconductor memory having an address-transition-detection circuit 失效
标题翻译：具有地址转换检测电路的非易失性半导体存储器
公开(公告)号：US5428580A
公开(公告)日：1995-06-27
申请号：US176431
申请日：1994-01-03
申请人： Hiromi Kawashima , Takao Akaogi
发明人： Hiromi Kawashima , Takao Akaogi
IPC分类号： G11C16/02 , G11C5/14 , G11C16/06 , G11C16/30 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C16/3445 , G11C16/30 , G11C16/3436 , G11C16/3459 , G11C5/143
摘要： The object of the present invention is to provide a nonvolatile memory wherein stored data can be properly read at power-on even if the memory is designed to achieve faster operating speeds by performing operations such as bit line charge-up by detecting an address signal change and the turning-on of the power. A nonvolatile semiconductor memory in which, after a write or an erase operation, a read operation for verification is performed by applying a voltage at a first verification level V2, which is lower than an applied voltage for a normal read operation, or a voltage at a second verification level V3, which is higher than the applied voltage V1, the nonvolatile semiconductor memory comprising: an address-transition-detection circuit 1; a supply voltage detection circuit 3 for generating an initialization transition signal at the rise of a supply voltage when the supply voltage has reached a first supply voltage transition threshold level V4 higher than the first verification level V2; and a transition operation circuit 2 for performing operations such as bit line charge-up in accordance with the address transition signal and initialization transition signal.
摘要翻译：本发明的目的是提供一种非易失性存储器，其中存储的数据可以在上电时被适当地读取，即使存储器被设计为通过通过检测地址信号变化来执行诸如位线充电的操作来实现更快的操作速度并开启电源。一种非易失性半导体存储器，其中，在写入或擦除操作之后，通过施加低于正常读取操作的施加电压的第一验证电平V2或者正常读取操作的电压来执行用于验证的读取操作第二验证电平V3高于施加的电压V1，非易失性半导体存储器包括：地址转换检测电路1; 电源电压检测电路3，用于当电源电压达到高于第一验证电平V2的第一电源电压转变阈值电平V4时，在电源电压上升时产生初始化转换信号; 以及用于根据地址转换信号和初始化转换信号执行诸如位线充电的操作的转换操作电路2。

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