专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06353566B1 System and method for tracking sensing speed by an equalization pulse for a high density flash memory device 有权
标题翻译：用于通过高密度闪存器件的均衡脉冲跟踪感测速度的系统和方法
公开(公告)号：US06353566B1
公开(公告)日：2002-03-05
申请号：US09663552
申请日：2000-09-18
申请人： Takao Akaogi , Kazuhiro Kurihara , Thomas T. Shieh
发明人： Takao Akaogi , Kazuhiro Kurihara , Thomas T. Shieh
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C16/24 , G11C16/26
摘要： A sense amplifier output equalization circuit for a variable operating voltage high density flash memory device is disclosed. The equalization circuit compensates for the varying sensing speeds due to the varying operating voltages by variably adjusting the duration of an equalization pulse which is used to equalize the output stage of the sense amplifier to the input stage.
摘要翻译：公开了一种用于可变工作电压高密度闪速存储器件的读出放大器输出均衡电路。均衡电路通过可变地调节用于均衡感测放大器的输出级与输入级的均衡脉冲的持续时间来补偿由于变化的工作电压引起的变化的感测速度。

2. 发明授权

US06359808B1 Low voltage read cascode for 2V/3V and different bank combinations without metal options for a simultaneous operation flash memory device 有权
标题翻译：低电压读取共源共栅，适用于2V / 3V和不同的组合组合，无需金属选项，可同时操作闪存器件
公开(公告)号：US06359808B1
公开(公告)日：2002-03-19
申请号：US09421985
申请日：1999-10-19
申请人： Tien-Min Chen , Kazuhiro Kurihara , Takao Akaogi
发明人： Tien-Min Chen , Kazuhiro Kurihara , Takao Akaogi
IPC分类号： G11C1606
CPC分类号： G11C16/26
摘要： A pre-amplifier portion of a sense amplifier for a dual bank architecture simultaneous operation flash memory device is provided. The sense pre-amplifier circuit includes two inverting amplifiers, the second inverting amplifier providing a feedback loop for the first inverting amplifier. In addition, special “kicker” circuitry raises the sense pre-amplifier's input signal line to its operating level. The combination of inverting amplifiers, feedback loop and level raising circuitry is configured to provide higher bandwidths for the sense pre-amplifier to accommodate low capacitive loading resulting from a small memory bank. The combination is also configured to provide faster raising of the input signal line to operating level to accommodate high capacitive loading resulting from a large memory bank. The combination is also configured to provide increased signal margins at the output of the sense pre-amplifier.
摘要翻译：提供了用于双存储体架构同时操作闪速存储器件的读出放大器的前置放大器部分。感测预放大器电路包括两个反相放大器，第二反相放大器为第一反相放大器提供反馈回路。另外，特殊的“咔icker”电路将感应前置放大器的输入信号线提升到其工作电平。反相放大器，反馈回路和电平提升电路的组合被配置为为感测前置放大器提供更高的带宽以适应由小存储器组成的低容性负载。该组合还被配置为将输入信号线更快地提升到操作电平以适应由大存储器组造成的高容性负载。该组合还被配置为在感测前置放大器的输出处提供增加的信号余量。

3. 发明授权

US6111787A Address transistion detect timing architecture for a simultaneous operation flash memory device 有权
标题翻译：地址转移检测定时架构，用于同时运行的闪存设备
公开(公告)号：US6111787A
公开(公告)日：2000-08-29
申请号：US421776
申请日：1999-10-19
申请人： Takao Akaogi , Kazuhiro Kurihara , Tien-Min Chen
发明人： Takao Akaogi , Kazuhiro Kurihara , Tien-Min Chen
IPC分类号： G11C8/12 , G11C8/18 , G11C16/32 , G11C16/04 , G11C8/00
CPC分类号： G11C16/32 , G11C8/12 , G11C8/18
摘要： An address transition signal generator for a dual bank flash memory device is disclosed. The generator includes signal transition detectors which monitor control signals of the device for transitions in their logical values. Upon detection of a signal transition, the transition detectors send a signal across equidistant signal paths to bank address transition detect signal generator circuits. This results in simultaneous generation of the address transition detect signal from each of the bank address transition detect signal generator circuits.
摘要翻译：公开了一种用于双银行闪存设备的地址转换信号发生器。发生器包括信号转换检测器，其监视器件的控制信号用于其逻辑值中的转换。在检测到信号转换时，转换检测器通过等距信号路径向bank地址转换检测信号发生器电路发送信号。这导致从每个存储体地址转换检测信号发生器电路同时生成地址转换检测信号。

4. 发明授权

US06185128B2 Reference cell four-way switch for a simultaneous operation flash memory device 有权
标题翻译：参考单元四路开关，用于同时运行闪存设备
公开(公告)号：US06185128B2
公开(公告)日：2001-02-06
申请号：US09421984
申请日：1999-10-19
申请人： Tien-Min Chen , Kazuhiro Kurihara , Takao Akaogi
发明人： Tien-Min Chen , Kazuhiro Kurihara , Takao Akaogi
IPC分类号： G11C1604
CPC分类号： G11C16/28 , G11C16/3436 , G11C2216/22
摘要： A flash memory system capable of simultaneous operation comprises upper and lower memory banks of flash memory cells, reference cells generating reference signals, a switch coupled to the reference cells and upper and lower sense amplifiers coupled to the switch and to the upper and lower memory bank, respectively. The switch steers the appropriate reference signal to the appropriate upper sense amplifier along one upper signal line and steers the appropriate reference signal to the appropriate lower sense amplifier along a lower signal line. The upper and lower sense amplifiers generate comparison signals in response to reference signals and data stored in the upper and lower memory bank, respectively.
摘要翻译：能够同时操作的闪速存储器系统包括闪存单元的上部和下部存储器组，产生参考信号的参考单元，耦合到参考单元的开关和耦合到该开关的上部和下部读出放大器以及上部和下部存储器组，分别。开关将适当的参考信号沿着一个上部信号线转向适当的上部读出放大器，并将适当的参考信号沿着较低的信号线转向适当的下部读出放大器。上和下感测放大器响应于分别存储在上部和下部存储体中的参考信号和数据产生比较信号。

5. 发明授权

US6118698A Output multiplexing implementation for a simultaneous operation flash memory device 有权
标题翻译：用于同时运行的闪存设备的输出多路复用实现
公开(公告)号：US6118698A
公开(公告)日：2000-09-12
申请号：US422199
申请日：1999-10-19
申请人： Takao Akaogi , Kazuhiro Kurihara , Tien-Min Chen
发明人： Takao Akaogi , Kazuhiro Kurihara , Tien-Min Chen
IPC分类号： G11C16/26 , G11C16/28 , G11C16/04
CPC分类号： G11C16/26 , G11C16/28
摘要： A flash memory chip including a synchronization circuit for multiplexed sense amplifier output signal paths is disclosed. The synchronization circuit includes a signal generator, sense amplifiers and an output multiplexer. The arrival of data from the sense amplifiers to the output multiplexer is equalized. Equalization is achieved by adjusting the signal path length, and thereby the resistance and capacitance, of the signal paths from the signal generator to the sense amplifiers which carry the signal to cause the sense amplifiers to transmit their data to the output multiplexers.
摘要翻译：公开了一种包括用于复用的读出放大器输出信号路径的同步电路的闪存芯片。同步电路包括信号发生器，读出放大器和输出多路复用器。来自读出放大器的数据到达输出多路复用器是相等的。通过调整信号路径长度，从而从信号发生器到读出放大器的信号路径长度的电阻和电容来实现均衡，该读出放大器承载信号以使读出放大器将其数据传输到输出多路复用器。

6. 发明授权

US06327181B1 Reference cell bitline path architecture for a simultaneous operation flash memory device 有权
标题翻译：用于同时操作闪存器件的参考单元位线路径架构
公开(公告)号：US06327181B1
公开(公告)日：2001-12-04
申请号：US09421775
申请日：1999-10-19
申请人： Takao Akaogi , Tien-Min Chen , Kazuhiro Kurihara
发明人： Takao Akaogi , Tien-Min Chen , Kazuhiro Kurihara
IPC分类号： G11C1604
CPC分类号： G11C16/24
摘要： A dual bank flash memory device including a reference path equalization circuits is disclosed. In the device, each bank includes a read path with an electrical characteristic. The device further includes a reference circuit which comprises a reference cell and reference paths which also have an electrical characteristic. The reference equalization circuits are coupled with the reference circuit which equalizes the read path electrical characteristics with the reference path electrical characteristics.
摘要翻译：公开了一种包括参考路径均衡电路的双银行闪存装置。在设备中，每个存储体包括具有电特性的读取路径。该装置还包括参考电路，其包括参考单元和也具有电特性的参考路径。参考均衡电路与参考电路耦合，该参考电路将读路径电特性与参考路径电特性相等。

7. 发明授权

US06259633B1 Sense amplifier architecture for sliding banks for a simultaneous operation flash memory device 有权
标题翻译：用于滑动组的感应放大器架构，用于同时操作的闪存设备
公开(公告)号：US06259633B1
公开(公告)日：2001-07-10
申请号：US09422198
申请日：1999-10-19
申请人： Tien-Min Chen , Kazuhiro Kurihara , Takao Akaogi
发明人： Tien-Min Chen , Kazuhiro Kurihara , Takao Akaogi
IPC分类号： G11C700
CPC分类号： G11C7/062 , G11C7/067 , G11C16/26
摘要： A flash memory device is provided with a two stage sense amplifier. The two stage sense amplifier includes a sense pre-amplifier coupled to a sense output amplifier. The sense pre-amplifier amplifies a data signal from a memory bank. The sense output amplifier then differentially compares the output of the sense pre-amplifier with a reference signal. An embodiment with first and second memory banks is also provided that is capable of simultaneous operation.
摘要翻译：闪存器件设置有两级读出放大器。两级读出放大器包括耦合到感测输出放大器的感测预放大器。感测前置放大器放大来自存储体的数据信号。然后，感测输出放大器将感测预放大器的输出与参考信号进行差分比较。还提供了具有第一和第二存储体的实施例，其能够同时操作。

8. 发明授权

US06201753B1 Latching CAM data in a flash memory device 有权
标题翻译：将CAM数据锁定在闪存设备中
公开(公告)号：US06201753B1
公开(公告)日：2001-03-13
申请号：US09421142
申请日：1999-10-19
申请人： Takao Akaogi , Kazuhiro Kurihara
发明人： Takao Akaogi , Kazuhiro Kurihara
IPC分类号： G11C700
CPC分类号： G11C15/00
摘要： A content addressable memory (CAM) circuit (200) is used as a data storage circuit to store information about operational mode and timing in a flash memory chip (100). To minimize current drain in a standby mode, the CAM circuit is placed in a low power state. To prevent unwanted switching of the output node (240) and eliminate excess current drain and mode switching of other circuits in the flash memory chip, the output of the CAM circuit is latched.
摘要翻译：内容可寻址存储器（CAM）电路（200）用作数据存储电路，用于将有关操作模式和定时的信息存储在闪存芯片（100）中。为了最小化待机模式下的电流消耗，CAM电路处于低功耗状态。为了防止输出节点（240）的不需要的切换，并消除闪速存储器芯片中其他电路的过剩电流消耗和模式切换，CAM电路的输出被锁存。

9. 发明授权

US06208556B1 Address transition detect timing architecture for a simultaneous operation flash memory device 有权
标题翻译：用于同时运行的闪存设备的地址转换检测定时架构
公开(公告)号：US06208556B1
公开(公告)日：2001-03-27
申请号：US09547556
申请日：2000-04-12
申请人： Takao Akaogi , Kazuhiro Kurihara , Tien-Min Chen
发明人： Takao Akaogi , Kazuhiro Kurihara , Tien-Min Chen
IPC分类号： G11C1604
CPC分类号： G11C16/32 , G11C8/12 , G11C8/18
摘要： An address transition signal generator for a dual bank flash memory device is disclosed. The generator includes signal transition detectors which monitor control signals of the device for transitions in their logical values. Upon detection of a signal transition, the transition detectors send a signal across equidistant signal paths to bank address transition detect signal generator circuits. This results in simultaneous generation of the address transition detect signal from each of the bank address transition detect signal generator circuits.
摘要翻译：公开了一种用于双银行闪存设备的地址转换信号发生器。发生器包括信号转换检测器，其监视器件的控制信号用于其逻辑值中的转换。在检测到信号转换时，转换检测器通过等距信号路径向bank地址转换检测信号发生器电路发送信号。这导致从每个存储体地址转换检测信号发生器电路同时生成地址转换检测信号。

10. 发明授权

US07227768B2 Power interconnect structure for balanced bitline capacitance in a memory array 有权
标题翻译：用于存储器阵列中平衡位线电容的功率互连结构
公开(公告)号：US07227768B2
公开(公告)日：2007-06-05
申请号：US11173930
申请日：2005-07-01
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C5/06
CPC分类号： H01L23/5286 , H01L23/5222 , H01L27/105 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a semiconductor die includes a memory core array situated over a substrate, where the memory core array includes a number of bitlines, where the bitlines can be situated in a first interconnect metal layer in the semiconductor die. The semiconductor die further includes an interconnect structure situated over the memory core array, where the interconnect structure is situated in a second interconnect metal layer in the semiconductor die and situated over each of the bitlines. The interconnect structure can include at least one interconnect line, which can form an angle with respect to the bitlines that can be greater than 0.0 degrees and less than or equal to 90.0 degrees. The interconnect structure can form one of a number of capacitances with each of the bitlines, where each of the capacitances can be substantially equal in value to each other of the capacitances.
摘要翻译：根据一个示例性实施例，半导体管芯包括位于衬底上的存储器芯阵列，其中存储器芯阵列包括多个位线，其中位线可以位于半导体管芯中的第一互连金属层中。半导体管芯还包括位于存储器芯阵列上方的互连结构，其中互连结构位于半导体管芯中的第二互连金属层中并且位于每个位线上。互连结构可以包括至少一个互连线，其可以相对于位线形成可以大于0.0度且小于或等于90.0度的角度。互连结构可以形成与每个位线的多个电容中的一个，其中每个电容可以在电容中彼此的值基本相等。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式