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51. 发明授权

US06335557B1 Metal silicide as a barrier for MOM capacitors in CMOS technologies 有权
标题翻译：金属硅化物作为CMOS技术中MOM电容器的屏障
公开(公告)号：US06335557B1
公开(公告)日：2002-01-01
申请号：US09441561
申请日：1999-11-17
申请人： Isik C. Kizilyalli , Sailesh M. Merchant , Joseph R. Radosevich
发明人： Isik C. Kizilyalli , Sailesh M. Merchant , Joseph R. Radosevich
IPC分类号： H01L2900
CPC分类号： H01L28/75 , H01L21/28568 , H01L21/76838 , H01L27/0805
摘要： The present invention provides a semiconductor device having a metal oxide metal (MOM) capacitor formed over a semiconductor wafer. In one embodiment, the device is a MOM capacitor that includes a first metal layer formed over the semiconductor wafer, a metal silicide layer, such as a tungsten silicide, silicide nitride or a refractory metal silicide, located on the first metal layer and an oxide layer located on the metal silicide layer. The metal silicide layer, which in an advantageous embodiment may be tungsten silicide nitride, resists the corrosive effects of deglazing that may be conducted on other portions of the wafer and is substantially unaffected by the deglazing process, unlike titanium nitride (TiN). Additionally, the metal silicide can act as an etch stop for the etching process. The MOM capacitor is completed by a second metal layer that is located on the oxide layer.
摘要翻译：本发明提供一种半导体器件，其具有在半导体晶片上形成的金属氧化物金属（MOM）电容器。在一个实施例中，器件是MOM电容器，其包括形成在半导体晶片上的第一金属层，位于第一金属层上的金属硅化物层，例如硅化钨，硅化物氮化物或难熔金属硅化物，以及氧化物层位于金属硅化物层上。在有利的实施例中，金属硅化物层可以是硅化钨氮化物，抵抗可能对晶片的其它部分进行的钝化的腐蚀作用，并且与氮化钛（TiN）不同，基本上不受脱镀工艺的影响。此外，金属硅化物可以用作蚀刻工艺的蚀刻停止。 MOM电容器由位于氧化物层上的第二金属层完成。

52. 发明授权

US06331460B1 Method of fabricating a mom capacitor having a metal silicide barrier 有权
标题翻译：制造具有金属硅化物屏障的母电容器的方法
公开(公告)号：US06331460B1
公开(公告)日：2001-12-18
申请号：US09441676
申请日：1999-11-17
申请人： Isik C. Kizilyalli , Sailesh M. Merchant , Joseph R. Radosevich
发明人： Isik C. Kizilyalli , Sailesh M. Merchant , Joseph R. Radosevich
IPC分类号： H01L218242
CPC分类号： H01L23/5223 , H01L21/76843 , H01L21/76846 , H01L27/0805 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of forming a metal oxide metal (MOM) capacitor over a semiconductor wafer. The method may include forming a first metal layer over the semiconductor wafer, forming a metal silicide layer, such as a tungsten silicide, silicide nitride or a refractory metal silicide, over the first metal layer and forming an oxide layer over the metal silicide layer. The metal silicide layer, which in an advantageous embodiment may be tungsten silicide nitride, resists the corrosive effects of deglazing that may be conducted on other portions of the wafer and is substantially unaffected by the deglazing process, unlike titanium nitride (TiN). The semiconductor device is completed by forming a second metal layer over the oxide layer.
摘要翻译：本发明提供一种在半导体晶片上形成金属氧化物金属（MOM）电容器的方法。该方法可以包括在半导体晶片之上形成第一金属层，在第一金属层上形成金属硅化物层，例如硅化钨，硅化物或难熔金属硅化物，并在金属硅化物层上形成氧化物层。在有利的实施例中，金属硅化物层可以是硅化钨氮化物，抵抗可能对晶片的其它部分进行的钝化的腐蚀作用，并且与氮化钛（TiN）不同，基本上不受脱镀工艺的影响。通过在氧化物层上形成第二金属层来完成半导体器件。

53. 发明授权

US06168991A DRAM capacitor including Cu plug and Ta barrier and method of forming 有权
标题翻译：包括Cu插头和Ta阻挡层的DRAM电容器及其形成方法
公开(公告)号：US06168991A
公开(公告)日：2001-01-02
申请号：US09340062
申请日：1999-06-25
申请人： Seungmoo Choi , Sailesh M. Merchant , Pradip K. Roy
发明人： Seungmoo Choi , Sailesh M. Merchant , Pradip K. Roy
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/28568 , H01L21/76895 , H01L27/10852 , H01L27/10888 , H01L28/55 , H01L28/75
摘要： A capacitor for a DRAM cell comprises a first electrode layer, a second electrode layer, and a dielectric film. The capacitor is disposed in a first opening defined in a second dielectric layer and overlaying a first plug through a first dielectric layer. The first plug is electrically connected to a transistor. The first electrode layer is electrically connected to the first plug. The second electrode layer can act as a barrier between a second plug exposed by a second opening and the second opening. The first and second electrode layer can be formed from Ta and TaN, and the dielectric film can be formed from tantalum oxide. A plug layer electrically connected to the second electrode layer can also be included. The plug layer can be formed from copper. A method of forming the DRAM capacitor is also disclosed.
摘要翻译：用于DRAM单元的电容器包括第一电极层，第二电极层和电介质膜。电容器设置在限定在第二电介质层中的第一开口中，并且通过第一介电层覆盖第一插塞。第一插头电连接到晶体管。第一电极层电连接到第一插头。第二电极层可以用作由第二开口暴露的第二插头和第二开口之间的屏障。第一和第二电极层可以由Ta和TaN形成，并且电介质膜可以由氧化钽形成。电连接到第二电极层的插塞层也可以包括在内。插塞层可以由铜形成。还公开了形成DRAM电容器的方法。

54. 发明授权

US5994221A Method of fabricating aluminum-indium (or thallium) vias for ULSI metallization and interconnects 失效
标题翻译：制造用于ULSI金属化和互连的铝铟（或铊）通孔的方法
公开(公告)号：US5994221A
公开(公告)日：1999-11-30
申请号：US16475
申请日：1998-01-30
申请人： Isik C. Kizilyalli , Sailesh M. Merchant
发明人： Isik C. Kizilyalli , Sailesh M. Merchant
IPC分类号： B23K35/26 , H01L21/768 , H01L23/532 , H01L23/48 , H01L23/54
CPC分类号： H01L21/76882 , H01L23/53223 , H01L2924/0002
摘要： The present invention provides a method of forming an alloy interconnect in an integrated circuit having a dielectric layer with an opening formed therein. In an advantageous embodiment, the method comprises the steps of forming a metal alloy within the opening. The metal alloy comprises at least a first and a second metal with the first metal selected from a Group 13 metal and having a melting point substantially lower than a melting point of the second metal and the dielectric. This particular method further comprises the steps of subjecting the first and second metals to a temperature sufficient to melt the first metal and reflow the metal alloy.
摘要翻译：本发明提供了一种在其中形成有开口的电介质层的集成电路中形成合金互连的方法。在有利的实施例中，该方法包括在开口内形成金属合金的步骤。所述金属合金包括至少第一和第二金属，所述第一金属选自第13族金属，并且具有基本上低于第二金属和电介质的熔点的熔点。该特定方法还包括以下步骤：使第一和第二金属处于足以熔化第一金属并回流金属合金的温度。

55. 发明授权

US5599739A Barrier layer treatments for tungsten plug 失效
标题翻译：钨丝塞的阻隔层处理
公开(公告)号：US5599739A
公开(公告)日：1997-02-04
申请号：US366867
申请日：1994-12-30
申请人： Sailesh M. Merchant , Arun K. Nanda , Pradip K. Roy
发明人： Sailesh M. Merchant , Arun K. Nanda , Pradip K. Roy
IPC分类号： C23C16/06 , C23C26/00 , H01L21/203 , H01L21/28 , H01L21/285 , H01L21/768 , H05K3/40 , H01L21/443
CPC分类号： H01L21/76876 , H01L21/76843 , H01L21/76856 , H01L21/76864 , H01L21/76877
摘要： Tungsten plugs are formed by passivating a substrate having a contact hole with SiH.sub.4, forming a nucleation layer on the passivated substrate by reducing WF.sub.6 with SiH.sub.4 at relatively low pressures and depositing tungsten to substantially fill the contact hole by reducing WF.sub.6 with H.sub.2 at relatively high pressures. Alternatively, rapid thermal annealing is used to cure pinhole defects in a titanium nitride layer on a substrate to avoid the formation of unwanted tungsten volcanoes.
摘要翻译：通过钝化具有与SiH 4的接触孔的基板来形成钨插塞，通过在相对低的压力下用SiH 4还原WF 6并在相对较低的压力下通过用H 2还原WF 6沉积钨来基本上填充接触孔，在钝化的衬底上形成成核层。或者，使用快速热退火来固化衬底上的氮化钛层中的针孔缺陷，以避免形成不需要的钨火山。

56. 发明授权

US5561083A Method of making multilayered Al-alloy structure for metal conductors 失效
标题翻译：制造金属导体多层Al合金结构的方法
公开(公告)号：US5561083A
公开(公告)日：1996-10-01
申请号：US365652
申请日：1994-12-29
申请人： Cheryl A. Bollinger , Edward A. Dein , Sailesh M. Merchant , Arun K. Nanda , Pradip K. Roy , Cletus W. Wilkins, Jr.
发明人： Cheryl A. Bollinger , Edward A. Dein , Sailesh M. Merchant , Arun K. Nanda , Pradip K. Roy , Cletus W. Wilkins, Jr.
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/822 , H01L23/482 , H01L23/532 , H01L27/04 , H01L21/283
CPC分类号： H01L23/53223 , H01L23/4827 , H01L2224/04026 , H01L2924/01021 , H01L2924/10253
摘要： A Si IC includes an Al-based layer which is deposited as a composite of sublayers of different composition Al-based materials. In one embodiment a first sublayer comprises an Al-Si-based alloy disposed so as to prevent substantial Si migration into the first sublayer, and a second sublayer, above the first, comprises an Al-based alloy with substantially no Si to alleviate precipitation-induced problems. The selection of the thickness of the second sublayer to be a major portion and the inclusion of barrier layers are also described.
摘要翻译： Si IC包括Al基层，其被沉积为不同组成的Al基材料的亚层的复合物。在一个实施例中，第一子层包括Al-Si基合金，其被设置为防止实质的Si迁移到第一子层中，并且第一子层在第一子层之上包括基本上不含Si的Al基合金以减轻沉淀 - 引起的问题。还描述了选择第二子层的厚度作为主要部分并包含阻挡层。

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