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51. 发明授权

US06737907B2 Programmable DC voltage generator system 失效
标题翻译：可编程直流电压发生器系统
公开(公告)号：US06737907B2
公开(公告)日：2004-05-18
申请号：US09898328
申请日：2001-07-03
申请人： Louis L. Hsu , Li-Kong Wang , John Atkinson Fifield , Wayne F. Ellis
发明人： Louis L. Hsu , Li-Kong Wang , John Atkinson Fifield , Wayne F. Ellis
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2001/0012 , H02M2001/0025
摘要： A digitally programmable DC voltage generator system having a programming circuit for controlling a control circuit of a voltage generator system. The programming circuit receives an input control signal, processes the input control signal, and generates an output control signal to the control circuit of the voltage generator system for controlling the control circuit in accordance with the input control signal. The control circuit includes a limiter circuit and an oscillator circuit. The output control signal controls at least one of the limiter circuit for disabling the oscillator circuit upon reaching a target output voltage, and the oscillator circuit for controlling the pumping speed of the oscillator circuit.
摘要翻译：一种具有用于控制电压发生器系统的控制电路的编程电路的数字可编程直流电压发生器系统。编程电路接收输入控制信号，处理输入控制信号，并将输出控制信号产生到电压发生器系统的控制电路，用于根据输入控制信号控制控制电路。控制电路包括限幅电路和振荡电路。输出控制信号控制至少一个限制电路，用于在达到目标输出电压时使振荡器电路无效，以及用于控制振荡器电路的泵送速度的振荡器电路。

52. 发明授权

US06649935B2 Self-aligned, planarized thin-film transistors, devices employing the same 失效
标题翻译：自对准的平面化薄膜晶体管，采用它们的器件
公开(公告)号：US06649935B2
公开(公告)日：2003-11-18
申请号：US09795535
申请日：2001-02-28
申请人： Louis L. Hsu , Jack Allan Mandelman , William Robert Tonti , Li-Kong Wang
发明人： Louis L. Hsu , Jack Allan Mandelman , William Robert Tonti , Li-Kong Wang
IPC分类号： H01L2976
CPC分类号： H01L29/66787 , H01L27/11 , H01L27/1108 , H01L29/42384 , H01L29/66765 , H01L29/78636
摘要： A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect transistor and a second field-effect transistor. The second field-effect transistor overlies the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor share a common gate. The second field-effect transistor includes a source and a drain which are self-aligned to the shared gate in a layer of planarized seminconductor material above the first field-effect transistor. In one embodiment, the second field-effect transistor is a thin-film transistor, and the shared gate has a U-shape wrap-around configuration at a body of the thin-film transistor.
摘要翻译：提出了一种半导体器件，其包括可用于诸如静态随机存取存储器（SRAM）单元的各种集成电路器件中的自对准的平坦化薄膜晶体管。半导体器件具有第一场效应晶体管和第二场效应晶体管。第二场效应晶体管覆盖第一场效应晶体管，第一场效应晶体管和第二场效应晶体管共用公共栅极。第二场效应晶体管包括在第一场效应晶体管之上的平坦化半导体材料层中与共享栅极自对准的源极和漏极。在一个实施例中，第二场效应晶体管是薄膜晶体管，并且共享栅极在薄膜晶体管的主体处具有U形环绕配置。

53. 发明授权

US06620657B2 Method of forming a planar polymer transistor using substrate bonding techniques 失效
标题翻译：使用基板接合技术形成平面聚合物晶体管的方法
公开(公告)号：US06620657B2
公开(公告)日：2003-09-16
申请号：US10052151
申请日：2002-01-15
申请人： Tricia L. Breen , Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Kwong Hon Wong
发明人： Tricia L. Breen , Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L2100
CPC分类号： H01L51/0001 , H01L51/0024 , H01L51/0516 , H01L51/0541 , H01L51/0545
摘要： A structure and method of forming a fully planarized polymer thin-film transistor by using a first planar carrier to process a first portion of the device including gate, source, drain and body elements. Preferably, the thin-film transistors made with all organic materials. The gate dielectric can be a high-k polymer to boost the device performance. Then, the partially-finished device structures are flipped upside-down and transferred to a second planar carrier. A layer of wax or photo-sensitive organic material is then applied, and can be used as the temporary glue. The device, including its body area, is then defined by an etching process. Contacts to the devices are formed by conductive material deposition and chemical-mechanical polish.
摘要翻译：通过使用第一平面载体来形成包括栅极，源极，漏极和主体元件的器件的第一部分来形成完全平坦化的聚合物薄膜晶体管的结构和方法。优选地，由所有有机材料制成的薄膜晶体管。栅极电介质可以是高k聚合物，以提高器件性能。然后，部分完成的装置结构被颠倒翻转并转移到第二平面载体。然后施加一层蜡或光敏有机材料，并且可以用作临时胶。然后通过蚀刻工艺限定该装置，包括其身体区域。与器件的接触通过导电材料沉积和化学机械抛光形成。

54. 发明授权

US06611033B2 Micromachined electromechanical (MEM) random access memory array and method of making same 失效
公开(公告)号：US06611033B2
公开(公告)日：2003-08-26
申请号：US09833547
申请日：2001-04-12
申请人： Louis L. Hsu , Li-Kong Wang
发明人： Louis L. Hsu , Li-Kong Wang
IPC分类号： H01L2714
CPC分类号： G11C23/00 , H01H59/0009 , H01L21/84 , H01L27/1203
摘要： A micromachined electromechanical random access memory (MEMRAM) array is disclosed which includes a plurality of MEM memory cells, where each MEM memory cell has an MEM switch and a capacitor. The MEM switch includes a contact portion configured for moving from a first position to a second position for reading out a charge stored within the capacitor or for writing the charge to the capacitor. A method is also disclosed for fabricating each MEM memory cell of the MEMRAM array.

55. 发明授权

US06603690B1 Low-power static column redundancy scheme for semiconductor memories 有权
标题翻译：半导体存储器的低功耗静态列冗余方案
公开(公告)号：US06603690B1
公开(公告)日：2003-08-05
申请号：US10091663
申请日：2002-03-06
申请人： Howard Hao Chen , Louis Lu-Chen Hsu , Li-Kong Wang
发明人： Howard Hao Chen , Louis Lu-Chen Hsu , Li-Kong Wang
IPC分类号： G11C700
CPC分类号： G11C29/802
摘要： A static column redundancy scheme for a semiconductor memory such as an eDRAM. By utilizing the existing scan registers for SRAM array testing, the column redundancy information of each bank or each microcell of the memory chip can be scanned, stored and programmed during the power-on period. Two programming methods are disclosed to find the column redundancy information on the fly. In the first method, the column redundancy information is first stored in the SRAM, and is then written into the program registers of the corresponding bank or microcell location. In the second method, the column redundancy information is loaded directly into the program registers of a bank or microcell location according to the bank address information without loading the SRAM. Since the new static column redundancy scheme does not need to compare the incoming addresses, it eliminates the use of control and decoding circuits, which significantly reduces the power consumption for memory macros.
摘要翻译：用于诸如eDRAM的半导体存储器的静态列冗余方案。通过利用现有的扫描寄存器进行SRAM阵列测试，可以在上电期间扫描，存储和编程存储器芯片的每个存储体或每个微单元的列冗余信息。公开了两种编程方法来即时查找列冗余信息。在第一种方法中，列冗余信息首先存储在SRAM中，然后被写入对应的存储体或微小区位置的程序寄存器中。在第二种方法中，列冗余信息根据存储体地址信息被直接加载到存储体或微小区位置的程序寄存器中而不加载SRAM。由于新的静态列冗余方案不需要比较输入地址，因此无需使用控制和解码电路，这显着降低了存储宏的功耗。

56. 发明授权

US06573565B2 Method and structure for providing improved thermal conduction for silicon semiconductor devices 有权
公开(公告)号：US06573565B2
公开(公告)日：2003-06-03
申请号：US09362399
申请日：1999-07-28
申请人： Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Tsomg-Dih Yuan
发明人： Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Tsomg-Dih Yuan
IPC分类号： H01L2362
CPC分类号： H01L21/76264 , H01L21/76283 , H01L23/3677 , H01L23/3732 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure. Yet another embodiment comprises diamond sidewalls formed along the device walls in thermal contact with the device junctions to provide heat dissipation through the device junctions to underlying cooling structures. It is also proposed that the foregoing structures, and combinations of the foregoing structures, could be used in conjunction with other known cooling schemes.

57. 发明授权

US06504173B2 Dual gate FET and process 失效
标题翻译：双栅FET和工艺
公开(公告)号：US06504173B2
公开(公告)日：2003-01-07
申请号：US09757153
申请日：2001-01-09
申请人： Louis Lu-Chen Hsu , Li-Kong Wang
发明人： Louis Lu-Chen Hsu , Li-Kong Wang
IPC分类号： H01L3300
CPC分类号： H01L29/66772 , H01L29/78648
摘要： The present invention is directed to a method of fabricating a dual gate structure for use in FET devices wherein the dual gate structure comprises a bottom gate that is substantially a mirror image of the top gate. The method utilizes a shallow trench isolation process for the purpose of planarization and gate alignment. Also disclosed is a dual gate structure which is fabricated utilizing the method of the present invention.
摘要翻译：本发明涉及一种制造用于FET器件的双栅极结构的方法，其中双栅结构包括基本上是顶栅的镜像的底栅。该方法利用浅沟槽隔离工艺，用于平坦化和栅极对准。还公开了利用本发明的方法制造的双栅结构。

58. 发明授权

US06437623B1 Data retention registers 有权
标题翻译：数据保留寄存器
公开(公告)号：US06437623B1
公开(公告)日：2002-08-20
申请号：US09782435
申请日：2001-02-13
申请人： Louis L. Hsu , Wei Hwang , Stephen V. Kosonocky , Li-Kong Wang
发明人： Louis L. Hsu , Wei Hwang , Stephen V. Kosonocky , Li-Kong Wang
IPC分类号： H03K3289
CPC分类号： H03K3/0375 , G01R31/319 , H03K3/35625
摘要： A data retention system has master-slave latches for holding data in an active mode; a data retention latch for preserving data read from the master latch in a sleep mode, which is connected to the master latch in parallel with the slave latch; a first multiplexer for receiving data externally provided and feedback data from the data retention latch, and selectively outputting either the data externally provided or the feedback data to the master latch in response to a first control signal; and a second multiplexer for transferring output data of the master latch to the slave latch and the data retention latch in response to a second control signal, wherein power for the data retention latch remains turned on in the sleep mode, while power for the data retention system except for the data retention latch is turned off. The data retention latch may include gate transistors controlled by the second control signal and a data holding unit having transistors for holding data transferred through the gate transistors, wherein the gate transistors and the transistors in the data holding unit have a high-threshold voltage.
摘要翻译：数据保留系统具有用于保持活动模式下的数据的主从锁存器; 数据保持锁存器，用于在休眠模式下保存从主锁存器读取的数据，其与从锁存器并行连接到主锁存器; 第一多路复用器，用于接收外部提供的数据并从数据保持锁存器反馈数据，并且响应于第一控制信号选择性地输出外部提供的数据或反馈数据到主锁存器; 以及第二多路复用器，用于响应于第二控制信号将主锁存器的输出数据传送到从锁存器和数据保持锁存器，其中数据保持锁存器的电源在睡眠模式下保持导通，而数据保持功率系统除了数据保持锁存器被关闭。数据保持锁存器可以包括由第二控制信号控制的栅极晶体管和具有用于保持通过栅极晶体管传送的数据的晶体管的数据保持单元，其中数据保持单元中的栅极晶体管和晶体管具有高阈值电压。

59. 发明授权

US06434076B1 Refresh control circuit for low-power SRAM applications 有权
标题翻译：刷新控制电路，用于低功耗SRAM应用
公开(公告)号：US06434076B1
公开(公告)日：2002-08-13
申请号：US09766799
申请日：2001-01-22
申请人： John E. Andersen , Louis L. Hsu , Stephen Kosonocky , Li-Kong Wang
发明人： John E. Andersen , Louis L. Hsu , Stephen Kosonocky , Li-Kong Wang
IPC分类号： G11C800
CPC分类号： G11C7/1072 , G11C11/406
摘要： A power management circuit for an SRAM system including one or more isolated memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to local supplies during an active mode of operation. The power management circuit comprises: a switch mechanism for disconnecting the external power supply to each of local power supply during a low power mode of operation; and, a refresh timing circuit implementing memory array refresh operation by selectively connecting the external power supply to a respective local power supply during the low power mode. During the low power mode, the refresh circuit intentionally enables the local power supply to float and allow it to drift to a lower predetermined voltage level prior to the memory array refresh operation.
摘要翻译：一种用于SRAM系统的电源管理电路，包括一个或多个隔离存储器阵列，并且在主动操作模式期间实现包括与每个存储器阵列相关联的本地电源的电源和连接到本地电源的外部电源。电源管理电路包括：开关机构，用于在低功率操作模式期间断开外部电源到每个本地电源; 以及通过在低功率模式期间选择性地将外部电源连接到各个本地电源来实现存储器阵列刷新操作的刷新定时电路。在低功率模式期间，刷新电路有意地使本地电源浮动并允许其在存储器阵列刷新操作之前漂移到较低的预定电压电平。

60. 发明授权

US06356134B1 Universal clock generator circuit and adjustment method for providing a plurality of clock frequencies 失效
标题翻译：通用时钟发生器电路和用于提供多个时钟频率的调整方法
公开(公告)号：US06356134B1
公开(公告)日：2002-03-12
申请号：US09531734
申请日：2000-03-21
申请人： Lawrence A. Clevenger , Louis L. C. Hsu , Li-Kong Wang , Kevin P. Guay
发明人： Lawrence A. Clevenger , Louis L. C. Hsu , Li-Kong Wang , Kevin P. Guay
IPC分类号： G06F104
CPC分类号： H03K3/0315 , G06F1/08 , H03K3/354
摘要： A universal clock generator circuit, in accordance with the present invention, includes an oscillator unit including circuitry for providing a first clock frequency. A plurality of load blocks are included. The load blocks are selectively connectable to the oscillator such that a range of clock rates are derived from the first clock frequency by selectively connecting a number of the load blocks to the oscillator unit to provide one of a plurality of clock frequencies from a same output.
摘要翻译：根据本发明的通用时钟发生器电路包括包括用于提供第一时钟频率的电路的振荡器单元。包括多个加载块。负载块可选择性地连接到振荡器，使得通过选择性地将多个负载块连接到振荡器单元从相同的输出提供多个时钟频率中的一个，从第一时钟频率导出一定范围的时钟速率。

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