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51. 发明授权

US07029956B2 Memory system capable of operating at high temperatures and method for fabricating the same 失效
公开(公告)号：US07029956B2
公开(公告)日：2006-04-18
申请号：US10666972
申请日：2003-09-19
申请人： Louis L. Hsu , Li-Kong Wang
发明人： Louis L. Hsu , Li-Kong Wang
IPC分类号： H01L21/332
CPC分类号： H01L27/1027 , H01L21/8213 , H01L27/0605 , Y10S438/931
摘要： A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.

52. 发明授权

US06911375B2 Method of fabricating silicon devices on sapphire with wafer bonding at low temperature 失效
标题翻译：在低温下用蓝宝石制造硅器件的方法
公开(公告)号：US06911375B2
公开(公告)日：2005-06-28
申请号：US10452715
申请日：2003-06-02
申请人： Kathryn W. Guarini , Louis L. Hsu , Leathen Shi , Dinkar V. Singh , Li-Kong Wang
发明人： Kathryn W. Guarini , Louis L. Hsu , Leathen Shi , Dinkar V. Singh , Li-Kong Wang
IPC分类号： H01L21/30 , H01L21/68 , H01L21/762
CPC分类号： H01L21/76256 , H01L21/6835 , H01L21/76254 , H01L2221/68368 , H01L2924/19041
摘要： Described is a method for making silicon on sapphire structures, and devices therefrom. The inventive method of forming integrated circuits on a sapphire substrate comprises the steps of providing a device layer on an oxide layer of a temporary substrate; bonding the device layer to a handling substrate; removing the temporary substrate to provide a structure containing the device layer between the oxide layer and the handling substrate; bonding a sapphire substrate to the oxide layer; removing the handling substrate from the structure; and annealing the final structure to provide a substrate comprising the oxide layer between the device layer and the sapphire substrate. The sapphire substrate may comprise bulk sapphire or may be a conventional substrate material with an uppermost sapphire layer.
摘要翻译：描述了在蓝宝石结构上制造硅的方法及其装置。在蓝宝石衬底上形成集成电路的本发明的方法包括以下步骤：在临时衬底的氧化物层上提供器件层; 将所述器件层接合到处理衬底; 去除所述临时衬底以提供在所述氧化物层和所述处理衬底之间包含所述器件层的结构; 将蓝宝石衬底结合到氧化物层; 从结构中去除处理基板; 并退火最终结构以提供包括在器件层和蓝宝石衬底之间的氧化物层的衬底。蓝宝石衬底可以包括散装蓝宝石，或者可以是具有最上层蓝宝石层的常规衬底材料。

53. 发明授权

US06894916B2 Memory array employing single three-terminal non-volatile storage elements 失效
标题翻译：采用单个三端非易失性存储元件的存储阵列
公开(公告)号：US06894916B2
公开(公告)日：2005-05-17
申请号：US10256715
申请日：2002-09-27
申请人： William Robert Reohr , Li-Kong Wang
发明人： William Robert Reohr , Li-Kong Wang
IPC分类号： G11C11/22 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792 , G11C5/06
CPC分类号： G11C11/22
摘要： An improved non-volatile memory array comprises a plurality of memory cells, at least one of the memory cells comprising a three-terminal non-volatile storage element for storing a logical state of the at least one memory cell. The memory array further comprises a plurality of write lines operatively coupled to the memory cells for selectively writing the logical state of one or more memory cells in the memory array, and a plurality of bit lines and word lines operatively coupled to the memory cells for selectively reading and writing the logical state of one or more memory cells in the memory array. The memory array is advantageously configured so as to eliminate the need for a pass gate being operatively coupled to a corresponding non-volatile storage element in the at least one memory cell.
摘要翻译：改进的非易失性存储器阵列包括多个存储器单元，至少一个存储器单元包括用于存储至少一个存储器单元的逻辑状态的三端非易失性存储元件。存储器阵列还包括可操作地耦合到存储器单元的多个写入线，用于选择性地将存储器阵列中的一个或多个存储器单元的逻辑状态写入，并且可操作地耦合到存储器单元的多个位线和字线用于选择性地读取和写入存储器阵列中的一个或多个存储器单元的逻辑状态。有利地，存储器阵列被配置为消除对可操作地耦合到至少一个存储器单元中的对应的非易失性存储元件的通过栅极的需要。

54. 发明授权

US06823293B2 Hierarchical power supply noise monitoring device and system for very large scale integrated circuits 有权
标题翻译：用于大型集成电路的分层电源噪声监测装置和系统
公开(公告)号：US06823293B2
公开(公告)日：2004-11-23
申请号：US10334312
申请日：2002-12-31
申请人： Howard H. Chen , Louis Lu-Chen Hsu , Brian L. Ji , Li-Kong Wang
发明人： Howard H. Chen , Louis Lu-Chen Hsu , Brian L. Ji , Li-Kong Wang
IPC分类号： G06F1500
CPC分类号： G01R31/3004 , G01R31/31721
摘要： A hierarchical power supply noise monitoring device and system for very large scale integrated circuits. The noise-monitoring device is fabricated on-chip to measure the noise on the chip. The noise-monitoring system includes a plurality of on-chip noise-monitoring devices distributed strategically across the chip. A noise-analysis algorithm analyzes the noise characteristics from the noise data collected from the noise-monitoring devices, and a hierarchical noise-monitoring system maps the noise of each core to the system on chip.
摘要翻译：一种用于大规模集成电路的分层电源噪声监测装置和系统。噪声监测装置是片上制造的，以测量芯片上的噪声。噪声监测系统包括跨芯片战略性分布的多个片上噪声监测装置。噪声分析算法从噪声监测装置收集的噪声数据中分析噪声特性，分层噪声监测系统将每个核心的噪声映射到片上系统。

55. 发明授权

US06781185B2 Semiconductor high dielectric constant decoupling capacitor structures and process for fabrication 有权
标题翻译：半导体高介电常数去耦电容器结构及其制造工艺
公开(公告)号：US06781185B2
公开(公告)日：2004-08-24
申请号：US10091193
申请日：2002-03-05
申请人： Howard Hao Chen , Louis L. Hsu , Li-Kong Wang
发明人： Howard Hao Chen , Louis L. Hsu , Li-Kong Wang
IPC分类号： H01L27108
CPC分类号： H01L28/91 , H01L23/5222 , H01L27/0805 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： Apparatus and method for providing high dielectric constant decoupling capacitors for semiconductor structures. The high dielectric constant decoupling capacitor can be fabricated by depositing high dielectric constant material between adjacent conductors on the same level, between conductors in successive levels, or both, to thereby provide very large capacitance value without any area or reliability penalty.
摘要翻译：用于为半导体结构提供高介电常数去耦电容器的装置和方法。高介电常数去耦电容器可以通过在相同电平上的相邻导体之间，连续电平的导体之间沉积高介电常数材料或两者来制造，从而提供非常大的电容值而没有任何面积或可靠性损失。

56. 发明授权

US06697909B1 Method and apparatus for performing data access and refresh operations in different sub-arrays of a DRAM cache memory 有权
标题翻译：用于在DRAM高速缓冲存储器的不同子阵列中执行数据访问和刷新操作的方法和装置
公开(公告)号：US06697909B1
公开(公告)日：2004-02-24
申请号：US09660431
申请日：2000-09-12
申请人： Li-Kong Wang , Louis L. Hsu
发明人： Li-Kong Wang , Louis L. Hsu
IPC分类号： G06F1300
CPC分类号： G11C11/40603 , G06F12/0802 , G11C11/406 , G11C11/40607
摘要： A method and apparatus for refreshing data in a dynamic random access memory (DRAM) cache memory in a computer system are provided to perform a data refresh operation without refresh penalty (e.g., delay in a processor). A data refresh operation is performed with respect to a DRAM cache memory by detecting a request address from a processor, stopping a normal refresh operation when the request address is detected, comparing the request address with TAG addresses stored in a TAG memory, generating refresh addresses to refresh data stored in the cache memory, each of which is generated based on an age of data corresponding to the refresh address, and performing a read/write operation on a wordline accessed by the request addresses and refreshing data on wordlines accessed by the refresh addresses, wherein the read/write operation and the refreshing of data are performed simultaneously.
摘要翻译：提供了一种用于刷新计算机系统中的动态随机存取存储器（DRAM）高速缓冲存储器中的数据的方法和装置，用于执行数据刷新操作而不刷新（例如处理器中的延迟）。通过检测来自处理器的请求地址，当检测到请求地址时停止正常刷新操作，将请求地址与存储在TAG存储器中的TAG地址进行比较，生成刷新地址刷新存储在高速缓冲存储器中的数据，其中每个基于与刷新地址相对应的数据的年龄生成，并且对由请求地址访问的字线执行读/写操作，并且通过刷新访问的字线刷新数据地址，其中同时执行读/写操作和数据刷新。

57. 发明授权

US06627924B2 Memory system capable of operating at high temperatures and method for fabricating the same 有权
公开(公告)号：US06627924B2
公开(公告)日：2003-09-30
申请号：US09845695
申请日：2001-04-30
申请人： Louis L. Hsu , Li-Kong Wang
发明人： Louis L. Hsu , Li-Kong Wang
IPC分类号： H01L2974
CPC分类号： H01L27/1027 , H01L21/8213 , H01L27/0605 , Y10S438/931
摘要： A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.

58. 发明授权

US06512683B2 System and method for increasing the speed of memories 有权
标题翻译：提高记忆速度的系统和方法
公开(公告)号：US06512683B2
公开(公告)日：2003-01-28
申请号：US09827071
申请日：2001-04-05
申请人： Louis L. Hsu , Li-Kong Wang , Toshiaki K. Kirihata
发明人： Louis L. Hsu , Li-Kong Wang , Toshiaki K. Kirihata
IPC分类号： G11C1500
CPC分类号： G06F12/0895 , G06F12/0846 , G11C7/1042
摘要： The speed of memories is increased by trading memory density (or area) for speed (or cycle time). An n by n memory array is used to reduce the memory cycle time by 1/n. For example, if an existing memory cycle time is 6 ns, in order to achieve a 3ns (or n=2) cycle time, a 2 by 2 memory array is used. Or, in order to achieve a 1ns cycle time (or n=6), then a 6 by 6 memory array is used.
摘要翻译：通过为速度（或循环时间）交易记忆密度（或面积）来提高记忆速度。 n n存储器阵列用于将存储器周期时间减少1 / n。例如，如果现有存储器周期时间为6ns，为了实现3ns（或n = 2）周期时间，则使用2乘2存储器阵列。或者，为了实现1ns周期时间（或n = 6），则使用6乘6存储器阵列。

59. 发明授权

US06426903B1 Redundancy arrangement using a focused ion beam 有权
标题翻译：使用聚焦离子束进行冗余布置
公开(公告)号：US06426903B1
公开(公告)日：2002-07-30
申请号：US09923721
申请日：2001-08-07
申请人： Lawrence A. Clevenger , Louis Lu-Chen Hsu , Li-Kong Wang , Keith Kwong-Hon Wong
发明人： Lawrence A. Clevenger , Louis Lu-Chen Hsu , Li-Kong Wang , Keith Kwong-Hon Wong
IPC分类号： G11C700
CPC分类号： G11C29/80 , Y10S977/888 , Y10S977/943
摘要： A static redundancy arrangement for a circuit using a focused ion beam anti-fuse methodology which reduces the circuit layout area and the switching activity compared to a prior art dynamic redundancy scheme, resulting in less power, a simpler design and higher speed. Focused ion beam anti-fuse methodology is used to program redundancy for circuits, particularly wide I/O embedded DRAM macros. An anti-fuse array circuit is comprised of a plurality of anti-fuse programming elements, each of which comprises a latch circuit controlled by a set input signal, and an anti-fuse device which is programmed by a focused ion beam.
摘要翻译：使用聚焦离子束反熔丝方法的电路的静态冗余布置，与现有技术的动态冗余方案相比，其减小了电路布局面积和开关活动，导致较少的功率，更简单的设计和更高的速度。聚焦离子束反熔丝方法用于编程电路冗余，特别是宽I / O嵌入式DRAM宏。反熔丝阵列电路由多个反熔丝编程元件组成，每个反熔丝编程元件包括由设定的输入信号控制的锁存电路和由聚焦离子束编程的反熔丝器件。

60. 发明授权

US06389505B1 Restore tracking system for DRAM 失效
标题翻译：恢复跟踪系统的DRAM
公开(公告)号：US06389505B1
公开(公告)日：2002-05-14
申请号：US09196086
申请日：1998-11-19
申请人： Philip George Emma , William Robert Reohr , Li-Kong Wang
发明人： Philip George Emma , William Robert Reohr , Li-Kong Wang
IPC分类号： G06F1200
CPC分类号： G06F12/0893 , G06F12/0802
摘要： A system and method for reducing the number of refresh actions needed to maintain data in a DRAM, by restoring only those cells which haven't been read from or written to within an allotted data retention time. One embodiment describes a restore tracking system as applied to a DRAM cache. The restore tracking system can alternatively be applied to any memory architecture having duplication of information. For example, the number of refresh actions needed to maintain data entries in a DRAM can be reduced by recording and updating a refresh status of one or more of the data entries in the DRAM; and invalidating those data entries having an expired status. Thus, more memory bandwidth can be made available to a computer system.
摘要翻译：一种用于通过仅恢复在分配的数据保留时间内未被读取或写入的那些单元来减少维持DRAM中的数据所需的刷新动作数量的系统和方法。一个实施例描述了应用于DRAM高速缓存的还原跟踪系统。还原跟踪系统可以替代地应用于具有信息重复的任何存储器架构。例如，可以通过记录和更新DRAM中的一个或多个数据条目的刷新状态来减少维护DRAM中的数据条目所需的刷新动作的数量; 并使那些具有过期状态的数据条目无效。因此，可以使更多的存储器带宽可用于计算机系统。

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