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51. 发明申请

US20140027841A1 HIGH VOLTAGE FIELD BALANCE METAL OXIDE FIELD EFFECT TRANSISTOR (FBM) 有权
公开(公告)号：US20140027841A1
公开(公告)日：2014-01-30
申请号：US13561523
申请日：2012-07-30
申请人： Anup Bhalla , Hamza Yilmaz , Madhur Bobde , Lingpeng Guan , Jun Hu , Jongoh Kim , Yongping Ding
发明人： Anup Bhalla , Hamza Yilmaz , Madhur Bobde , Lingpeng Guan , Jun Hu , Jongoh Kim , Yongping Ding
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/0634 , H01L21/26586 , H01L29/0615 , H01L29/0623 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/401 , H01L29/404 , H01L29/407 , H01L29/66712 , H01L29/7802 , H01L29/7811 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

52. 发明授权

US08637959B2 Vertical parasitic PNP device in a BiCMOS process and manufacturing method of the same 有权
标题翻译： BiCMOS工艺中的垂直寄生PNP器件及其制造方法
公开(公告)号：US08637959B2
公开(公告)日：2014-01-28
申请号：US13220485
申请日：2011-08-29
申请人： Wensheng Qian , Donghua Liu , Jun Hu
发明人： Wensheng Qian , Donghua Liu , Jun Hu
IPC分类号： H01L21/02
CPC分类号： H01L29/7371 , H01L21/76224 , H01L21/8249 , H01L29/0817 , H01L29/161 , H01L29/41708 , H01L29/66242
摘要： The invention discloses a vertical parasitic PNP transistor in a BiCMOS process and manufacturing method of the same, wherein an active region is isolated by STIs. The transistor includes a collector region, a base region, an emitter region, pseudo buried layers, and N-type polysilicon. The pseudo buried layers, formed at the bottom of the STIs located on both sides of the collector region, extend laterally into the active region and contact with the collector region, whose electrodes are picked up through making deep-hole contacts in the STIs. The N-type polysilicon is formed on the base region and contacts with it, whose electrodes are picked up through making metal contacts on the N-type polysilicon. The transistors can be used as output devices in high-speed and high-gain circuits, efficiently reducing the transistors area, diminishing the collector resistance, and improving the transistors performance. The method can reduce the cost without additional technological conditions.
摘要翻译：本发明公开了一种BiCMOS工艺中的垂直寄生PNP晶体及其制造方法，其中有源区由STI分离。晶体管包括集电极区域，基极区域，发射极区域，伪掩埋层和N型多晶硅。形成在位于集电区域两侧的STI的底部的伪掩埋层横向延伸到有源区并与集电区接触，该集电极区通过在STI中形成深孔接触来拾取电极。 N型多晶硅形成在基极区上并与其接触，其电极通过在N型多晶硅上形成金属接触来拾取。晶体管可以用作高速和高增益电路中的输出器件，有效降低晶体管面积，减小集电极电阻，并提高晶体管的性能。该方法可以降低成本而不需要额外的技术条件。

53. 发明授权

US08598678B2 Parasitic vertical PNP bipolar transistor and its fabrication method in BiCMOS process 有权
标题翻译：寄生垂直PNP双极晶体管及其在BiCMOS工艺中的制造方法
公开(公告)号：US08598678B2
公开(公告)日：2013-12-03
申请号：US12963242
申请日：2010-12-08
申请人： Wensheng Qian , Jun Hu , Donghua Liu
发明人： Wensheng Qian , Jun Hu , Donghua Liu
IPC分类号： H01L29/732 , H01L21/8228
CPC分类号： H01L29/732 , H01L21/8249 , H01L27/0623 , H01L29/66272
摘要： A parasitic vertical PNP bipolar transistor in BiCMOS process comprises a collector, a base and an emitter. The collector is formed by active region with p-type ion implanting layer (P type well in NMOS). It connects a P-type conductive region, which formed in the bottom region of shallow trench isolation (STI). The collector terminal connection is through the P-type buried layer and the adjacent active region. The base is formed by N type ion implanting layer above the collector which shares a N-type lightly doped drain (NLDD) implanting of NMOS. Its connection is through the N-type poly on the base region. The emitter is formed by the P-type epitaxy layer on the base region with heavy p-type doped, and connected by the extrinsic base region of NPN bipolar transistor device. This invention also includes the fabrication method of this parasitic vertical PNP bipolar transistor in BiCMOS process. And this PNP bipolar transistor can be used as the I/O (input/output) device in high speed, high current and power gain BiCMOS circuits. It also provides a device option with low cost.
摘要翻译： BiCMOS工艺中的寄生垂直PNP双极晶体管包括集电极，基极和发射极。集电极由具有p型离子注入层（P型阱在NMOS中）的有源区形成。它连接形成在浅沟槽隔离（STI）的底部区域中的P型导电区域。集电极端子连接通过P型掩埋层和相邻的有源区。基极由收集器上方的N型离子注入层形成，其共享NMOS的N型轻掺杂漏极（NLDD）注入。其连接是通过基底区域上的N型聚合物。发射极由P型掺杂的P型外延层构成，并由NPN双极晶体管器件的非本征基极区连接。本发明还包括在BiCMOS工艺中该寄生垂直PNP双极晶体管的制造方法。该PNP双极晶体管可用作高速，大电流和功率增益BiCMOS电路中的I / O（输入/输出）器件。它还提供低成本的设备选项。

54. 发明授权

US08316921B2 Plate type heat pipe and heat sink using the same 失效
标题翻译：板式热管和散热器使用相同
公开(公告)号：US08316921B2
公开(公告)日：2012-11-27
申请号：US12553997
申请日：2009-09-04
申请人： Chuen-Shu Hou , Jiang-Jun Hu , Min Lu , De-Yu Wang
发明人： Chuen-Shu Hou , Jiang-Jun Hu , Min Lu , De-Yu Wang
IPC分类号： F28D15/04
CPC分类号： F28D15/0233 , F28D15/046 , F28F3/02 , F28F3/027 , F28F2225/04 , H01L23/427 , H01L2924/0002 , H05K7/20309 , H05K7/20336 , H01L2924/00
摘要： A heat sink includes a fin assembly including a plurality of fins and a plate type heat pipe attached to the fin assembly. The plate type heat pipe includes a sealed shell in which a working fluid is filled, a wick layer formed on an inner face of the shell and a supporting member disposed in the shell. The supporting member includes a plurality of supporting portions and a plurality of bodies connecting the supporting portions. Each supporting portion includes a plurality of convex portions contacting a top of the wick layer and a plurality of concave portions contacting a bottom of the wick layer. The convex portions and the concave portions of each supporting portion are alternately arranged. Each convex portion and an adjacent concave portion cooperatively enclose a first through hole for the working fluid flowing therethrough.
摘要翻译：散热器包括包括多个翅片的翅片组件和附接到翅片组件的板式热管。板式热管包括其中填充有工作流体的密封壳体，形成在壳体的内表面上的芯层和设置在壳体中的支撑构件。支撑构件包括多个支撑部分和连接支撑部分的多个主体。每个支撑部分包括与芯层顶部接触的多个凸部和与芯层的底部接触的多个凹部。各支撑部的凸部和凹部交替配置。每个凸部和相邻的凹部协作地封闭用于流过其中的工作流体的第一通孔。

55. 发明申请

US20120199875A1 CASCODE SCHEME FOR IMPROVED DEVICE SWITCHING BEHAVIOR 有权
标题翻译：用于改进设备切换行为的CASCODE方案
公开(公告)号：US20120199875A1
公开(公告)日：2012-08-09
申请号：US13020758
申请日：2011-02-03
申请人： Anup Bhalla , Sik Lui , Jun Hu , Fei Wang
发明人： Anup Bhalla , Sik Lui , Jun Hu , Fei Wang
IPC分类号： H01L27/085
CPC分类号： H03K17/6871 , H01L27/0629 , H01L27/085 , H01L2224/73265 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H03K17/0406 , H03K17/102 , H03K17/567 , H03K2017/6875 , H01L2924/00
摘要： A switching device includes a low voltage normally-off transistor and a control circuit built into a common die. The device includes source, gate and drain electrodes for the transistor and one or more auxiliary electrodes. The drain electrode is on one surface of a die on which the transistor is formed, while each of the remaining electrodes is located on an opposite surface. The one or more auxiliary electrodes provide electrical contact to the control circuit, which is electrically connected to one or more of the other electrodes.
摘要翻译：开关器件包括低电压常关晶体管和内置在公共管芯中的控制电路。该器件包括用于晶体管的源极，栅极和漏极以及一个或多个辅助电极。漏电极在其上形成晶体管的管芯的一个表面上，而每个剩余的电极位于相对的表面上。一个或多个辅助电极提供与控制电路的电接触，该电接触电连接到一个或多个其它电极。

56. 发明申请

US20120060726A1 Emergently Openable Safe Door 审中-公开
标题翻译：突然敞开的安全门
公开(公告)号：US20120060726A1
公开(公告)日：2012-03-15
申请号：US13321555
申请日：2010-05-21
申请人： Yongyao Yao , Jun Hu , Zhongwei Cao
发明人： Yongyao Yao , Jun Hu , Zhongwei Cao
IPC分类号： E05G1/04
CPC分类号： E05B27/0053 , E05B27/0007 , E05B27/0042 , E05B35/12 , E05B47/06 , E05B63/0069 , E05B65/0075 , E05C3/042 , E05G1/04
摘要： An emergently openable safe door having a mechanic lock and an electronic lock. The mechanic lock has a shell and a cylindrical plug in the shell. The plug has a primary keyway for a primary key and an emergent keyway for an emergent key. The mechanic lock and an electric lock are able to respectively be opened with a primary key and enter cod normally and be opened with the primary key and a emergent key emergently when the electronic lock thereof malfunctions or an enter code thereof is forgotten.
摘要翻译：具有机械锁和电子锁的紧急开启的安全门。机械锁具有外壳和外壳中的圆柱塞。插头具有用于主键的主键槽和紧急键的紧急键槽。机械锁和电锁能够分别用主键打开并正常进入，并且当其电子锁故障或其输入代码被忘记时，主键和紧急钥匙突然打开。

57. 发明申请

US20120060571A1 Dual Key Bi-Step Lock 有权
标题翻译：双重双向锁
公开(公告)号：US20120060571A1
公开(公告)日：2012-03-15
申请号：US13321549
申请日：2010-05-20
申请人： Yongyao Yu , Jun Hu , Zhongwei Cao
发明人： Yongyao Yu , Jun Hu , Zhongwei Cao
IPC分类号： E05B35/10
CPC分类号： E05B27/0053 , E05B27/0007 , E05B27/0042 , E05B35/12 , E05B63/0069 , E05C3/042 , Y10T70/5788 , Y10T70/7446 , Y10T70/7458 , Y10T70/7463 , Y10T70/7565 , Y10T70/7605
摘要： A dual key bi-step lock having a shell and a cylindrical plug in the shell. The plug has a primary keyway and a secondary keyway and at least one set of primary pin stack and at least one set of secondary pin stack between the shell and the plug, respectively coupling with the primary and the secondary keys. a longitudinal stage is formed on a cylindrical surface of the plug. An involute side face extending from the stage to the cylindrical surface of the plug. The primary key is able to dive the plug to a position of first step open at which the stage is stopped by the key pin of the secondary pin stack. The secondary pin stack is unlocked by the secondary key and the plug is able to be further driven to a position of second step open by the primary and the secondary keys from the first step open.
摘要翻译：双键双向锁具有外壳和外壳中的圆柱塞。插头具有主键槽和辅助键槽以及分别与主键和副键耦合的壳和插头之间的至少一组主引脚叠层和至少一组次级引脚叠层。在插头的圆柱形表面上形成纵向台。从阶段延伸到插头的圆柱形表面的渐开线侧面。主键能够将插头潜入第一级打开的位置，在该位置，辅助引脚堆叠的键销停止该级。辅助销堆叠由辅助钥匙解锁，并且插头能够被进一步驱动到第一阶段打开的主键和辅助键的第二阶段打开的位置。

58. 发明申请

US20110232874A1 HEAT DISSIPATION APPARATUS WITH HEAT PIPE 审中-公开
标题翻译：热管散热装置
公开(公告)号：US20110232874A1
公开(公告)日：2011-09-29
申请号：US12770784
申请日：2010-04-30
申请人： CHAO XU , DE-YU WANG , JIANG-JUN HU
发明人： CHAO XU , DE-YU WANG , JIANG-JUN HU
IPC分类号： F28D15/00
CPC分类号： H01L23/427 , F28D15/0266 , H01L2924/0002 , H01L2924/00
摘要： A heat dissipation apparatus includes an evaporator receiving heat from a heat source, a condenser releasing the heat of the heat source, and a pipeline inter connecting the evaporator and the condenser. The condenser defines a flat rectangular chamber therein. A working fluid is contained in the evaporator. The working fluid vaporizes upon receiving the heat of the heat source. The pipeline conducts the vaporized working fluid from the evaporator to the condenser. The vaporized working fluid condenses upon releasing the heat in the chamber.
摘要翻译：散热装置包括从热源接收热量的蒸发器，释放热源的热量的冷凝器以及连接蒸发器和冷凝器的管道。冷凝器在其中限定了一个平坦的矩形室。工作流体包含在蒸发器中。工作流体在接收到热源的热量时蒸发。管道将蒸发的工作流体从蒸发器传导到冷凝器。蒸发的工作流体在释放室中的热量时冷凝。

59. 发明申请

US20110140239A1 High Voltage Bipolar Transistor with Pseudo Buried Layers 有权
标题翻译：具有伪埋层的高电压双极晶体管
公开(公告)号：US20110140239A1
公开(公告)日：2011-06-16
申请号：US12966078
申请日：2010-12-13
申请人： Tzuyin CHIU , TungYuan CHU , Wensheng QIAN , YungChieh FAN , Jun HU , Donghua LIU , Yukun LV
发明人： Tzuyin CHIU , TungYuan CHU , Wensheng QIAN , YungChieh FAN , Jun HU , Donghua LIU , Yukun LV
IPC分类号： H01L29/70
CPC分类号： H01L21/76232 , H01L21/8249 , H01L27/0623 , H01L29/0657 , H01L29/0821 , H01L29/41708 , H01L29/66242 , H01L29/66287 , H01L29/7322 , H01L29/7378
摘要： A high voltage bipolar transistor with shallow trench isolation (STI) comprises the areas of a collector formed by implanting first electric type impurities into active area and connected with pseudo buried layers at two sides; Pseudo buried layers which are formed by implanting high dose first type impurity through the bottoms of STI at two sides if active area, and do not touch directly; deep contact through field oxide to contact pseudo buried layers and pick up the collectors; a base deposited on the collector by epitaxial growth and in-situ doped by second electric type impurity, in which the intrinsic base touches local collector and extrinsic base is used for base pick-up; a emitter which is a polysilicon layer deposited on the intrinsic base and doped with first electric type impurities. This invention makes the depletion region of collector/base junction from 1D (vertical) distribution to 2D (vertical and lateral) distribution. The bipolar transistor's breakdown voltages are increased by only enlarge active critical dimension (CD). This is low-cost process.
摘要翻译：具有浅沟槽隔离（STI）的高电压双极晶体管包括通过将第一电型杂质注入有源区并且在两侧与伪掩埋层连接而形成的集电极的区域; 伪埋层是通过在两侧的STI两侧植入高剂量第一类杂质而形成的，如果有活动区域，并且不直接接触; 通过场氧化物深接触接触伪埋层并拾取集电器; 通过外延生长沉积在集电体上并通过第二电型杂质原位掺杂的基极，其中本征基极接触局部集电极和外部基极用于基极拾取; 作为沉积在本征基底上并掺杂有第一电型杂质的多晶硅层的发射极。本发明使集电极/基极结的耗尽区从1D（垂直）分布到2D（垂直和横向）分布。双极晶体管的击穿电压仅通过增加主动临界尺寸（CD）来增加。这是低成本的过程。

60. 发明授权

US07876264B2 Method of source number estimation and its application in method of direction of arrival estimation 有权
标题翻译：源数估计方法及其在到达方向估计方法中的应用
公开(公告)号：US07876264B2
公开(公告)日：2011-01-25
申请号：US12051569
申请日：2008-03-19
申请人： Weiqing Zhu , Jun Hu , Xiaodong Liu , Zhiyu Liu , Feng Pan
发明人： Weiqing Zhu , Jun Hu , Xiaodong Liu , Zhiyu Liu , Feng Pan
IPC分类号： G01S5/02 , G01S3/14
CPC分类号： G01S3/74
摘要： The present invention provides a method of source number estimation based on eigenspace in DOA estimation, including: (1) obtaining signals received by uniform linear array; (2) calculating a covariance matrix according to the received signals; (3) calculating a complex-valued covariance matrix or a covariance matrix after real-valued computations; (4) conducting eigendecomposition to the covariance matrix to obtain its eigenvector matrix; (5) calculating a source number decision based on the eigenvector; (6) calculating a ratio; and (7) source number estimation. The present invention can accurately estimate source number and save huge amounts of computation during signal processing in DOA estimation, and lower the cost of hardware.
摘要翻译：本发明提供了一种基于DOA估计中的本征空间的源数估计方法，包括：（1）获得均匀线性阵列接收的信号; （2）根据接收信号计算协方差矩阵; （3）在实值计算之后计算复值协方差矩阵或协方差矩阵; （4）对协方差矩阵进行特征分解，得到其特征向量矩阵; （5）基于特征向量计算源数量决定; （6）计算比率; 和（7）源数估计。本发明可以在DOA估计中的信号处理期间准确地估计源数量并节省大量的计算量，降低硬件成本。

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