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1. 发明申请

US20170148910A1 TERMINATION DESIGN FOR HIGH VOLTAGE DEVICE 审中-公开
公开(公告)号：US20170148910A1
公开(公告)日：2017-05-25
申请号：US15425235
申请日：2017-02-06
申请人： Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
发明人： Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/78 , H01L29/40 , H01L29/10 , H01L29/66 , H01L29/06
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/66712 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

2. 发明申请

US20160005809A1 CONFIGURATION AND METHOD TO GENERATE SADDLE JUNCTION ELECTRIC FIELD IN EDGE TERMINATION 审中-公开
公开(公告)号：US20160005809A1
公开(公告)日：2016-01-07
申请号：US14298537
申请日：2014-06-06
申请人： Madhur Bobde , Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
发明人： Madhur Bobde , Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/06 , H01L21/761
CPC分类号： H01L29/0634 , H01L21/26513 , H01L21/761 , H01L29/0615 , H01L29/0619 , H01L29/6609 , H01L29/861
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.

3. 发明授权

US08680613B2 Termination design for high voltage device 有权
标题翻译：高压设备终端设计
公开(公告)号：US08680613B2
公开(公告)日：2014-03-25
申请号：US13561300
申请日：2012-07-30
申请人： Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
发明人： Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/66712 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：本公开描述了一种用于高电压半导体晶体管器件的端接结构。终端结构由至少两个终端区域和身体层与设备的边缘之间的电断开组成。第一区被配置成在设备内扩展电场。第二区域被配置成平滑地将电场返回到设备的顶表面。电气断开防止设备短路设备的边缘。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

4. 发明申请

US20130221430A1 NANO-TUBE MOSFET TECHNOLOGY AND DEVICES 有权
标题翻译：纳米管MOSFET技术和器件
公开(公告)号：US20130221430A1
公开(公告)日：2013-08-29
申请号：US13594837
申请日：2012-08-26
申请人： Hamza Yilmaz , Daniel Ng , Lingpeng Guan , Anup Bhalla , Wilson Ma , Moses Ho , John Chen
发明人： Hamza Yilmaz , Daniel Ng , Lingpeng Guan , Anup Bhalla , Wilson Ma , Moses Ho , John Chen
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7827 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0649 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/404 , H01L29/66136 , H01L29/66348 , H01L29/66666 , H01L29/66734 , H01L29/7322 , H01L29/7395 , H01L29/7397 , H01L29/7802 , H01L29/7811 , H01L29/7813 , H01L29/8083 , H01L29/861 , H01L29/872
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件，半导体衬底具有多个沟槽。每个沟槽填充有多个交替导电类型的外延层，其构成纳米管，其功能是作为沿着侧壁方向延伸的层堆叠的导电通道，“间隙填充”层填充基本上位于其上的纳米管之间的合并间隙每个沟渠的中心。 “间隙填料”层可以非常轻掺杂硅或生长和沉积的介电层。在一个示例性实施例中，多个沟槽被柱柱分隔开，柱柱各自具有沟槽宽度的大约一半到三分之一的宽度。

5. 发明申请

US20130001695A1 UNI-DIRECTIONAL TRANSIENT VOLTAGE SUPPRESSOR (TVS) 有权
标题翻译：单向瞬态电压抑制器（TVS）
公开(公告)号：US20130001695A1
公开(公告)日：2013-01-03
申请号：US13171037
申请日：2011-06-28
申请人： Lingpeng Guan , Madhur Bobde , Anup Bhalla
发明人： Lingpeng Guan , Madhur Bobde , Anup Bhalla
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/0262 , H01L21/8222 , H01L27/0255 , H01L27/0259 , H01L27/0814 , H01L27/082
摘要： An epitaxial layer is supported on top of a substrate. First and second body regions are formed within the epitaxial layer separated by a predetermined lateral distance. Trigger and source regions are formed within the epitaxial layer. A first source region is transversely adjacent the first body region between first and second trigger regions laterally adjacent the first source region and transversely adjacent the first body region. A second source region is located transversely adjacent the second body region between third and fourth trigger regions laterally adjacent the second source region and transversely adjacent the second body region. A third source region is laterally adjacent the fourth trigger region. The fourth trigger region is between the second and third source regions. An implant region within the fourth trigger region is laterally adjacent the third source region.
摘要翻译：外延层支撑在基板的顶部。第一和第二体区域形成在外延层中以预定的横向距离分开。在外延层内形成触发源区和源极区。第一源区域横向地邻近第一和第二触发区域之间的与第一源区域相邻并且横向邻近第一体区域的第一体区域相邻。第二源区域横向地邻近第二和第四触发区域之间的第二体区横向邻近第二源区域并且横向邻近第二体区域定位。第三源区域与第四触发区域横向相邻。第四触发区域在第二和第三源区之间。第四触发区域内的植入区域与第三源区域横向相邻。

6. 发明申请

US20110147830A1 METHOD OF FORMING A SELF-ALIGNED CHARGE BALANCED POWER DMOS 有权
标题翻译：形成自对准电荷平衡功率DMOS的方法
公开(公告)号：US20110147830A1
公开(公告)日：2011-06-23
申请号：US12643837
申请日：2009-12-21
申请人： John Chen , Yeeheng Lee , Lingpeng Guan , Moses Ho , Wilson Ma , Anup Bhalla , Hamza Yilmaz
发明人： John Chen , Yeeheng Lee , Lingpeng Guan , Moses Ho , Wilson Ma , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/26586 , H01L29/0615 , H01L29/0634 , H01L29/0878 , H01L29/165 , H01L29/456 , H01L29/66719 , H01L29/78 , H01L29/7811
摘要： Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.
摘要翻译：公开了自对准电荷平衡半导体器件及其形成方法。在第一导电类型的半导体衬底上形成一个或多个平面栅极。在与平面栅极自对准的半导体中蚀刻一个或多个深沟槽。沟槽填充有第二导电类型的半导体材料，使得深沟槽与半导体衬底的相邻区域电荷平衡。该工艺可以形成具有小于12微米的电池间距的自对准电荷平衡装置。

7. 发明申请

US20170125514A9 MANUFACTURING METHODS FOR ACCURATELY ALIGNED AND SELF-BALANCED SUPERJUNCTION DEVICES 审中-公开
公开(公告)号：US20170125514A9
公开(公告)日：2017-05-04
申请号：US14298922
申请日：2014-06-08
申请人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
发明人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
IPC分类号： H01L29/06 , H01L21/266 , H01L21/324 , H01L29/10
CPC分类号： H01L29/0634 , H01L21/2253 , H01L21/266 , H01L21/324 , H01L29/1095 , H01L29/66712 , H01L29/7802
摘要： This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a . drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types. Then the manufacturing processes proceed by carrying out a device manufacturing process on a top side of the epitaxial layer on top of the dopant regions of the alternating conductivity types with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.

8. 发明申请

US20160181391A1 DIODE STRUCTURES WITH CONTROLLED INJECTION EFFICIENCY FOR FAST SWITCHING 审中-公开
标题翻译：具有控制注射效率的二极管结构，用于快速切换
公开(公告)号：US20160181391A1
公开(公告)日：2016-06-23
申请号：US14573187
申请日：2014-12-17
申请人： Madhur Bobde , Harsh Naik , Lingpeng Guan , Anup Bhalla , Sik Lui
发明人： Madhur Bobde , Harsh Naik , Lingpeng Guan , Anup Bhalla , Sik Lui
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06 , H01L29/868
CPC分类号： H01L29/868 , H01L29/0615 , H01L29/0619 , H01L29/0696 , H01L29/36 , H01L29/402 , H01L29/407 , H01L29/6609 , H01L29/66136 , H01L29/66143 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7803 , H01L29/7839 , H01L29/861 , H01L29/8613 , H01L29/8725
摘要： This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体器件。半导体器件包括在第一主表面上的第一导电类型的第一半导体层。半导体器件还包括与第一主表面相对的第二主表面上的第二导电类型的第二半导体层。该半导体器件还包括设置在第二半导体层正下方的第一导电类型的注入效率控制缓冲层，以控制第二半导体层的注入效率。

9. 发明申请

US20150115333A1 LATERAL SUPER JUNCTIONS WITH HIGH SUBSTRATE BREAKDOWN AND BUILD IN AVALANCHE CLAMP DIODE 审中-公开
标题翻译：具有高基板断裂和建立在AVALANCHE钳位二极管的横向超级结
公开(公告)号：US20150115333A1
公开(公告)日：2015-04-30
申请号：US14062868
申请日：2013-10-24
申请人： Madhur Bobde , Anup Bhalla , Hamza Yilmaz , Wilson Ma , Lingpeng Guan , Yeeheng Lee , John Chen
发明人： Madhur Bobde , Anup Bhalla , Hamza Yilmaz , Wilson Ma , Lingpeng Guan , Yeeheng Lee , John Chen
IPC分类号： H01L29/10 , H01L29/808 , H01L27/06
CPC分类号： H01L29/1058 , H01L27/0727 , H01L29/0634 , H01L29/808 , H01L2224/0603 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2924/181 , H01L2924/00014 , H01L2924/00012
摘要： This invention discloses configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.
摘要翻译：本发明公开了制造横向功率器件的结构和方法，该器件包括在漏极和栅极之间形成的具有雪崩钳位二极管的超结结构。横向超结结构降低了导通电阻，而结构增强（包括雪崩钳位二极管和N缓冲区）增加了衬底和漏极之间的击穿电压，并改善了非钳位感应开关（UIS）性能。

10. 发明授权

US08975720B2 Corner layout for superjunction device 有权
标题翻译：超级装置的角落布局
公开(公告)号：US08975720B2
公开(公告)日：2015-03-10
申请号：US13923065
申请日：2013-06-20
申请人： Lingpeng Guan , Madhur Bobde
发明人： Lingpeng Guan , Anup Bhalla , Tinggang Zhu , Madhur Bobde
IPC分类号： H01L29/72 , H01L29/78 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/47
CPC分类号： H01L29/7823 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/47 , H01L29/7811
摘要： A superjunction device and methods for layout design and fabrication of a superjunction device are disclosed. A layout of active cell column structures can be configured so that a charge due to first conductivity type dopants balances out charge due to second conductivity type dopants in a doped layer in an active cell region. A layout of end portions of the active cell column structures proximate termination column structures can be configured so that a charge due to the first conductivity type dopants in the end portions and a charge due to the first conductivity type dopants in the termination column structures balances out charge due to the second conductivity type dopants in a portion of the doped layer between the termination column structures and the end portions.
摘要翻译：公开了一种用于布置设计和超级结装置制造的超结装置和方法。可以配置活性单元列结构的布局，使得由于第一导电型掺杂剂引起的电荷由于活性单元区域中的掺杂层中的第二导电类型掺杂物而平衡电荷。靠近端子列结构的活性单元列结构的端部的布局可以被配置为使得由于端部中的第一导电类型掺杂物引起的电荷和由端接塔结构中的第一导电类型掺杂剂引起的电荷平衡在终端柱结构和端部之间的掺杂层的一部分中的第二导电类型掺杂剂引起的电荷。

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