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51. 发明申请

US20110230027A1 Methods of Forming Semiconductor Devices Having Faceted Semiconductor Patterns 有权
标题翻译：形成具有半导体图案的半导体器件的方法
公开(公告)号：US20110230027A1
公开(公告)日：2011-09-22
申请号：US13052460
申请日：2011-03-21
申请人： Myung-Sun Kim , Dong-Suk Shin , Dong-Hyuk Kim , Yong-Joo Lee , Hoi-Sung Chung
发明人： Myung-Sun Kim , Dong-Suk Shin , Dong-Hyuk Kim , Yong-Joo Lee , Hoi-Sung Chung
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/26586 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： Provided are methods of forming semiconductor devices. A method may include preparing a semiconductor substrate including a first region and a second region adjacent the first region. The method may also include forming sacrificial pattern covering the second region and exposing the first region. The method may further include forming a capping layer including a faceted sidewall on the first region using selective epitaxial growth (SEG). The faceted sidewall may be separate from the sacrificial pattern. The sacrificial pattern may be removed. Impurity ions may be implanted into the semiconductor substrate.
摘要翻译：提供了形成半导体器件的方法。一种方法可以包括制备包括第一区域和邻近第一区域的第二区域的半导体衬底。该方法还可以包括形成覆盖第二区域并暴露第一区域的牺牲图案。该方法还可以包括使用选择性外延生长（SEG）在第一区域上形成包括有侧壁的覆盖层。分面侧壁可以与牺牲图案分离。可以去除牺牲图案。杂质离子可以注入到半导体衬底中。

52. 发明授权

US08013420B2 Electrical fuse device 失效
标题翻译：电熔丝装置
公开(公告)号：US08013420B2
公开(公告)日：2011-09-06
申请号：US12203256
申请日：2008-09-03
申请人： Dong-suk Shin , Andrew-tae Kim , Hong-jae Shin
发明人： Dong-suk Shin , Andrew-tae Kim , Hong-jae Shin
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L23/5258 , H01L27/112 , H01L2924/0002 , H01L2924/00
摘要： The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.
摘要翻译：本发明一般涉及半导体器件的熔丝器件，更具体地，涉及一种半导体器件的电熔丝器件。本发明的实施例提供一种能够减少由熔丝链中的不均匀电流密度引起的编程误差的熔丝装置。在一方面，提供一种电熔丝装置，其包括：阳极; 熔丝链路，其在所述熔丝连接件的第一侧上耦合到所述阳极; 连接到所述熔丝链的第二侧上的所述熔断体的阴极; 耦合到阴极的第一阴极接触; 以及耦合到所述阳极的第一阳极触点，所述第一阴极触点和所述第一阳极触点中的至少一个跨越所述熔断体的虚拟延伸表面设置。

53. 发明授权

US07839190B2 Locking state detector and DLL circuit having the same 有权
标题翻译：具有相同的锁定状态检测器和DLL电路
公开(公告)号：US07839190B2
公开(公告)日：2010-11-23
申请号：US12263300
申请日：2008-10-31
申请人： Dong-Suk Shin , Chul Woo Kim , Hyun Soo Chae
发明人： Dong-Suk Shin , Chul Woo Kim , Hyun Soo Chae
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/095
摘要： A locking state detector includes a phase comparing unit configured to compare a reference clock signal and a feedback clock signal to generate a first phase difference distinction signal to distinguish a first phase difference range, and a second phase difference distinction signal to distinguish a second phase difference range wider than the first phase difference range, and a locking state setting unit configured to generate a locking state signal in response to the first phase difference distinction signal and the second phase difference distinction signal.
摘要翻译：锁定状态检测器包括：相位比较单元，被配置为比较参考时钟信号和反馈时钟信号以产生第一相位差区分信号以区分第一相位差范围;以及第二相位差区别信号，以区分第二相位差范围宽于第一相位差范围;锁定状态设置单元，被配置为响应于第一相位差识别信号和第二相位差识别信号产生锁定状态信号。

54. 发明申请

US20100207210A1 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US20100207210A1
公开(公告)日：2010-08-19
申请号：US12656752
申请日：2010-02-16
申请人： Dong-Suk Shin
发明人： Dong-Suk Shin
IPC分类号： H01L29/786 , H01L29/78
CPC分类号： H01L29/6656 , H01L21/76232 , H01L29/665 , H01L29/66651 , H01L29/78
摘要： A semiconductor device includes an isolation layer pattern, an epitaxial layer pattern, a gate insulation layer pattern and a gate electrode. The isolation layer pattern is formed on a substrate, and defines an active region in the substrate. The isolation layer pattern extends in a second direction. The epitaxial layer pattern is formed on the active region and the isolation layer pattern, and has a width larger than that of the active region in a first direction perpendicular to the second direction. The gate insulation layer pattern is formed on the epitaxial layer pattern. The gate electrode is formed on the gate insulation layer pattern.
摘要翻译：半导体器件包括隔离层图案，外延层图案，栅极绝缘层图案和栅电极。隔离层图案形成在衬底上，并且在衬底中限定有源区。隔离层图案沿第二方向延伸。外延层图案形成在有源区和隔离层图案上，并且在垂直于第二方向的第一方向上具有大于有源区的宽度的宽度。栅极绝缘层图案形成在外延层图案上。栅电极形成在栅极绝缘层图案上。

55. 发明申请

US20100200929A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20100200929A1
公开(公告)日：2010-08-12
申请号：US12702618
申请日：2010-02-09
申请人： Dong Suk Shin , Chong-Kwang Chang
发明人： Dong Suk Shin , Chong-Kwang Chang
IPC分类号： H01L29/78
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： A semiconductor integrated circuit memory device includes a gate line that extends in a first direction, an active region adjacent to a first end of the gate line and that extends in a second direction, a silicide layer formed on a top surface of the active region, on a top surface of the gate line, on both sidewalls of the first end of the gate line, and on a transverse endwall of the first end of the gate line. A spacer may be formed on sidewalls of the gate line, excluding the first end of the gate line, and a contact shared by the active region may be formed on the first end of the gate line.
摘要翻译：半导体集成电路存储器件包括：沿第一方向延伸的栅极线，与栅极线的第一端相邻并且沿第二方向延伸的有源区，形成在有源区的顶表面上的硅化物层; 在栅极线的顶表面上，在栅极线的第一端的两个侧壁上以及在栅极线的第一端的横向端壁上。除了栅极线的第一端之外，可以在栅极线的侧壁上形成间隔物，并且可以在栅极线的第一端上形成由有源区域共享的触点。

56. 发明授权

US07761757B2 Apparatus and method of setting test mode in semiconductor integrated circuit 有权
标题翻译：设置半导体集成电路测试模式的方法和设备
公开(公告)号：US07761757B2
公开(公告)日：2010-07-20
申请号：US12013866
申请日：2008-01-14
申请人： Won-Joo Yun , Hyun-Woo Lee , Dong-Suk Shin
发明人： Won-Joo Yun , Hyun-Woo Lee , Dong-Suk Shin
IPC分类号： G01R31/28
CPC分类号： G11C29/46 , G11C29/14 , G11C2029/0407 , Y10T307/747 , Y10T307/826 , Y10T307/858 , Y10T307/977
摘要： An apparatus for setting a test mode in a semiconductor integrated circuit includes a test mode control block that generates a coding control signal according to whether or not a control fuse is cut, and a test mode coding block that sets default values of a multi-bit test code in response to the coding control signal.
摘要翻译：一种用于在半导体集成电路中设置测试模式的装置包括：测试模式控制块，其根据是否切断控制熔丝产生编码控制信号;以及测试模式编码块，其设置多位的默认值响应于编码控制信号的测试码。

57. 发明授权

US07737746B2 DLL circuit and method of controlling the same 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US07737746B2
公开(公告)日：2010-06-15
申请号：US12170282
申请日：2008-07-09
申请人： Dong-Suk Shin
发明人： Dong-Suk Shin
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/10
摘要： A delay locked loop (DLL) circuit includes an initial operation setting unit configured to generate an initial operation signal in response to a reference clock signal and an operation start signal; a shift register configured to generate a delay control code in response to the initial operation signal, a phase comparison signal, and an initial setting code; a delay line configured to delay the reference clock signal or a feedback clock signal in response to the initial operation signal and the delay control code, thereby generating a plurality of unit delay clock signals; and an initial delay monitoring unit configured to generate the initial setting code in response to the reference clock signal and the plurality of unit delay clock signals.
摘要翻译：延迟锁定环（DLL）电路包括初始操作设置单元，其被配置为响应于参考时钟信号和操作开始信号而产生初始操作信号; 移位寄存器，被配置为响应于初始操作信号，相位比较信号和初始设置码产生延迟控制代码; 延迟线，被配置为响应于初始操作信号和延迟控制代码来延迟参考时钟信号或反馈时钟信号，由此产生多个单位延迟时钟信号; 以及初始延迟监视单元，被配置为响应于所述参考时钟信号和所述多个单位延迟时钟信号而产生所述初始设置码。

58. 发明授权

US07714394B2 CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same 有权
标题翻译：具有升高的源极和漏极区域的CMOS半导体器件及其制造方法
公开(公告)号：US07714394B2
公开(公告)日：2010-05-11
申请号：US11285978
申请日：2005-11-23
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L23/58
CPC分类号： H01L29/7834 , H01L21/265 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628
摘要： A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regions, respectively. A first elevated source region and a first elevated drain region are disposed at both sides of the first gate pattern respectively, and a second elevated source region and a second elevated drain region are disposed at both sides of the second gate pattern respectively. The first elevated source/drain regions are provided on the first active region, and the second elevated source/drain regions are provided on the second active region. A first gate spacer is provided between the first gate pattern and the first elevated source/drain regions. A second gate spacer is provided to cover edges of the second elevated source/drain regions adjacent to the second gate pattern and an upper sidewall of the second gate pattern. Methods of fabricating the CMOS device is also provided.
摘要翻译：提供互补金属氧化物半导体（CMOS）器件。 CMOS器件包括设置在半导体衬底中以限定第一和第二有源区的隔离层。第一和第二栅极图案分别设置成跨越第一和第二有源区域。第一升高的源极区域和第一升高的漏极区域分别设置在第一栅极图案的两侧，并且第二升高的源极区域和第二升高的漏极区域分别设置在第二栅极图案的两侧。第一升高的源极/漏极区域设置在第一有源区上，而第二升高的源极/漏极区域设置在第二有源区域上。在第一栅极图案和第一升高的源极/漏极区域之间提供第一栅极间隔物。设置第二栅极间隔物以覆盖与第二栅极图案相邻的第二升高的源极/漏极区域和第二栅极图案的上侧壁的边缘。还提供了制造CMOS器件的方法。

59. 发明授权

US07599004B2 Digital video signal processing apparatus and method for extracting data in a vertical blanking interval 失效
标题翻译：用于在垂直消隐间隔中提取数据的数字视频信号处理装置和方法
公开(公告)号：US07599004B2
公开(公告)日：2009-10-06
申请号：US11331354
申请日：2006-01-13
申请人： Dong-suk Shin , Hyung-jun Lim , Jae-hong Park , Kyoung-mook Lim , Heo-jin Byeon , Sung-cheol Park
发明人： Dong-suk Shin , Hyung-jun Lim , Jae-hong Park , Kyoung-mook Lim , Heo-jin Byeon , Sung-cheol Park
IPC分类号： H04N7/00
CPC分类号： H04N7/0355 , H04L7/046 , H04N7/035 , H04N21/435 , H04N21/488
摘要： A digital video signal processing apparatus and method for detecting data in a vertical blanking interval (VBI) includes a re-sampler generating, from input video data, first re-sample data at a VBI data rate and second re-sample data with a data rate twice as high as the VBI data rate, a signal tracking unit tracking an existence of a clock run-in and a phase of the clock run-in from the second re-sample data and calculating an average of the clock run-in, and a slicer determining a logical value of the first re-sample data according to the average of the clock run-in and outputting the determined logical value as VBI data, wherein the re-sampler determines a compensation phase from the tracked phase of the clock run-in, re-samples the input video data according to the compensation phase with the VBI data rate and generates the first re-sample data.
摘要翻译：用于在垂直消隐间隔（VBI）中检测数据的数字视频信号处理装置和方法包括重新采样器，其从输入视频数据生成VBI数据速率的第一重新采样数据和具有数据的第二重新采样数据速率是VBI数据速率的两倍，信号跟踪单元从第二重新采样数据跟踪时钟输入和时钟输入的存在并计算时钟输入的平均值，以及切片器，根据所述时钟输入的平均值确定所述第一再采样数据的逻辑值，并将所确定的逻辑值输出为VBI数据，其中所述重新取样器从所述时钟的跟踪相位确定补偿相位根据具有VBI数据速率的补偿阶段重新对输入视频数据进行采样，并生成第一个重新采样数据。

60. 发明授权

US07579861B2 Impedance-controlled pseudo-open drain output driver circuit and method for driving the same 失效
标题翻译：阻抗控制的开漏输出驱动电路及其驱动方法
公开(公告)号：US07579861B2
公开(公告)日：2009-08-25
申请号：US11906365
申请日：2007-10-01
申请人： Dong-Suk Shin , Inhwa Jung , Chulwoo Kim , Hyung-Dong Lee , Young-Jung Choi
发明人： Dong-Suk Shin , Inhwa Jung , Chulwoo Kim , Hyung-Dong Lee , Young-Jung Choi
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00384
摘要： An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.
摘要翻译：阻抗控制的伪开漏输出驱动电路包括：处理电压和温度（PVT）检测器，被配置为具有接收参考时钟的延迟线，并根据PVT条件检测延迟线的状态变化以输出检测信号; 选择信号发生器，被配置为基于所述检测信号和输出数据产生驱动选择信号; 以及输出驱动器，被配置为驱动输出端子，所述输出驱动器包括由所述驱动选择信号控制的多个上拉/下拉驱动块，每个所述上拉/下拉驱动块包括具有一个预期的阻抗。

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