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51. 发明授权

US07808043B2 Semiconductor device and methods of fabricating the same including forming spacers and etch stop layers with stress properties 有权
标题翻译：半导体器件及其制造方法包括形成具有应力特性的间隔物和蚀刻停止层
公开(公告)号：US07808043B2
公开(公告)日：2010-10-05
申请号：US11525024
申请日：2006-09-22
申请人： Ki-Chul Kim , Dong-Suk Shin , Yong-Kuk Jeong
发明人： Ki-Chul Kim , Dong-Suk Shin , Yong-Kuk Jeong
IPC分类号： H01L29/74 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L21/8238 , H01L21/4763
CPC分类号： H01L21/823807 , H01L21/823864
摘要： A semiconductor device having an etch stop layer and a method of fabricating the same are provided. The semiconductor device may include a substrate and a first gate electrode formed on the substrate. An auxiliary spacer may be formed on the sidewall of the first gate electrode. An etch stop layer may be formed on the substrate having the auxiliary spacer. The etch stop layer and the auxiliary spacer may be formed of a material having a same stress property.
摘要翻译：提供了具有蚀刻停止层的半导体器件及其制造方法。半导体器件可以包括形成在衬底上的衬底和第一栅电极。可以在第一栅电极的侧壁上形成辅助间隔物。可以在具有辅助间隔物的衬底上形成蚀刻停止层。蚀刻停止层和辅助间隔物可以由具有相同应力特性的材料形成。

52. 发明申请

US20100164573A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100164573A1
公开(公告)日：2010-07-01
申请号：US12494355
申请日：2009-06-30
申请人： Ja-Beom Koo , Dong-Suk Shin
发明人： Ja-Beom Koo , Dong-Suk Shin
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03K5/133 , H03K2005/00026 , H03L7/087
摘要： A semiconductor device, includes a clock delay unit configured to include a plurality of delay units connected in series, where the delay amount of each delay unit varies depending on a level of a control voltage, for delaying a source clock to generate a feedback clock and mixing clocks outputted from the respective delay units to generate a frequency multiplication clock, a harmonic lock determination unit configured to determine whether a harmonic lock has occurred based on a frequency difference between the source clock and the frequency multiplication clock, and a control voltage generator configured to adjust a level of the control voltage based on a phase difference between the source clock and the feedback clock and a determination result of the harmonic lock determination unit.
摘要翻译：一种半导体器件，包括：时钟延迟单元，被配置为包括串联连接的多个延迟单元，其中每个延迟单元的延迟量根据控制电压的电平而变化，用于延迟源时钟以产生反馈时钟; 从相应的延迟单元输出的混合时钟以产生倍频时钟;谐波锁定确定单元，被配置为基于源时钟和倍频时钟之间的频率差来确定是否发生了谐波锁定;以及控制电压发生器，基于源时钟和反馈时钟之间的相位差以及谐波锁定确定单元的确定结果来调节控制电压的电平。

53. 发明申请

US20100134155A1 POWER-DOWN MODE CONTROL APPARATUS AND DLL CIRCUIT HAVING THE SAME 有权
标题翻译：掉电模式控制装置和具有该模式的DLL电路
公开(公告)号：US20100134155A1
公开(公告)日：2010-06-03
申请号：US12698606
申请日：2010-02-02
申请人： Hyun Woo Lee , Won Joo Yun , Dong Suk Shin
发明人： Hyun Woo Lee , Won Joo Yun , Dong Suk Shin
IPC分类号： H03L7/00 , H03L7/06
CPC分类号： G11C7/02 , G11C5/143 , G11C5/144 , G11C7/22 , G11C7/222
摘要： A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.
摘要翻译：断电模式控制装置包括内部掉电控制块，其被配置为接收锁定完成信号并产生切换预定时间的内部掉电信号; 噪声检查块，被配置为基于相位检测信号来检查噪声的发生/不发生，并且响应于锁定完成信号和内部掉电信号而产生多个掉电选择信号; 以及断电进入控制块，被配置为产生多个断电输入信号，其响应于参考时钟信号指示各个电路进入掉电模式，所述多个掉电选择信号，功率下降模式信号和内部掉电信号。

54. 发明授权

US07719333B2 Power control circuit, method of controlling power control circuit, and DLL circuit including power control circuit 有权
标题翻译：功率控制电路，电源控制电路的控制方法，电源控制电路的DLL电路
公开(公告)号：US07719333B2
公开(公告)日：2010-05-18
申请号：US11964802
申请日：2007-12-27
申请人： Won Joo Yun , Hyun Woo Lee , Dong Suk Shin
发明人： Won Joo Yun , Hyun Woo Lee , Dong Suk Shin
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal.
摘要翻译：功率控制电路包括：检查单元，接收参考时钟并产生用于循环地激活DLL电路的反馈回路的检查信号;相位检测单元，其检测参考时钟和反馈时钟之间的相位差，并产生相位差检测信号，以及响应于锁定完成信号，检查信号和相位差检测信号产生电力切断信号的信号组合单元。

55. 发明申请

US20100109729A1 DUTY DETECTING CIRCUIT AND DUTY CYCLE CORRECTOR INCLUDING THE SAME 有权
标题翻译：负责检测电路和占空比校正器，包括它们
公开(公告)号：US20100109729A1
公开(公告)日：2010-05-06
申请号：US12343859
申请日：2008-12-24
申请人： Dong-Suk SHIN
发明人： Dong-Suk SHIN
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K5/159 , H03K5/26
摘要： A duty cycle corrector includes a duty adjusting unit configured to adjust a duty cycle of an input clock in response to a duty correction code and generate an output clock, a duty detecting unit configured to measure a difference between a high pulse width and a low pulse width of the output clock and output a difference value, and an accumulating unit configured to accumulate the difference value to generate the duty correction code.
摘要翻译：占空比校正器包括：占空比调整单元，被配置为响应于占空比校正码调整输入时钟的占空比并产生输出时钟;占空比检测单元，被配置为测量高脉冲宽度与低脉冲之间的差输出时钟的宽度并输出差值;以及累加单元，被配置为累积差值以生成占空比校正码。

56. 发明授权

US07701010B2 Method of fabricating transistor including buried insulating layer and transistor fabricated using the same 有权
标题翻译：制造包括埋入绝缘层的晶体管的方法和使用其制造的晶体管
公开(公告)号：US07701010B2
公开(公告)日：2010-04-20
申请号：US12206225
申请日：2008-09-08
申请人： Dong-Suk Shin
发明人： Dong-Suk Shin
IPC分类号： H01L29/786
CPC分类号： H01L29/66636 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66628 , H01L29/66772 , H01L29/7848 , H01L29/78621 , H01L29/78639
摘要： In a method of fabricating a transistor including a buried insulating layer and transistor fabricated using the same, the method includes sequentially forming a sacrificial layer and a top semiconductor layer on a single crystalline semiconductor substrate. A gate pattern is formed on the top semiconductor layer. A sacrificial spacer is formed to cover sidewalls of the gate pattern. An elevated semiconductor layer is grown on a portion of the top semiconductor layer adjacent to the sacrificial spacer. The sacrificial spacer is removed. A portion of the top semiconductor layer from which the sacrificial spacer is removed is etched until the sacrificial layer is exposed, thereby forming a recess, which separates the top semiconductor layer into a first top semiconductor layer pattern and a second top semiconductor layer pattern, which remain under the gate pattern and the elevated semiconductor layer, respectively. The sacrificial layer is selectively removed. A buried insulating layer is formed to fill a region from which the sacrificial layer is removed. A buried semiconductor layer is grown in the recess. An extending recess extends from the recess and is formed to expose the semiconductor substrate. The extending recess separates the buried insulating layer into a first buried insulating layer pattern and a second buried insulating layer pattern, which are self-aligned to the first and second top semiconductor layer patterns, respectively.
摘要翻译：在制造包括掩埋绝缘层的晶体管和使用其制造的晶体管的方法中，该方法包括在单晶半导体衬底上顺序地形成牺牲层和顶部半导体层。在顶部半导体层上形成栅极图案。形成牺牲隔离物以覆盖栅极图案的侧壁。在与牺牲间隔物相邻的顶部半导体层的一部分上生长升高的半导体层。去除牺牲隔离物。去除牺牲隔离物的顶部半导体层的一部分被蚀刻直到牺牲层被暴露，从而形成将顶部半导体层分离为第一顶部半导体层图案和第二顶部半导体层图案的凹部，其中分别保持在栅极图案和升高的半导体层之下。牺牲层被选择性地去除。形成掩埋绝缘层以填充去除牺牲层的区域。在凹槽中生长掩埋半导体层。延伸凹部从凹部延伸并形成为露出半导体衬底。延伸凹部将掩埋绝缘层分别分别与第一和第二顶部半导体层图案自对准的第一掩埋绝缘层图案和第二掩埋绝缘层图案。

57. 发明申请

US20090256214A1 Semiconductor device and associated methods 审中-公开
标题翻译：半导体器件及相关方法
公开(公告)号：US20090256214A1
公开(公告)日：2009-10-15
申请号：US12385574
申请日：2009-04-13
申请人： Min-Chul Sun , Dong-Suk Shin , Jung-Deog Lee
发明人： Min-Chul Sun , Dong-Suk Shin , Jung-Deog Lee
IPC分类号： H01L29/78
CPC分类号： H01L27/088 , H01L21/76897 , H01L29/665 , H01L29/6656
摘要： A semiconductor device and process of fabricating the same, the semiconductor device including a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a gate electrode having sidewalls, on the gate insulating layer, first spacers on the sidewalls of the gate electrode, a source/drain region in the semiconductor substrate, aligned with the sidewalls, a silicide layer on the gate electrode, a silicide layer on the source/drain region, and second spacers covering the first spacers and end parts of a surface of the silicide layer on the source drain region.
摘要翻译：一种半导体器件及其制造方法，半导体器件包括半导体衬底，半导体衬底上的栅极绝缘层，具有侧壁的栅电极，栅极绝缘层，栅电极的侧壁上的第一间隔物，源极/漏极区域，与侧壁对准，栅极上的硅化物层，源极/漏极区域上的硅化物层，以及覆盖第一间隔物和硅化物层的表面的端部的第二间隔物，源极漏极区域。

58. 发明授权

US07601983B2 Transistor and method of manufacturing the same 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US07601983B2
公开(公告)日：2009-10-13
申请号：US11207703
申请日：2005-08-19
申请人： Tetsuji Ueno , Hwa-Sung Rhee , Ho Lee , Dong-Suk Shin , Seung-Hwan Lee
发明人： Tetsuji Ueno , Hwa-Sung Rhee , Ho Lee , Dong-Suk Shin , Seung-Hwan Lee
IPC分类号： H01L29/10
CPC分类号： H01L29/66636 , H01L29/045 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7834
摘要： A transistor includes a semiconductor substrate that has a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a third surface of a {111} crystal plane connecting the first surface to the second surface. First heavily doped impurity regions are formed under the second surface. A gate structure is formed on the first surface. An epitaxial layer is formed on the second surface and the third surface. Second heavily doped impurity regions are formed at both sides of the gate structure. The second heavily doped impurity regions have side faces of the {111} crystal plane so that a short channel effect generated between the impurity regions may be prevented.
摘要翻译：晶体管包括具有{100}晶面的第一表面，{100}晶面的第二表面的半导体衬底的高度低于第一表面的第一表面，以及{111}晶体的第三表面将第一表面连接到第二表面的平面。在第二表面下形成第一重掺杂杂质区。栅极结构形成在第一表面上。在第二表面和第三表面上形成外延层。在栅极结构的两侧形成第二重掺杂杂质区。第二重掺杂杂质区域具有{111}晶面的侧面，从而可以防止在杂质区域之间产生的短沟道效应。

59. 发明申请

US20090146707A1 DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US20090146707A1
公开(公告)日：2009-06-11
申请号：US12170282
申请日：2008-07-09
申请人： Dong-Suk Shin
发明人： Dong-Suk Shin
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/10
摘要： A delay locked loop (DLL) circuit includes an initial operation setting unit configured to generate an initial operation signal in response to a reference clock signal and an operation start signal; a shift register configured to generate a delay control code in response to the initial operation signal, a phase comparison signal, and an initial setting code; a delay line configured to delay the reference clock signal or a feedback clock signal in response to the initial operation signal and the delay control code, thereby generating a plurality of unit delay clock signals; and an initial delay monitoring unit configured to generate the initial setting code in response to the reference clock signal and the plurality of unit delay clock signals.
摘要翻译：延迟锁定环（DLL）电路包括初始操作设置单元，其被配置为响应于参考时钟信号和操作开始信号而产生初始操作信号; 移位寄存器，被配置为响应于初始操作信号，相位比较信号和初始设置码产生延迟控制代码; 延迟线，被配置为响应于初始操作信号和延迟控制代码来延迟参考时钟信号或反馈时钟信号，由此产生多个单位延迟时钟信号; 以及初始延迟监视单元，被配置为响应于所述参考时钟信号和所述多个单位延迟时钟信号而产生所述初始设置码。

60. 发明申请

US20090121784A1 POWER-DOWN MODE CONTROL APPARATUS AND DLL CIRCUIT HAVING THE SAME 有权
标题翻译：掉电模式控制装置和具有该模式的DLL电路
公开(公告)号：US20090121784A1
公开(公告)日：2009-05-14
申请号：US12175212
申请日：2008-07-17
申请人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
发明人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
IPC分类号： G05F1/10
CPC分类号： G11C7/02 , G11C5/143 , G11C5/144 , G11C7/22 , G11C7/222
摘要： A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.
摘要翻译：断电模式控制装置包括内部掉电控制块，其被配置为接收锁定完成信号并产生切换预定时间的内部掉电信号; 噪声检查块，被配置为基于相位检测信号来检查噪声的发生/不发生，并且响应于锁定完成信号和内部掉电信号而产生多个掉电选择信号; 以及断电进入控制块，被配置为产生多个断电输入信号，其响应于参考时钟信号指示各个电路进入掉电模式，所述多个掉电选择信号，功率下降模式信号和内部掉电信号。

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