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1. 发明授权

US08450125B2 Methods of evaluating epitaxial growth and methods of forming an epitaxial layer 有权
标题翻译：评估外延生长的方法和形成外延层的方法
公开(公告)号：US08450125B2
公开(公告)日：2013-05-28
申请号：US13186515
申请日：2011-07-20
申请人： Dong-Suk Shin , Yong-Joo Lee , Dong-Hyuk Kim , Myung-Sun Kim , Hoi-Sung Chung
发明人： Dong-Suk Shin , Yong-Joo Lee , Dong-Hyuk Kim , Myung-Sun Kim , Hoi-Sung Chung
IPC分类号： H01L21/66
CPC分类号： H01L29/66636 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L22/12 , H01L29/78 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A method of evaluating an epitaxial growing process includes forming a mold layer on each of a plurality of substrates, forming a photoresist pattern on each mold layer, the photoresist pattern having opening portions, a total area of a bottom portion of the opening portions being different for each substrate, patterning each mold layer to expose a surface portion of the substrate to form an evaluation pattern on each substrate, evaluation patterns including opening portions corresponding to the opening portion in the photoresist pattern, determining substrate opening ratios for each substrate based on the opening portions in the evaluation pattern thereon, the substrate opening ratios being different for each substrate, performing a selective epitaxial process on each substrate to form an epitaxial layer, and evaluating characteristics of the epitaxial layer for each substrate to determine an optimal substrate opening ratio.
摘要翻译：评价外延生长方法的方法包括在多个基板的每一个上形成模具层，在每个模具层上形成光致抗蚀剂图案，所述光致抗蚀剂图案具有开口部分，所述开口部分的底部的总面积不同对于每个基板，图案化每个模具层以暴露基板的表面部分以在每个基板上形成评估图案，评估图案包括与光致抗蚀剂图案中的开口部分对应的开口部分，基于该基板确定每个基板的基板开口率在其上的评估图案中的开口部分，基板开口率对于每个基板不同，在每个基板上执行选择性外延处理以形成外延层，以及评估每个基板的外延层的特性以确定最佳的基板开口率。

2. 发明申请

US20120021537A1 METHODS OF EVALUATING EPITAXIAL GROWTH AND METHODS OF FORMING AN EPITAXIAL LAYER 有权
标题翻译：外源生长评估方法及形成外源层的方法
公开(公告)号：US20120021537A1
公开(公告)日：2012-01-26
申请号：US13186515
申请日：2011-07-20
申请人： Dong-Suk Shin , Yong-Joo Lee , Dong-Hyuk Kim , Myung-Sun Kim , Hoi-Sung Chung
发明人： Dong-Suk Shin , Yong-Joo Lee , Dong-Hyuk Kim , Myung-Sun Kim , Hoi-Sung Chung
IPC分类号： H01L21/66
CPC分类号： H01L29/66636 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L22/12 , H01L29/78 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A method of evaluating an epitaxial growing process includes forming a mold layer on each of a plurality of substrates, forming a photoresist pattern on each mold layer, the photoresist pattern having opening portions, a total area of a bottom portion of the opening portions being different for each substrate, patterning each mold layer to expose a surface portion of the substrate to form an evaluation pattern on each substrate, evaluation patterns including opening portions corresponding to the opening portion in the photoresist pattern, determining substrate opening ratios for each substrate based on the opening portions in the evaluation pattern thereon, the substrate opening ratios being different for each substrate, performing a selective epitaxial process on each substrate to form an epitaxial layer, and evaluating characteristics of the epitaxial layer for each substrate to determine an optimal substrate opening ratio.
摘要翻译：评价外延生长方法的方法包括在多个基板的每一个上形成模具层，在每个模具层上形成光致抗蚀剂图案，所述光致抗蚀剂图案具有开口部分，所述开口部分的底部的总面积不同对于每个基板，图案化每个模具层以暴露基板的表面部分以在每个基板上形成评估图案，评估图案包括与光致抗蚀剂图案中的开口部分对应的开口部分，基于该基板确定每个基板的基板开口率在其上的评估图案中的开口部分，基板开口率对于每个基板不同，在每个基板上执行选择性外延处理以形成外延层，以及评估每个基板的外延层的特性以确定最佳的基板开口率。

3. 发明申请

US20110230027A1 Methods of Forming Semiconductor Devices Having Faceted Semiconductor Patterns 有权
标题翻译：形成具有半导体图案的半导体器件的方法
公开(公告)号：US20110230027A1
公开(公告)日：2011-09-22
申请号：US13052460
申请日：2011-03-21
申请人： Myung-Sun Kim , Dong-Suk Shin , Dong-Hyuk Kim , Yong-Joo Lee , Hoi-Sung Chung
发明人： Myung-Sun Kim , Dong-Suk Shin , Dong-Hyuk Kim , Yong-Joo Lee , Hoi-Sung Chung
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/26586 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： Provided are methods of forming semiconductor devices. A method may include preparing a semiconductor substrate including a first region and a second region adjacent the first region. The method may also include forming sacrificial pattern covering the second region and exposing the first region. The method may further include forming a capping layer including a faceted sidewall on the first region using selective epitaxial growth (SEG). The faceted sidewall may be separate from the sacrificial pattern. The sacrificial pattern may be removed. Impurity ions may be implanted into the semiconductor substrate.
摘要翻译：提供了形成半导体器件的方法。一种方法可以包括制备包括第一区域和邻近第一区域的第二区域的半导体衬底。该方法还可以包括形成覆盖第二区域并暴露第一区域的牺牲图案。该方法还可以包括使用选择性外延生长（SEG）在第一区域上形成包括有侧壁的覆盖层。分面侧壁可以与牺牲图案分离。可以去除牺牲图案。杂质离子可以注入到半导体衬底中。

4. 发明授权

US08703592B2 Methods of forming semiconductor devices having faceted semiconductor patterns 有权
标题翻译：形成具有刻面半导体图案的半导体器件的方法
公开(公告)号：US08703592B2
公开(公告)日：2014-04-22
申请号：US13052460
申请日：2011-03-21
申请人： Myung-Sun Kim , Dong-Suk Shin , Dong-Hyuk Kim , Yong-Joo Lee , Hoi-Sung Chung
发明人： Myung-Sun Kim , Dong-Suk Shin , Dong-Hyuk Kim , Yong-Joo Lee , Hoi-Sung Chung
IPC分类号： H01L21/425
CPC分类号： H01L29/66636 , H01L21/26586 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： Provided are methods of forming semiconductor devices. A method may include preparing a semiconductor substrate including a first region and a second region adjacent the first region. The method may also include forming sacrificial pattern covering the second region and exposing the first region. The method may further include forming a capping layer including a faceted sidewall on the first region using selective epitaxial growth (SEG). The faceted sidewall may be separate from the sacrificial pattern. The sacrificial pattern may be removed. Impurity ions may be implanted into the semiconductor substrate.
摘要翻译：提供了形成半导体器件的方法。一种方法可以包括制备包括第一区域和邻近第一区域的第二区域的半导体衬底。该方法还可以包括形成覆盖第二区域并暴露第一区域的牺牲图案。该方法还可以包括使用选择性外延生长（SEG）在第一区域上形成包括有侧壁的覆盖层。小面侧壁可以与牺牲图案分离。可以去除牺牲图案。杂质离子可以注入到半导体衬底中。

5. 发明授权

US08207040B2 Methods of manufacturing semiconductor devices including forming (111) facets in silicon capping layers on source/drain regions 有权
标题翻译：制造半导体器件的方法包括在源/漏区上的硅封装层中形成（111）刻面
公开(公告)号：US08207040B2
公开(公告)日：2012-06-26
申请号：US13021029
申请日：2011-02-04
申请人： Hoi-Sung Chung , Dong-Suk Shin , Dong-Hyuk Kim , Jung-Shik Heo , Myung-Sun Kim
发明人： Hoi-Sung Chung , Dong-Suk Shin , Dong-Hyuk Kim , Jung-Shik Heo , Myung-Sun Kim
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/36 , H01L21/425
CPC分类号： H01L21/823807 , H01L21/30608 , H01L21/3086 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7834 , H01L29/7848 , Y10S438/938
摘要： A method of manufacturing a semiconductor device includes forming a gate electrode on a semiconductor substrate and a sidewall spacer on the gate electrode. Then, a portion of the semiconductor substrate at both sides of the sidewall spacer is partially etched to form a trench. A SiGe mixed crystal layer is formed in the trench. A silicon layer is formed on the SiGe mixed crystal layer. A portion of the silicon layer is partially etched using an etching solution having different etching rates in accordance with a crystal direction of a face of the silicon layer to form a capping layer including a silicon facet having an (111) inclined face.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上形成栅电极和在栅电极上形成侧壁间隔物。然后，部分地蚀刻在侧壁间隔物的两侧的半导体衬底的一部分以形成沟槽。在沟槽中形成SiGe混合晶体层。在SiGe混晶层上形成硅层。使用根据硅层的表面的晶体方向具有不同蚀刻速率的蚀刻溶液来部分蚀刻硅层的一部分，以形成包括具有（111）倾斜面的硅小面的覆盖层。

6. 发明申请

US20120223364A1 TRANSISTORS AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US20120223364A1
公开(公告)日：2012-09-06
申请号：US13410475
申请日：2012-03-02
申请人： Hoi-Sung CHUNG , Dong-Suk Shin , Dong-Hyuk Kim , Myung-Sun Kim
发明人： Hoi-Sung CHUNG , Dong-Suk Shin , Dong-Hyuk Kim , Myung-Sun Kim
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/20
CPC分类号： H01L21/823807 , H01L21/30608 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer.
摘要翻译：在制造晶体管的方法中，在包括硅的衬底上形成栅极结构。蚀刻与栅极结构相邻的衬底的上部，以在衬底中形成第一凹部。在第一凹部中形成包括硅 - 锗的初步的第一外延层。蚀刻初步第一外延层的上部以在初步第一外延层上形成第二凹槽。此外，蚀刻与第二凹槽相邻的初步第一外延层的一部分，从而将初步第一外延层转变为第一外延层。在位于第一外延层上的第二凹槽中形成包括硅 - 锗的第二外延层。

7. 发明授权

US08637373B2 Transistors and methods of manufacturing the same 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US08637373B2
公开(公告)日：2014-01-28
申请号：US13410475
申请日：2012-03-02
申请人： Hoi-Sung Chung , Dong-Suk Shin , Dong-Hyuk Kim , Myung-Sun Kim
发明人： Hoi-Sung Chung , Dong-Suk Shin , Dong-Hyuk Kim , Myung-Sun Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/30608 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer.
摘要翻译：在制造晶体管的方法中，在包括硅的衬底上形成栅极结构。蚀刻与栅极结构相邻的衬底的上部，以在衬底中形成第一凹部。在第一凹部中形成包括硅 - 锗的初步的第一外延层。蚀刻初步第一外延层的上部以在初步第一外延层上形成第二凹槽。此外，蚀刻与第二凹槽相邻的初步第一外延层的一部分，从而将初步第一外延层转变为第一外延层。在位于第一外延层上的第二凹槽中形成包括硅 - 锗的第二外延层。

8. 发明授权

US08648424B2 Semiconductor device including transistors having embedded source/drain regions each including upper and lower main layers comprising germanium 有权
标题翻译：半导体器件包括具有嵌入的源/漏区的晶体管，每个晶体管包括包含锗的上和下主层
公开(公告)号：US08648424B2
公开(公告)日：2014-02-11
申请号：US13600375
申请日：2012-08-31
申请人： Hoi-Sung Chung , Dong-Hyuk Kim , Myung-Sun Kim , Dong-Suk Shin
发明人： Hoi-Sung Chung , Dong-Hyuk Kim , Myung-Sun Kim , Dong-Suk Shin
IPC分类号： H01L21/70
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823418 , H01L29/165 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device includes a substrate having a channel region, a gate insulation layer on the channel region, a gate electrode on the gate insulation layer, and source and drain regions in recesses in the substrate on both sides of the channel region, respectively. The source and drain regions include a lower main layer whose bottom surface is located at level above the bottom of a recess and lower than that of the bottom surface of the gate insulation layer, and a top surface no higher than the level of the bottom surface of the gate insulation layer, and an upper main layer contacting the lower main layer and whose top surface extends to a level higher than that of the bottom surface of the gate insulation layer, and in which the lower layer has a Ge content higher than that of the upper layer.
摘要翻译：半导体器件包括具有沟道区的衬底，沟道区上的栅极绝缘层，栅极绝缘层上的栅电极，以及沟道区两侧的衬底中的凹槽中的源极和漏极区。源极和漏极区域包括下表面位于凹槽底部的平面以上并且低于栅极绝缘层的底表面的下主层，以及不高于底表面的高度的顶表面的栅极绝缘层的上部主层和与下部主层接触的上部主层，其上表面延伸到比栅极绝缘层的底面高的水平，并且其中下层的Ge含量高于栅极绝缘层的底面。的上层。

9. 发明申请

US20120061578A1 X-Ray Detector Panel 有权
标题翻译： X光检测器面板
公开(公告)号：US20120061578A1
公开(公告)日：2012-03-15
申请号：US13175097
申请日：2011-07-01
申请人： James Lim , Kwan-Wook Jung , Dong-Hyuk Kim , Jea-Eun Ryu
发明人： James Lim , Kwan-Wook Jung , Dong-Hyuk Kim , Jea-Eun Ryu
IPC分类号： G01T1/24
CPC分类号： G01T1/2928 , H01L27/14663 , H01L27/14692
摘要： An X-ray detector panel comprises: a substrate; a transistor including a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate electrode, an active layer disposed on the gate insulating layer, and a source electrode and a drain electrode disposed on the active layer and separated from each other; a photodiode including a first electrode connected to the drain electrode of the transistor, a photoconductive layer disposed on the first electrode, and a second electrode disposed on the photoconductive layer; an interlayer insulating layer including a first interlayer insulating layer covering the transistor and the photodiode, the first interlayer insulating layer being formed of an insulating material having a band gap energy of about 8 eV to about 10 eV; a data line disposed on the interlayer insulating layer and contacting the source electrode of the transistor via the interlayer insulating layer; a bias line disposed on the interlayer insulating layer and contacting the second electrode of the photodiode via the interlayer insulating layer; and a passivation layer disposed on the data line, the bias line, and the interlayer insulating layer.
摘要翻译： X射线检测器面板包括：基板; 设置在所述基板上的栅电极，配置在所述栅电极上的栅极绝缘层，配置在所述栅极绝缘层上的有源层，以及设置在所述有源层上并分离的源电极和漏电极的晶体管，光电二极管，包括连接到晶体管的漏电极的第一电极，设置在第一电极上的光电导层和设置在光电导层上的第二电极; 层间绝缘层，包括覆盖所述晶体管和所述光电二极管的第一层间绝缘层，所述第一层间绝缘层由具有约8eV至约10eV的带隙能量的绝缘材料形成; 数据线，设置在所述层间绝缘层上，并经由所述层间绝缘层与所述晶体管的源电极接触; 偏置线，设置在所述层间绝缘层上，并经由所述层间绝缘层与所述光电二极管的所述第二电极接触; 以及设置在数据线，偏置线和层间绝缘层上的钝化层。

10. 发明授权

US08916830B2 X-ray detector panel 有权
标题翻译： X光检测器面板
公开(公告)号：US08916830B2
公开(公告)日：2014-12-23
申请号：US13175097
申请日：2011-07-01
申请人： James Lim , Kwan-Wook Jung , Dong-Hyuk Kim , Jea-Eun Ryu
发明人： James Lim , Kwan-Wook Jung , Dong-Hyuk Kim , Jea-Eun Ryu
IPC分类号： H01L27/146 , G01T1/20 , G01T1/24 , G01T1/29
CPC分类号： G01T1/2928 , H01L27/14663 , H01L27/14692
摘要： An X-ray detector panel comprises: a substrate; a transistor including a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate electrode, an active layer disposed on the gate insulating layer, and a source electrode and a drain electrode disposed on the active layer and separated from each other; a photodiode including a first electrode connected to the drain electrode of the transistor, a photoconductive layer disposed on the first electrode, and a second electrode disposed on the photoconductive layer; an interlayer insulating layer including a first interlayer insulating layer covering the transistor and the photodiode, the first interlayer insulating layer being formed of an insulating material having a band gap energy of about 8 eV to about 10 eV; a data line disposed on the interlayer insulating layer and contacting the source electrode of the transistor via the interlayer insulating layer; a bias line disposed on the interlayer insulating layer and contacting the second electrode of the photodiode via the interlayer insulating layer; and a passivation layer disposed on the data line, the bias line, and the interlayer insulating layer.
摘要翻译： X射线检测器面板包括：基板; 设置在所述基板上的栅电极，配置在所述栅电极上的栅极绝缘层，配置在所述栅极绝缘层上的有源层，以及设置在所述有源层上并分离的源电极和漏电极的晶体管，光电二极管，包括连接到晶体管的漏电极的第一电极，设置在第一电极上的光电导层和设置在光电导层上的第二电极; 层间绝缘层，包括覆盖所述晶体管和所述光电二极管的第一层间绝缘层，所述第一层间绝缘层由具有约8eV至约10eV的带隙能量的绝缘材料形成; 数据线，设置在所述层间绝缘层上，并经由所述层间绝缘层与所述晶体管的源电极接触; 偏置线，设置在所述层间绝缘层上，并经由所述层间绝缘层与所述光电二极管的所述第二电极接触; 以及设置在数据线，偏置线和层间绝缘层上的钝化层。

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