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41. 发明授权

US09424384B2 Method of density-controlled floorplan design for integrated circuits and integrated circuits 有权
标题翻译：集成电路和集成电路密度控制平面图设计方法
公开(公告)号：US09424384B2
公开(公告)日：2016-08-23
申请号：US14310376
申请日：2014-06-20
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chung-Chieh Yang , Yung-Chow Peng , Chung-Peng Hsieh , Wen-Shen Chou , Chih-Chiang Chang
IPC分类号： H01L21/02 , G06F17/50 , H01L23/64 , H01L23/66
CPC分类号： G06F17/5072 , H01L23/50 , H01L23/642 , H01L23/66 , H01L2223/6666 , H01L2924/0002 , H01L2924/00
摘要： A method of density-controlled floorplan design for integrated circuits having a plurality of blocks includes positioning decoupling capacitor (DCAP) cells at least partially around a pattern density sensitive block. The method also includes changing at least a portion of a pattern density insensitive block adjacent to the pattern density sensitive block according to at least one pattern density rule.
摘要翻译：具有多个块的集成电路的密度控制平面图规划设计的方法包括至少部分地围绕图案密度敏感块的定位去耦电容器（DCAP）单元。该方法还包括根据至少一种图案密度规则改变与图案密度敏感块相邻的图案密度不敏感块的至少一部分。

42. 发明授权

US09300254B2 Radio frequency devices with surface-mountable capacitors for decoupling and methods thereof 有权
标题翻译：具有用于去耦的表面贴装电容器的射频装置及其方法
公开(公告)号：US09300254B2
公开(公告)日：2016-03-29
申请号：US14316484
申请日：2014-06-26
申请人： Freescale Semiconductor, Inc.
发明人： Mahesh K. Shah , Jerry L. White , Li Li , Hussain H. Ladhani , Audel A. Sanchez , Lakshminarayan Viswanathan , Fernando A. Santos
IPC分类号： H03F3/213 , H03F1/30 , H03H1/00 , H03F3/195
CPC分类号： H03F1/0288 , H01L23/3107 , H01L23/49562 , H01L23/642 , H01L23/66 , H01L2223/665 , H01L2223/6655 , H01L2223/6666 , H01L2224/49175 , H01L2924/0002 , H03F1/0283 , H03F1/30 , H03F1/565 , H03F3/193 , H03F3/195 , H03F3/211 , H03F3/213 , H03F2200/267 , H03F2200/451 , H03F2200/555 , H03F2203/21103 , H03F2203/21106 , H03F2203/21139 , H03H1/00 , H03H7/38 , H03H2001/0021 , H05K7/005 , H01L2924/00
摘要： An embodiment of a radio-frequency (RF) device includes at least one transistor, a package, and a surface-mountable capacitor. The package contains the at least one transistor and includes at least one termination. The surface-mountable capacitor is coupled in a shunt configuration between the at least one transistor and a power supply terminal of the device to decouple the at least one transistor from a power supply.
摘要翻译：射频（RF）器件的一个实施例包括至少一个晶体管，封装和表面贴装电容器。该封装包含至少一个晶体管，并且包括至少一个端接。表面安装电容器以至少一个晶体管和该器件的电源端之间的分流配置耦合，以将至少一个晶体管与电源分离。

43. 发明申请

US20140132353A1 AMPLIFIER CIRCUIT 有权
标题翻译：放大器电路
公开(公告)号：US20140132353A1
公开(公告)日：2014-05-15
申请号：US14080711
申请日：2013-11-14
申请人： NXP B.V.
发明人： Vittorio Cuoco , Josephus Henricus Bartholomeus van der Zanden , Albert Gerardus Wilhelmus Philipus van Zuijlen
IPC分类号： H03F3/68 , H01L21/50
CPC分类号： H03F3/68 , H01L21/50 , H01L23/66 , H01L24/48 , H01L24/49 , H01L2223/6666 , H01L2224/48247 , H01L2224/49111 , H01L2224/49113 , H01L2224/49175 , H01L2924/00014 , H03F1/0288 , H01L2224/45099 , H01L2924/00
摘要： An integrated power amplifier circuit is disclosed. The circuit comprises: first and second amplifiers fabricated on one or more dies, the one or more dies being mounted on a support structure; a first set of one or more connection elements connected to the first amplifier and passing above a portion of the support structure; and a second set of one or more connection elements connected to the second amplifier and passing above a portion of the support structure. The support structure comprises at least one void, at least a portion of the at least one void being positioned directly underneath at least one of the first and second sets of one or more connection elements.
摘要翻译：公开了一种集成功率放大器电路。该电路包括：在一个或多个管芯上制造的第一和第二放大器，一个或多个管芯安装在支撑结构上; 连接到第一放大器并通过支撑结构的一部分的一个或多个连接元件的第一组; 以及连接到第二放大器并且通过支撑结构的一部分的一个或多个连接元件的第二组。所述支撑结构包括至少一个空隙，所述至少一个空隙的至少一部分直接位于所述第一和第二组一个或多个连接元件中的至少一个之下。

44. 发明申请

US20130062763A1 DE-POP ON-DEVICE DECOUPLING FOR BGA 有权
公开(公告)号：US20130062763A1
公开(公告)日：2013-03-14
申请号：US13231609
申请日：2011-09-13
申请人： Alex CHAN , Paul Brown
发明人： Alex CHAN , Paul Brown
IPC分类号： H01L23/498
CPC分类号： H01L24/14 , G06F17/5068 , H01L23/49816 , H01L23/50 , H01L23/66 , H01L2223/6666 , H01L2224/13014 , H01L2224/1413 , H01L2224/73204 , H01L2924/1203 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/1304 , H01L2924/14 , H01L2924/15321 , H01L2924/20648 , H05K1/112 , H05K2201/10636 , H05K2201/10734 , Y02P70/611
摘要： Embodiments of the invention place surface-mount devices such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, in place of de-populated BGA pads.

45. 发明授权

US08174126B2 Stacked multi-chip 有权
标题翻译：堆叠多芯片
公开(公告)号：US08174126B2
公开(公告)日：2012-05-08
申请号：US12882805
申请日：2010-09-15
申请人： Ting-Ting Hwang , Hsien-Te Chen
发明人： Ting-Ting Hwang , Hsien-Te Chen
IPC分类号： H01L23/12 , H01L23/52 , H01L23/48
CPC分类号： H01L23/5286 , H01L23/481 , H01L25/0657 , H01L2223/6616 , H01L2223/6666 , H01L2225/06513 , H01L2225/06544 , H01L2924/0002 , H01L2924/00
摘要： A stacked multi-chip comprises a base layer, a first chip, a first stacked chip and at least one second stacked chip. The base layer comprises a mounting panel and a redistributed layer. The redistributed layer is mounted on the mounting panel. The first chip comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer abuts the redistributed layer. The first stacked chip is mounted on the first chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel that is connected to the TSV channel of the first chip. The second stacked chip is mounted on the first stacked chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer is connected to the connective layer of the first stacked chip.
摘要翻译：堆叠式多芯片包括基底层，第一芯片，第一堆叠芯片和至少一个第二堆叠芯片。基层包括安装面板和再分布层。再分布层安装在安装面板上。第一芯片包括非导电层和连接层。非导电层包括TSV通道。连接层邻接重新分布的层。第一堆叠芯片安装在第一芯片上并且包括非导电层和连接层。非导电层包括连接到第一芯片的TSV通道的TSV通道。第二堆叠芯片安装在第一堆叠芯片上，并且包括非导电层和连接层。非导电层包括TSV通道。连接层连接到第一堆叠芯片的连接层。

46. 发明申请

US20120007251A1 STACKED MULTI-CHIP 有权
标题翻译：堆叠多芯片
公开(公告)号：US20120007251A1
公开(公告)日：2012-01-12
申请号：US12882805
申请日：2010-09-15
申请人： Ting-Ting Hwang , Chen Hsien-Te
发明人： Ting-Ting Hwang , Chen Hsien-Te
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L23/481 , H01L25/0657 , H01L2223/6616 , H01L2223/6666 , H01L2225/06513 , H01L2225/06544 , H01L2924/0002 , H01L2924/00
摘要： A stacked multi-chip comprises a base layer, a first chip, a first stacked chip and at least one second stacked chip. The base layer comprises a mounting panel and a redistributed layer. The redistributed layer is mounted on the mounting panel. The first chip comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer abuts the redistributed layer. The first stacked chip is mounted on the first chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel that is connected to the TSV channel of the first chip. The second stacked chip is mounted on the first stacked chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer is connected to the connective layer of the first stacked chip.
摘要翻译：堆叠式多芯片包括基底层，第一芯片，第一堆叠芯片和至少一个第二堆叠芯片。基层包括安装面板和再分布层。再分布层安装在安装面板上。第一芯片包括非导电层和连接层。非导电层包括TSV通道。连接层邻接重新分布的层。第一堆叠芯片安装在第一芯片上并且包括非导电层和连接层。非导电层包括连接到第一芯片的TSV通道的TSV通道。第二堆叠芯片安装在第一堆叠芯片上，并且包括非导电层和连接层。非导电层包括TSV通道。连接层连接到第一堆叠芯片的连接层。

47. 发明申请

US20190206815A1 DESIGN AND PLACEMENT OF DE-COUPLING CAPACITORS FOR PDN DESIGN 审中-公开
公开(公告)号：US20190206815A1
公开(公告)日：2019-07-04
申请号：US15858404
申请日：2017-12-29
申请人： SEAGATE TECHNOLOGY LLC
发明人： Abhishek Nagaraj LAGUVARAM , Vinod Arjun HUDDAR
IPC分类号： H01L23/66 , H01L23/498 , H01L23/00 , H01L23/50
CPC分类号： H01L23/66 , H01L23/49816 , H01L23/49838 , H01L23/50 , H01L23/642 , H01L24/13 , H01L2223/6666 , H01L2224/14131 , H01L2924/1205 , H01L2924/13091 , H01L2924/381
摘要： Systems and methods for placing capacitors between IC bumps and BGA balls are described. In one embodiment, the method may include placing a ball grid array (BGA) package or integrated circuit (IC) package on a printed circuit board (PCB) of an electronic device, and placing a capacitor between a first BGA ball and a second BGA ball of the BGA package and/or placing a capacitor between a first IC bump and a second IC bump of the IC package to maintain impedance of a power delivery network (PDN) of the BGA package or IC package below a target impedance.

48. 发明申请

US20180259384A1 HOUSING FOR A HIGH-FREQUENCY CHIP 审中-公开
公开(公告)号：US20180259384A1
公开(公告)日：2018-09-13
申请号：US15914637
申请日：2018-03-07
申请人： VEGA GRIESHABER KG
发明人： Roland BAUR , Michael FISCHER , Christoph MUELLER , Daniel SCHULTHEISS
IPC分类号： G01F23/284 , H01L23/00 , G01S13/88 , G01S7/03 , H05K1/18 , H05K1/11 , H01L23/66 , H01L23/10
CPC分类号： G01F23/284 , G01S7/032 , G01S13/88 , H01L23/10 , H01L23/562 , H01L23/66 , H01L2223/6616 , H01L2223/6666 , H01L2223/6677 , H01Q1/225 , H01Q1/2283 , H05K1/11 , H05K1/18
摘要： A housing for a high-frequency chip in a radar device for level measurement is provided, including a high-frequency chip having a high-frequency terminal and a supply terminal; horizontal metal layers; vertical metal connecting lines; and an external supply terminal configured to connect the chip to a circuit board of the device, the chip being attached to one of the horizontal metal layers in an electrically conductive manner, and being embedded in a polymer compound, which is located between the horizontal metal layers, the supply terminal being connected to the external supply terminal via at least one of the horizontal metal layers and via at least one of the vertical metal connecting lines, and the high-frequency terminal being connected to an antenna configured to decouple and receive radar waves, via at least one of the horizontal metal layers and/or via at least one of the vertical metal connections.

49. 发明申请

US20180175792A1 RADIO FREQUENCY (RF) DEVICES WITH RESONANT CIRCUITS TO REDUCE COUPLING 审中-公开
公开(公告)号：US20180175792A1
公开(公告)日：2018-06-21
申请号：US15383775
申请日：2016-12-19
申请人： NXP USA, INC.
发明人： NICK YANG
IPC分类号： H03B1/04 , H03F3/19 , H03F3/21 , H03F1/02 , H01L23/498 , H03B5/08 , H01L23/66
CPC分类号： H01L23/66 , H01L23/49838 , H01L2223/6666 , H03B5/08 , H03F1/0288 , H03F3/19 , H03F3/21 , H03F3/245 , H03F2200/114 , H03F2200/451
摘要： The embodiments described herein use resonant circuits to provide isolation between closely proximate conductors. For example, these resonant circuits can be used to reduce unwanted electromagnetic coupling and minimize crosstalk energy between package leads, bonding wires, and circuit board traces on radio frequency (RF) electronic devices, including RF power amplifiers. To facilitate a reduction in electromagnetic coupling, the resonant circuit is configured resonate with the closely proximate conductors at a selected frequency f0, and when resonating at the selected frequency f0 the resonant circuit provides a path to ground for the crosstalk energy. This path to ground reduces the crosstalk energy that would otherwise be shared between the two closely proximate conductors, and thus provides the electromagnetic isolation between the conductors.

50. 发明授权

US09941227B2 Impedance matching configuration 有权
公开(公告)号：US09941227B2
公开(公告)日：2018-04-10
申请号：US15165317
申请日：2016-05-26
申请人： Ampleon Netherlands B.V.
发明人： Yi Zhu , Josephus Van Der Zanden , Iouri Volokhine , Rob Mathijs Heeres
IPC分类号： H01L23/66 , H01L23/48 , H03F3/191 , H03H7/38 , H01L23/00 , H03F1/56 , H03F3/195
CPC分类号： H01L23/66 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2223/6655 , H01L2223/6666 , H01L2223/6672 , H01L2224/04042 , H01L2224/05552 , H01L2224/05553 , H01L2224/48091 , H01L2224/4813 , H01L2224/48195 , H01L2224/48227 , H01L2224/49175 , H01L2924/00014 , H01L2924/1421 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19104 , H01L2924/19105 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/30111 , H03F1/565 , H03F3/195 , H03F2200/451 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2224/05599
摘要： A package is provided. The package comprises a die and an impedance matching network. The die has a first terminal and a second terminal. The impedance matching network is coupled to the second terminal and comprises a first inductor and a first capacitor. The first inductor comprises first bond wire connections coupled between the second terminal and a first bond pad on the die, and second bond wire connections coupled between the first bond pad and a second bond pad coupled to the first capacitor.

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