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41. 发明授权

US5260971A Apparatus and methods employing distribution preserving tomlinson precoding in transmission of digital data signals 失效
标题翻译：在数字数据信号传输中使用分配保存到milinson预编码的装置和方法
公开(公告)号：US5260971A
公开(公告)日：1993-11-09
申请号：US651563
申请日：1991-02-06
申请人： Paul D. Cole
发明人： Paul D. Cole
IPC分类号： H03M13/25 , H04L25/03 , H04L25/49
CPC分类号： H04L25/4975 , H03M13/25 , H04L25/03343 , H04L25/49 , H04L2025/03802
摘要： A transmitter is provided with a distribution preserving Tomlinson coder which predistorts shaped data signals such that the power of each data signal exiting the coder is substantially similar to the power of the data signal entering the coder and such that upon transmission of the predistorted data signal over a channel, the effect of ISI of the channel is substantially removed. The transmitter is primarily intended for coded modulation systems utilizing a "coset" code, and the predistortion is preferably accomplished according to a linear function ##EQU1## where r.sub.k is a data signal entering the coder, a.sub.l and b.sub.l are the coefficients of polynomials relating to the channel impulse response, x.sub.k is the predistorted data signal exiting the coder, and s.sub.k is a multiple of a given value (N) which is chosen to cause x.sub.k and r.sub.k to occupy identical defined regions in space, where the total length of each defined region is the given value N. One and two dimensional regions are disclosed which are chosen in several ways. Receivers which cooperate with the provided transmitters are also provided. The receivers receive a sequence of signals, and process the sequence to provide a sequence of signals whose k'th term is an estimate of r.sub.k -s.sub.k. From the estimate of r.sub.k -s.sub.k, the receiver generates an estimate of x.sub.k by multiplying the received estimate by the channel ISI. From the estimate of x.sub.k and the estimate of r.sub.k -s.sub.k, the receiver determines the particular value of s.sub.k, and hence the value of an estimate of r.sub.k.
摘要翻译：发射机设置有分布保留Tomlinson编码器，其预失真成形数据信号，使得离开编码器的每个数据信号的功率基本上类似于进入编码器的数据信号的功率，并且使得在传输预失真数据信号之后一个通道，通道的ISI的效果被大大地消除。发射机主要用于利用“陪集”码的编码调制系统，并且预失真优选地根据线性函数“IMAGE”来完成，其中rk是进入编码器的数据信号，a1和b1是与信道脉冲响应xk是离开编码器的预失真数据信号，而sk是给定值（N）的倍数，其被选择为使得xk和rk占据空间中相同的定义区域，其中每个定义的总长度区域是给定值N.公开一个和二维区域，其以多种方式选择。还提供与所提供的发射机配合的接收机。接收器接收信号序列，并处理该序列以提供第k个项是rk-sk的估计的信号序列。从rk-sk的估计，接收机通过将接收到的估计乘以信道ISI来生成x k的估计。从xk的估计和rk-sk的估计，接收器确定sk的特定值，因此确定rk的估计值。

42. 发明授权

US5256073A Electrical connectors for direct connection to plated through holes in circuit board 失效
标题翻译：电连接器，用于直接连接到电路板中的电镀通孔
公开(公告)号：US5256073A
公开(公告)日：1993-10-26
申请号：US892684
申请日：1992-05-27
申请人： Welles K. Reymond , Gregory L. Sorrentino
发明人： Welles K. Reymond , Gregory L. Sorrentino
IPC分类号： H01R12/71 , H01R23/70
CPC分类号： H01R12/58 , H01R12/724 , H05K1/184 , H05K2201/10393 , H05K2203/176
摘要： A pluggable electrical connector is provided having contact elements with first ends soldered to a daughter board, mid-sections which are crimped and bent through ninety degrees, and second ends which have a converging portion and which terminate in bifurcated conical contact portions which make contact with the rims of contact-quality plated through holes of a mother board. By causing contact between the rim and the cone surface, normal forces greater than the mating force are generated. The connector housing includes self-centering funnel openings adjacent the mother board for centering the converging portions of the contact elements therein in a nominal position and for acting as a preloading stop. The housing also includes side-wall locking tabs which hold adjacent rows of contacts at identical fixing points relative to the ninety-degree bend to ensure identical spring parameters for all contact elements. By arranging the housing properly, the contact elements can be manufactured into preloaded spring contacts during assembly by bending and locking the first ends of the contacts past the side-wall locking tabs. Cams or retracting bars can be used with rows or individual contacts to create a ZIF connector and/or a selectively engaged pin enabled connector. Magnets, spring-loaded jack screws, or the like are used in conjunction with the connector to establish and maintain force during mating.
摘要翻译：提供了一种可插拔电连接器，其具有第一端焊接到子板的接触元件，中间部分被压接并弯曲90度，第二端具有会聚部分，并且终止于与第二端接触的分叉圆锥形接触部分接触质量的边缘通过母板的孔穿过。通过引起轮缘和锥面之间的接触，产生大于配合力的法向力。连接器壳体包括邻近母板的自定心漏斗开口，用于将接触元件的会聚部分定位在标称位置并用作预加载止动件。壳体还包括侧壁锁定突出部，其相对于九十度弯曲部在相同的固定点处保持相邻的触点行，以确保用于所有接触元件的相同的弹簧参数。通过适当地布置外壳，接合元件可以通过弯曲和锁定接触件的第一端通过侧壁锁定突片而在组装期间被制造成预加载的弹簧触点。凸轮或回缩杆可以与行或单个触点一起使用，以创建ZIF连接器和/或选择性接合的引脚使能连接器。与连接器一起使用磁铁，弹簧式千斤顶螺丝等，以在配合期间建立并保持力。

43. 发明授权

US5157651A Apparatus and method for determining line rates 失效
标题翻译：用于确定线路速率的装置和方法
公开(公告)号：US5157651A
公开(公告)日：1992-10-20
申请号：US558701
申请日：1990-07-26
申请人： Emil Ghelberg , Patrick A. Evans , Seng P. Lee , Don W. Liyanage
发明人： Emil Ghelberg , Patrick A. Evans , Seng P. Lee , Don W. Liyanage
IPC分类号： H04L25/02
CPC分类号： H04L25/0262
摘要： Apparatus and methods for automatically determining the bit rate of an incoming signal are provided. The apparatus includes a counter, a logic circuit, and a histogram generating circuit. The counter counts the number of fast reference clock cycles which fit within each pulse of the incoming signal for a statistically significant number of pulses and provides indications thereof to the logic circuit. The logic circuit associates each of the indications with one of a plurality of allowable bit rates. The histogram generating circuit tracks the numbers of times the counts are associated with each allowable bit rate. In one embodiment, the allowable bit rate most often chosen is determined to be the bit rate of the incoming signal. In another embodiment, if a DDS1 line rate is determined to be the bit rate most often chosen, the DDS2 rate associated with the DDS1 line rate is provisionally selected. Also, if a DDS2 line is determined to be the bit rate most often chosen, that DDS2 line rate is provisionally selected. Then a frame pattern detector is used to detect the DDS/SC frame pattern. If a frame pattern is detected, the DDS2 rate provisionally selected is determined to be the bit rate of the incoming signal; if not, the DDS1 line rate associated with the DDS2 provisionally selected is chosen.
摘要翻译：提供用于自动确定输入信号的比特率的装置和方法。该装置包括计数器，逻辑电路和直方图发生电路。计数器计数适合输入信号的每个脉冲内的快速参考时钟周期的数量，用于统计上显着数量的脉冲，并将其指示给逻辑电路。逻辑电路将每个指示与多个可允许比特率中的一个相关联。直方图生成电路跟踪计数与每个允许的比特率相关联的次数。在一个实施例中，最常选择的容许比特率被确定为输入信号的比特率。在另一个实施例中，如果DDS1线路速率被确定为最常选择的比特率，则暂时选择与DDS1线路速率相关联的DDS2速率。此外，如果DDS2线路被确定为最常选择的比特率，则暂时选择该DDS2线路速率。然后使用帧模式检测器来检测DDS / SC帧模式。如果检测到帧模式，则暂时选择的DDS2速率被确定为输入信号的比特率; 如果不是，则选择与暂时选择的DDS2相关联的DDS1线路速率。

44. 发明授权

US4877364A Captive screw and assembly 失效
标题翻译：固定螺丝和组装
公开(公告)号：US4877364A
公开(公告)日：1989-10-31
申请号：US54299
申请日：1987-05-26
申请人： Gregory Sorrentino
发明人： Gregory Sorrentino
IPC分类号： F16B5/02 , F16B21/09 , F16B35/04 , F16B41/00
CPC分类号： F16B5/0275 , F16B21/09 , F16B41/002 , F16B35/048 , F16B5/02 , Y10S411/999 , Y10T403/75
摘要： This invention relates to an improved captive screw and assembly, and particularly a screw which may be held loosely captive in the threaded hole of a support member. The invention comprises a machine screw or cold formed fastener with an unthreaded interrupted mid-section that separates two spaced-apart threaded portions of the fastener, with both threaded portions of the fastener preferably of a similar thread size, and with the unthreaded mid-section of the screw of a diameter less than the root diameter of the threaded sections. The screw may be completely removed or readily installed into threaded engagement with a female threaded hole in the support member, when necessary, by first manually aligning the fastener axis with the axis of the threaded hole, then rotating the fastener to engage the starting threads of the fastener with those of the female threaded hole, and further continued rotating of the fastener in a conventional manner. The fastener may clamp a panel member to the support member. The panel member may be formed with a shaped hole to enable removal of the panel member from engagement with the fastener, when the fastener is held in the loosely captive mode to the support member.
摘要翻译：本发明涉及一种改进的紧固螺钉和组件，特别是一种可以松动地固定在支撑构件的螺纹孔中的螺钉。本发明包括机器螺钉或冷成形紧固件，其具有无螺纹中断的中间部分，其分离紧固件的两个间隔开的螺纹部分，其中紧固件的两个螺纹部分优选地具有类似的螺纹尺寸，并且与无螺纹的中间部分的螺杆直径小于螺纹部分的根部直径。当需要时，可以通过首先将紧固件轴线与螺纹孔的轴线对准，然后旋转紧固件以使紧固件与起始螺纹接合，螺钉可以被完全移除或容易地安装成与支撑构件中的内螺纹孔螺纹接合紧固件与内螺纹孔的紧固件，并且以常规方式进一步继续旋转紧固件。紧固件可以将面板构件夹紧到支撑构件。面板构件可以形成有成形孔，以便当紧固件以松散捕获模式保持在支撑构件上时，能够移除面板构件与紧固件的接合。

45. 发明授权

US4811360A Apparatus and method for adaptively optimizing equalization delay of data communication equipment 失效
标题翻译：适应性优化数据通信设备均衡延迟的装置和方法
公开(公告)号：US4811360A
公开(公告)日：1989-03-07
申请号：US144534
申请日：1988-01-14
申请人： William J. Potter
发明人： William J. Potter
IPC分类号： H04L25/03 , H03H7/30
CPC分类号： H04L25/03038
摘要： A data communication equipment equalizer which minimizes the total training time delay (RTS-CTS) is disclosed. The total RTS-CTS delay of the provided equalizer consists of a delay due to a minimal training sequence required for the equalizer coefficients to converge given a low distortion channel, plus whatever delay is necessary for the equalizer coefficients to converge given the particular channel. The equalizer of the invention preferably comprises: first and second FIRs each having a plurality of taps for storing data signal samples over time, a plurality of tap gain for multiplying the equalizer coefficients with the stored data samples, a coefficient update for comparing the sum of the tap gain products to an ideal value and for changing equalizer coefficients accordingly, and a processor for processing the communications data according to the adapted equalizer coefficients; a buffer delay for receiving and storing the communications data transmitted after the completion of the training sequence and before the equalizer coefficients have been sufficiently adapted to allow substantially error free transmission; and a data decision for deciding what ideal data value to assign a processed data sample. While the training sequence length is minimized for an optimal channel, no communications data is lost in a non-optimal channel as the buffer delay stores the communications data while the FIRs use the communications data to continue to adapt the equalizer coefficients.
摘要翻译：公开了一种使总训练时间延迟（RTS-CTS）最小化的数据通信设备均衡器。所提供的均衡器的总RTS-CTS延迟由给定低失真信道的均衡器系数收敛所需的最小训练序列加上给定特定信道的均衡器系数收敛所需的任何延迟的延迟构成。本发明的均衡器优选地包括：第一和第二FIR，每个具有多个用于随时间存储数据信号样本的抽头，用于将均衡器系数与存储的数据样本相乘的多个抽头增益，用于比较抽头增益产品达到理想值并相应地改变均衡器系数;以及处理器，用于根据适配的均衡器系数处理通信数据; 缓冲延迟，用于接收和存储在完成训练序列之后发送的通信数据，并且在均衡器系数已被充分地适于允许基本上无差错传输之前; 以及用于决定分配处理数据样本的理想数据值的数据决定。虽然训练序列长度被最小化为最佳信道，但是由于缓冲器延迟存储通信数据，而FIR使用通信数据继续适应均衡器系数，所以在非最佳信道中没有通信数据丢失。

46. 发明授权

US4727536A Variable control and data rates in highly efficient multiplexer 失效
标题翻译：高效多路复用器中的变量控制和数据速率
公开(公告)号：US4727536A
公开(公告)日：1988-02-23
申请号：US876232
申请日：1986-06-19
申请人： Jonathan M. Reeves , David J. Manning
发明人： Jonathan M. Reeves , David J. Manning
IPC分类号： H04J3/12 , H04J3/16
CPC分类号： H04J3/1682 , H04J3/12 , H04Q2213/13166 , H04Q2213/13174 , H04Q2213/13292 , H04Q2213/13332
摘要： Methods and apparatuses for efficiently allocating bandwidth to data, control and multiplexer overhead and for providing flexible data rates and control rates are provided. The apparatuses of the invention are used in a time division miltiplexer which multiplexes for transmission over and for receipt from at least one aggregate line in accord with at least one frame, data and control information from a plurality of channels and multiplexer overhead information. The method comprises: determining the requested data transmission rates for each data channel and the aggregate line; determining the requested control transmission rates for each data channel; summing the total of the requested data transmission rates to produce a second total, summing the first and second totals, determining whether the sum of the first and second total exceeds the determined transmission rate of the aggregate line, decreasing the data rate channel thereby changing the first total to ensure that the aggregate line rate is at least equal to the sum of the first and second total.
摘要翻译：提供了有效地将带宽分配给数据，控制和多路复用器开销以及提供灵活的数据速率和控制速率的方法和装置。本发明的装置用在时分多路复用器中，该多路复用器根据来自多个信道的至少一个帧，数据和控制信息以及多路复用器开销信息进行复用，以从至少一个汇总线传输和接收。该方法包括：确定每个数据信道和聚合线路的请求数据传输速率; 确定每个数据信道的所请求的控制传输速率; 将所请求的数据传输速率的总和相加以产生第二总数，对第一和第二总计进行求和，确定第一和第二总数的和是否超过所确定的总线的传输速率，从而减少数据速率信道，从而改变首先确保总线速率至少等于第一和第二总数的总和。

47. 发明授权

US4667180A Continuous time domain analog-digital converter 失效
标题翻译：连续时域模数转换器
公开(公告)号：US4667180A
公开(公告)日：1987-05-19
申请号：US822396
申请日：1986-01-27
申请人： Jeffrey I. Robinson
发明人： Jeffrey I. Robinson
IPC分类号： H03M1/44
CPC分类号： H03M1/442
摘要： A continuous time domain parallel analog to digital converter is provided for accomplishing the general successive rectification algorithm I.sub.out =2.vertline.I.sub.in .vertline.-I.sub.ref. One stage of the continuous parallel converter comprises a complimentary transistor pair and three current mirrors. The transistor pair and a first current mirror and a second current mirror act as a rectifier. The complimentary transistor pair has I.sub.in connected to common sources, and common gates connected to ground. A first current mirror has its input connected to the drain of the n-type transistor of the complimentary pair and its output connected to the drain of the p-type transistor. The second current mirror acts as an amplifier by having its input transistors being half the width of the corresponding output transistors. The second mirror has its input connected to the output of the first current mirror, and its output going to I.sub.out. The third current mirror acts to subtract I.sub.ref from the rectified amplified V.sub.in, and has V.sub.ref as an input and an output connected to I.sub.out. The I.sub.out of one stage acts as the I.sub.in to a second stage, and the stages are cascaded. The direction of flow of I.sub.in to each stage provides bits of information. Where a voltage signal is to be converted into digital form, the signal is transformed into a current signal I.sub.in through the use a transconductance amplifier prior to digital conversion by the provided continuous parallel A/D converter.
摘要翻译：提供连续的时域并行模数转换器，用于实现一般的连续整流算法Iout = 2 | Iin | -Iref。连续并联转换器的一个阶段包括互补晶体管对和三个电流镜。晶体管对和第一电流镜和第二电流镜用作整流器。互补晶体管对具有连接到公共源的Iin，并且公共栅极连接到地。第一电流镜的输入连接到互补对的n型晶体管的漏极，其输出连接到p型晶体管的漏极。第二电流镜通过使其输入晶体管为相应输出晶体管的宽度的一半作为放大器。第二个反射镜的输入连接到第一个电流镜的输出端，其输出转到Iout。第三电流镜用于从经整流放大的Vin中减去Iref，并具有Vref作为输入，输出连接到Iout。一个阶段的Iout作为第二阶段的阶段，阶段是级联的。 Iin到每个阶段的流动方向提供了一些信息。在将电压信号转换为数字形式的情况下，通过所提供的连续并行A / D转换器进行数字转换之前，通过使用跨导放大器将信号转换为电流信号Iin。

48. 发明授权

US2464107A Material working apparatus 失效
公开(公告)号：US2464107A
公开(公告)日：1949-03-08
申请号：US52900944
申请日：1944-03-31
申请人： WESTERN ELECTRIC CO
发明人： VAUGHN WATERS DANIEL
IPC分类号： B23B3/24 , H01J9/28
CPC分类号： H01J9/28 , B23B3/24 , Y10T409/309184

49. 发明授权

US6141322A Method and apparatus for precedence and preemption in ATM connection admission control 失效
标题翻译： ATM连接准入控制中优先权和抢占的方法和装置
公开(公告)号：US6141322A
公开(公告)日：2000-10-31
申请号：US853654
申请日：1997-05-09
申请人： Scott Michael Poretsky
发明人： Scott Michael Poretsky
IPC分类号： H04L12/56
CPC分类号： H04L49/20 , H04L49/254 , H04L2012/563 , H04L2012/5651
摘要： A informational element (IE) is provided which permits the user to assign a precedence level to a call. A precedence/preemption connection admission control (P/P CAC) for use with any bandwidth allocation algorithm is also provided for processing a virtual circuit connection (VCC) request having an assigned precedence level, and for preempting one or more VCCs when a VCC request having a relatively higher precedence level is received at an ATM switch. Preferably, a resource allocator containing two databases, one listing all active virtual circuit connections and a second listing all preempted virtual circuits, is provided for storing the call parameters of preempted VCCs. According to a preferred embodiment, preempted VCCs may be reestablished. Reestablishment occurs according to various criteria. In addition, a second embodiment of a P/P CAC is provided in which active VCCs identified for preemption are buffered until the requested VCC is accepted by a downstream ATM switch. Once acceptance is received, the identified calls are released. If downstream acceptance is not provided prior to a timeout, the requested VCC is released and the VCCs identified for preemption are kept active.
摘要翻译：提供信息元素（IE），其允许用户为呼叫分配优先级。还提供了与任何带宽分配算法一起使用的优先/抢占连接准入控制（P / P CAC），用于处理具有分配的优先级的虚拟电路连接（VCC）请求，并且用于在VCC请求时抢占一个或多个VCC 在ATM交换机处接收到具有相对较高优先级的信号。优选地，提供包含两个数据库的资源分配器，一个列出所有活动的虚拟电路连接，以及列出所有被抢占的虚拟电路的资源分配器，用于存储被抢占的VCC的呼叫参数。根据优选实施例，可以重新建立被抢占的VCC。重建按照各种标准进行。此外，提供了P / P CAC的第二实施例，其中缓存识别用于抢占的活动VCC被缓冲，直到所请求的VCC被下游ATM交换机接受。一旦接收到接收，所发出的呼叫被释放。如果在超时之前未提供下游接收，则请求的VCC被释放，并且识别为抢占的VCC保持活动。

50. 发明授权

US6032187A Data service unit having inband networking protocol packet processing capabilities 失效
标题翻译：具有带内网络协议分组处理能力的数据业务单元
公开(公告)号：US6032187A
公开(公告)日：2000-02-29
申请号：US658842
申请日：1996-05-31
申请人： Robert A. Blain
发明人： Robert A. Blain
IPC分类号： H04L12/24 , G06F13/14
CPC分类号： H04L41/0213
摘要： An intelligent data service unit (DSU) which terminates a digital subscriber loop is provided and includes a digital subscriber loop interface which receives incoming data from a DDS line of the service provider, a framing and signal converter for taking the incoming data and formatting the data for output, an output interface, a processor connected to the framing and signal converter and to each of the interfaces, and a data memory buffer coupled to the processor. All data provided to the DSU from the digital subscriber loop is reformatted by the framing and signal converter and propagated to the output interface as it is received. At the same time, a copy of the data is buffered into the memory, and the processor scans the memory to find and synchronize with an networking protocol frame (e.g., an IP frame) Once synchronized, the processor compares the destination address in the IP frame to the network address of the DSU. If the addresses match, the IP frame is stored for processing (e.g., the DSU may be directed to gather statistical information and/or to configure the DSU according to protocol standards). If the addresses do not match, the frame is discarded by the processor. The DSU is preferably SNMP compatible and is provided with a management information base which allows the SNMP controller to configure, diagnose and maintain circuit integrity.
摘要翻译：提供了终止数字用户环路的智能数据服务单元（DSU），并且包括数字用户环路接口，其从服务提供商的DDS线路接收输入数据，成帧和信号转换器，用于接收输入数据并格式化数据用于输出，输出接口，连接到成帧和信号转换器以及每个接口的处理器以及耦合到处理器的数据存储器缓冲器。从数字用户环路提供给DSU的所有数据由成帧和信号转换器重新格式化，并在接收时传播到输出接口。同时，将数据的副本缓冲到存储器中，并且处理器扫描存储器以找到并与网络协议帧（例如，IP帧）同步。一旦同步，处理器将IP中的目的地地址进行比较帧到DSU的网络地址。如果地址匹配，则IP帧被存储用于处理（例如，可以指示DSU收集统计信息和/或根据协议标准配置DSU）。如果地址不匹配，则该帧被处理器丢弃。 DSU优选地是SNMP兼容的，并且具有允许SNMP控制器配置，诊断和维持电路完整性的管理信息库。

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