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    • 1. 发明授权
    • Apparatus and method for determining line rates
    • 用于确定线路速率的装置和方法
    • US5157651A
    • 1992-10-20
    • US558701
    • 1990-07-26
    • Emil GhelbergPatrick A. EvansSeng P. LeeDon W. Liyanage
    • Emil GhelbergPatrick A. EvansSeng P. LeeDon W. Liyanage
    • H04L25/02
    • H04L25/0262
    • Apparatus and methods for automatically determining the bit rate of an incoming signal are provided. The apparatus includes a counter, a logic circuit, and a histogram generating circuit. The counter counts the number of fast reference clock cycles which fit within each pulse of the incoming signal for a statistically significant number of pulses and provides indications thereof to the logic circuit. The logic circuit associates each of the indications with one of a plurality of allowable bit rates. The histogram generating circuit tracks the numbers of times the counts are associated with each allowable bit rate. In one embodiment, the allowable bit rate most often chosen is determined to be the bit rate of the incoming signal. In another embodiment, if a DDS1 line rate is determined to be the bit rate most often chosen, the DDS2 rate associated with the DDS1 line rate is provisionally selected. Also, if a DDS2 line is determined to be the bit rate most often chosen, that DDS2 line rate is provisionally selected. Then a frame pattern detector is used to detect the DDS/SC frame pattern. If a frame pattern is detected, the DDS2 rate provisionally selected is determined to be the bit rate of the incoming signal; if not, the DDS1 line rate associated with the DDS2 provisionally selected is chosen.
    • 提供用于自动确定输入信号的比特率的装置和方法。 该装置包括计数器,逻辑电路和直方图发生电路。 计数器计数适合输入信号的每个脉冲内的快速参考时钟周期的数量,用于统计上显着数量的脉冲,并将其指示给逻辑电路。 逻辑电路将每个指示与多个可允许比特率中的一个相关联。 直方图生成电路跟踪计数与每个允许的比特率相关联的次数。 在一个实施例中,最常选择的容许比特率被确定为输入信号的比特率。 在另一个实施例中,如果DDS1线路速率被确定为最常选择的比特率,则暂时选择与DDS1线路速率相关联的DDS2速率。 此外,如果DDS2线路被确定为最常选择的比特率,则暂时选择该DDS2线路速率。 然后使用帧模式检测器来检测DDS / SC帧模式。 如果检测到帧模式,则暂时选择的DDS2速率被确定为输入信号的比特率; 如果不是,则选择与暂时选择的DDS2相关联的DDS1线路速率。
    • 2. 发明授权
    • Automatic detector and selector of RS-232 or V.35 interface
    • RS-232或V.35接口的自动检测器和选择器
    • US5331672A
    • 1994-07-19
    • US727822
    • 1991-07-09
    • Patrick A. EvansEugene Vellucci, Jr.
    • Patrick A. EvansEugene Vellucci, Jr.
    • H04L27/00H04L23/00
    • H04L27/0008
    • An automatic detection and selection circuit resident in a DCE is provided. The circuit is coupled to the DCE interface connector and detects receipt by the DCE of V.35 and RS-232 transmit data signals, distinguishes between those signals, and selects circuitry for passing the data therethrough. The circuit comprises a switch coupled to a first TX data terminal (pin 2 or P) of the DCE interface connector, first and second line receiving circuits, a microprocessor, and a relay. The first line receiving circuit is coupled to a first pole of the switch and to the second TX data terminal (pin S) of the DCE interface connector and provides indications as to whether or not an input signal is present at at least one of pins P and S. The second line receiving circuit is coupled to the second pole of the switch and provides indications as to whether or not a valid RS-232 transmit data signal is detected. The microprocessor is coupled to the outputs of the line receiving circuits, and based on the indications output thereby, appropriately controls the relay, and hence the switch. The microprocessor first checks in a V.35 mode as to whether a data signal is being received. It then checks in a RS-232 mode as to whether the data signal is a valid RS-232 signal. If not, it switches the circuit back to the V.35 mode.
    • 提供驻留在DCE中的自动检测和选择电路。 该电路耦合到DCE接口连接器,并检测到DCE接收到V.35和RS-232发送数据信号,区分这些信号,并选择用于传递数据的电路。 电路包括耦合到DCE接口连接器的第一TX数据端(引脚2或P),第一和第二线路接收电路,微处理器和继电器的开关。 第一行接收电路耦合到开关的第一极和DCE接口连接器的第二TX数据端(引脚S),并提供关于输入信号是否存在于引脚P中的至少一个的指示 和第二线路接收电路耦合到开关的第二极,并提供关于是否检测到有效的RS-232发送数据信号的指示。 微处理器耦合到线路接收电路的输出,并且由此基于指示输出,适当地控制继电器,并因此适当地控制开关。 微处理器首先检查V.35模式是否正在接收数据信号。 然后它检查RS-232模式是否数据信号是有效的RS-232信号。 如果不是,则将电路切换回V.35模式。