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    • 2. 发明授权
    • Bit interleaved multiplexer system providing byte synchronization for
communicating apparatuses
    • US4710920A
    • 1987-12-01
    • US876229
    • 1986-06-19
    • David J. Manning
    • David J. Manning
    • G06F5/10H04J3/12H04J3/16H04J3/06
    • G06F5/10H04J3/12
    • A bit interleaved multiplexer system permitting byte synchronization of apparatuses communicating thereon without the consumption of additional aggregate bandwidth is provided. The system comprises a multiplexer, a demultiplexer, and an aggregate line. The multiplexer includes a transmit frame which includes a memory means and at least one recirculating counter which is programmed according to a framing algorithm, and a transmit data buffer and transmit mark buffer for each terminal which is to be connected to the system. Every time the transmit frame requests a predetermined bit of a byte (e.g. an MSB), a "1" is marked in the mark buffer. When a bit leaves the mark buffer it causes the terminal to write a bit into the transmit data buffer, with the written bit being an MSB when the bit leaving the mark buffer is a "1". By arranging the delay through the transmit mark and data buffers to be equal to I(L)+C, where I is an integer greater than zero, L is the length of a byte, and C is a constant phase shift, when the transmit frame requests an MSB, an MSB will be sent by the transmit data buffer C requests later. If C is set to zero, an MSB will be sent when the transmit frame so requests. The demultiplexer of the invention includes a receive frame which is synchronized with the transmit frame and which includes a memory means and at least one recirculating counter, and a receive data buffer and receive mark buffer for each terminal which is connected to the system. Every time the framing algorithm indicates that an MSB is being received by the receive frame, a "1" is marked into the receive mark buffer while the bit is forwarded to the receive data buffer. Because the receive mark and receive data buffers are equal in length, the terminal receiving information from the buffers will be provided with the information as to whether the received bit is an MSB.
    • 3. 发明授权
    • Industrial caster wheel with elastomeric spring/damper member and adjustment member
    • 具有弹性弹簧/阻尼器构件和调节构件的工业脚轮
    • US07093319B2
    • 2006-08-22
    • US10658198
    • 2003-09-10
    • Henri E. Lemeur, Jr.John D. SwartzDavid J. Manning
    • Henri E. Lemeur, Jr.John D. SwartzDavid J. Manning
    • B60B33/00
    • B60B33/045Y10T16/184Y10T16/193Y10T16/212Y10T16/3834
    • An industrial caster wheel assembly including a base member, a wheel, side plates, a housing, a pivot axle, a suspension assembly and an adjustment assembly. The suspension assembly includes an adjustable axle, a support member, and a plate. The support member allows one of the wheel and the base member to rotate about the pivot axle as the adjustable axle compresses the support member by contacting the plate. The adjustment assembly adjusts the height of the industrial caster wheel by adjusting the pressure applied by the adjustable axle to the support member. The industrial caster wheel assembly may alternatively include at least one adjustment assembly that can be placed in contact with at least one of the second axle to press the second axle at least indirectly against the elastomeric support member or the first axle to press the first axle toward the center of the housing.
    • 一种工业脚轮组合件,包括基座构件,车轮,侧板,壳体,枢轴,悬架组件和调节组件。 悬架组件包括可调轴,支撑构件和板。 当可调节轴通过接触板来压缩支撑构件时,支撑构件允许轮和基部构件中的一个围绕枢转轴线旋转。 调节组件通过将可调节轴施加的压力调节到支撑构件来调节工业脚轮的高度。 工业脚轮车轮组件可以可选地包括至少一个调节组件,其可以放置成与第二轴中的至少一个相接触,以将至少间接地压靠第二轴的第二轴抵靠弹性体支撑构件或第一轴以将第一轴向 房屋的中心。
    • 4. 发明授权
    • Ground anchor
    • 地锚
    • US4825604A
    • 1989-05-02
    • US137420
    • 1987-12-22
    • David J. Manning
    • David J. Manning
    • E02D5/80
    • E02D5/80
    • A ground anchor is described for anchoring one end of a cable. The anchor includes an elongated stake member, attachment means on the front edge of the stake for attachment of one end of a cable, a support arm connected at one end to the upper end of the stake, and retention means on the opposite end of the support arm. The retention means holds down the cable when tension is applied. The support arm is preferably pivotable between an outward position for use and an inward position for storage and transport.
    • 描述了用于锚定电缆的一端的接地锚。 锚固件包括细长的桩构件,在桩的前边缘处的附接装置,用于连接电缆的一端,支撑臂在一端连接到桩的上端,并且保持装置位于桩的另一端 支撑臂。 当施加张力时,保持装置压住电缆。 支撑臂优选在使用的向外位置和用于存储和运输的向内位置之间可枢转。
    • 5. 发明授权
    • Variable control and data rates in highly efficient multiplexer
    • 高效多路复用器中的变量控制和数据速率
    • US4727536A
    • 1988-02-23
    • US876232
    • 1986-06-19
    • Jonathan M. ReevesDavid J. Manning
    • Jonathan M. ReevesDavid J. Manning
    • H04J3/12H04J3/16
    • H04J3/1682H04J3/12H04Q2213/13166H04Q2213/13174H04Q2213/13292H04Q2213/13332
    • Methods and apparatuses for efficiently allocating bandwidth to data, control and multiplexer overhead and for providing flexible data rates and control rates are provided. The apparatuses of the invention are used in a time division miltiplexer which multiplexes for transmission over and for receipt from at least one aggregate line in accord with at least one frame, data and control information from a plurality of channels and multiplexer overhead information. The method comprises: determining the requested data transmission rates for each data channel and the aggregate line; determining the requested control transmission rates for each data channel; summing the total of the requested data transmission rates to produce a second total, summing the first and second totals, determining whether the sum of the first and second total exceeds the determined transmission rate of the aggregate line, decreasing the data rate channel thereby changing the first total to ensure that the aggregate line rate is at least equal to the sum of the first and second total.
    • 提供了有效地将带宽分配给数据,控制和多路复用器开销以及提供灵活的数据速率和控制速率的方法和装置。 本发明的装置用在时分多路复用器中,该多路复用器根据来自多个信道的至少一个帧,数据和控制信息以及多路复用器开销信息进行复用,以从至少一个汇总线传输和接收。 该方法包括:确定每个数据信道和聚合线路的请求数据传输速率; 确定每个数据信道的所请求的控制传输速率; 将所请求的数据传输速率的总和相加以产生第二总数,对第一和第二总计进行求和,确定第一和第二总数的和是否超过所确定的总线的传输速率,从而减少数据速率信道,从而改变 首先确保总线速率至少等于第一和第二总数的总和。