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1. 发明授权

US5157651A Apparatus and method for determining line rates 失效
标题翻译：用于确定线路速率的装置和方法
公开(公告)号：US5157651A
公开(公告)日：1992-10-20
申请号：US558701
申请日：1990-07-26
申请人： Emil Ghelberg , Patrick A. Evans , Seng P. Lee , Don W. Liyanage
发明人： Emil Ghelberg , Patrick A. Evans , Seng P. Lee , Don W. Liyanage
IPC分类号： H04L25/02
CPC分类号： H04L25/0262
摘要： Apparatus and methods for automatically determining the bit rate of an incoming signal are provided. The apparatus includes a counter, a logic circuit, and a histogram generating circuit. The counter counts the number of fast reference clock cycles which fit within each pulse of the incoming signal for a statistically significant number of pulses and provides indications thereof to the logic circuit. The logic circuit associates each of the indications with one of a plurality of allowable bit rates. The histogram generating circuit tracks the numbers of times the counts are associated with each allowable bit rate. In one embodiment, the allowable bit rate most often chosen is determined to be the bit rate of the incoming signal. In another embodiment, if a DDS1 line rate is determined to be the bit rate most often chosen, the DDS2 rate associated with the DDS1 line rate is provisionally selected. Also, if a DDS2 line is determined to be the bit rate most often chosen, that DDS2 line rate is provisionally selected. Then a frame pattern detector is used to detect the DDS/SC frame pattern. If a frame pattern is detected, the DDS2 rate provisionally selected is determined to be the bit rate of the incoming signal; if not, the DDS1 line rate associated with the DDS2 provisionally selected is chosen.
摘要翻译：提供用于自动确定输入信号的比特率的装置和方法。该装置包括计数器，逻辑电路和直方图发生电路。计数器计数适合输入信号的每个脉冲内的快速参考时钟周期的数量，用于统计上显着数量的脉冲，并将其指示给逻辑电路。逻辑电路将每个指示与多个可允许比特率中的一个相关联。直方图生成电路跟踪计数与每个允许的比特率相关联的次数。在一个实施例中，最常选择的容许比特率被确定为输入信号的比特率。在另一个实施例中，如果DDS1线路速率被确定为最常选择的比特率，则暂时选择与DDS1线路速率相关联的DDS2速率。此外，如果DDS2线路被确定为最常选择的比特率，则暂时选择该DDS2线路速率。然后使用帧模式检测器来检测DDS / SC帧模式。如果检测到帧模式，则暂时选择的DDS2速率被确定为输入信号的比特率; 如果不是，则选择与暂时选择的DDS2相关联的DDS1线路速率。

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