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41. 发明申请

US20080090412A1 Pre-silicide spacer removal 失效
标题翻译：预硅化物间隔物去除
公开(公告)号：US20080090412A1
公开(公告)日：2008-04-17
申请号：US11548842
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Jun Jung Kim , Yaocheng Liu , Huilong Zhu
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Jun Jung Kim , Yaocheng Liu , Huilong Zhu
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/32 , H01L29/6653 , H01L29/66545 , H01L29/6659
摘要： A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers to form source and drain regions. The method deposits a mask over the gate conductor, the spacers, and the source and drain regions. The mask is recessed to a level below a top of the gate conductor but above the source and drain regions, such that the spacers are exposed and the source and drain regions are protected by the mask. With the mask in place, the method then safely removes the spacers and the gate cap, without damaging the source/drain regions or the isolation regions (which are protected by the mask). Next, the method removes the mask and then forms silicide regions on the gate conductor and the source and drain regions.
摘要翻译：一种方法在衬底上形成栅极导体，同时在栅极导体的侧面和栅极导体的顶部上形成栅极盖。在衬底中形成隔离区域，并且该方法将杂质注入未被栅极导体和间隔物保护的衬底的暴露区域中以形成源区和漏区。该方法在栅极导体，间隔物以及源极和漏极区域上沉积掩模。掩模凹陷到栅极导体的顶部下方但在源极和漏极区域之上的水平面，使得间隔物被暴露，并且源极和漏极区域被掩模保护。在掩模就位的情况下，该方法然后安全地去除间隔物和栅极盖，而不损坏源极/漏极区域或隔离区域（被掩模保护）。接下来，该方法移除掩模，然后在栅极导体和源极和漏极区域上形成硅化物区域。

42. 发明申请

US20070281413A1 N-CHANNEL MOSFETS COMPRISING DUAL STRESSORS, AND METHODS FOR FORMING THE SAME 有权
标题翻译：包含双重压力机的N沟道MOSFET及其形成方法
公开(公告)号：US20070281413A1
公开(公告)日：2007-12-06
申请号：US11840795
申请日：2007-08-17
申请人： Jinghong Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
发明人： Jinghong Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/324 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S257/90
摘要： The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.
摘要翻译：本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。具体地说，n-FET包括第一和第二图案应力层，它们都包含碳取代和拉伸应力单晶半导体。第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

43. 发明授权

US07632724B2 Stressed SOI FET having tensile and compressive device regions 失效
标题翻译：具有拉伸和压缩装置区域的受压SOI FET
公开(公告)号：US07632724B2
公开(公告)日：2009-12-15
申请号：US11673716
申请日：2007-02-12
申请人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
发明人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
IPC分类号： H01L21/00
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203 , H01L29/7843
摘要： A method is provided for fabricating a field effect transistor (“FET”) having a channel region in a semiconductor-on-insulator (“SOI”) layer of an SOI substrate. Desirably, in such method, a sacrificial stressed layer is formed to overlie a first portion of an active semiconductor region but not overlie second portion of the active semiconductor region which shares a common boundary with the first portion. After forming trenches in the SOI layer, the SOI substrate is heated with the stressed layer thereon sufficiently to cause the stressed layer to relax, thereby causing the stressed layer to apply a first stress to the first portion and to apply a second stress to the second portion. For example, when the first stress is tensile, the second stress is compressive, or the first stress can be compressive when the second stress is tensile. Desirably, the stressed layer is then removed to expose the first and second portions of the active semiconductor region. Desirably, the field effect transistor (“FET”) is formed to include (i) a source region in the first portion, (ii) a drain region in the first portion, and (iii) a channel region in the second portion.
摘要翻译：提供一种用于制造在SOI衬底的绝缘体上半导体（“SOI”）层中具有沟道区的场效应晶体管（“FET”）的方法。理想地，在这种方法中，牺牲应力层形成为覆盖有源半导体区域的第一部分，但不覆盖与第一部分共用共同边界的有源半导体区域的第二部分。在SOI层中形成沟槽之后，将SOI衬底上的应力层充分加热，使得应力层松弛，从而使应力层对第一部分施加第一应力并向第二部分施加第二应力一部分。例如，当第一应力是拉伸时，第二应力是压缩的，或者当第二应力是拉伸时，第一应力可以是压缩的。理想地，应力层被去除以暴露有源半导体区域的第一和第二部分。期望地，场效应晶体管（“FET”）形成为包括（i）第一部分中的源极区域，（ii）第一部分中的漏极区域，以及（iii）第二部分中的沟道区域。

44. 发明申请

US20090166770A1 METHOD OF FABRICATING GATE ELECTRODE FOR GATE OF MOSFET AND STRUCTURE THEREOF 审中-公开
标题翻译：制造MOSFET栅极电极的方法及其结构
公开(公告)号：US20090166770A1
公开(公告)日：2009-07-02
申请号：US11968396
申请日：2008-01-02
申请人： Oleg Gluschenkov , Sameer H. Jain , Yaocheng Liu
发明人： Oleg Gluschenkov , Sameer H. Jain , Yaocheng Liu
IPC分类号： H01L29/423 , H01L21/28
CPC分类号： H01L29/4983 , H01L21/268 , H01L21/2686 , H01L21/2807 , H01L21/823828 , H01L21/823842
摘要： A method of fabricating a gate electrode for a gate of a metal oxide semiconductor field effect transistor (MOSFET), where the transistor has a structure incorporating a gate disposed on a substrate. The substrate comprises a source-drain region. The gate includes a gate electrode disposed on a gate dielectric and surrounded by a spacer. The gate electrode includes a capping layer of polysilicon (poly-Si) and a thin polycrystalline intermixed silicon-germanium (SiGe) layer superposed on the gate dielectric. The thin polycrystalline intermixed silicon-germanium (SiGe) layer may be formed by a high-temperature ultrafast melt-crystalization annealing process. The melt-crystallization process of the intermixed silicon-germanium provides an active dopant concentration that reduces the width of a depletion region formed at an interface of the polycrystalline intermixed silicon-germanium (SiGe) layer and the gate dielectric.
摘要翻译：一种制造用于金属氧化物半导体场效应晶体管（MOSFET）的栅极的栅极的方法，其中晶体管具有结合设置在衬底上的栅极的结构。衬底包括源极 - 漏极区域。栅极包括设置在栅极电介质上并被间隔物包围的栅电极。栅电极包括多晶硅（poly-Si）的覆盖层和叠加在栅极电介质上的薄的多晶混合的硅 - 锗（SiGe）层。薄多晶混合硅锗（SiGe）层可以通过高温超快熔融结晶退火工艺形成。混合硅 - 锗的熔融结晶过程提供了活性掺杂剂浓度，其减小了在多晶混合硅 - 锗（SiGe）层和栅极电介质的界面处形成的耗尽区的宽度。

45. 发明申请

US20080248626A1 SHALLOW TRENCH ISOLATION SELF-ALIGNED TO TEMPLATED RECRYSTALLIZATION BOUNDARY 审中-公开
标题翻译： SHOWOW TRENCH ISOLATION自对准至模拟重构边界
公开(公告)号：US20080248626A1
公开(公告)日：2008-10-09
申请号：US11697102
申请日：2007-04-05
申请人： Yaocheng Liu , Zhijiong Luo , Katherine L. Saenger , Chun-Yung Sung , Rajasekhar Venigalla , Haizhou Yin
发明人： Yaocheng Liu , Zhijiong Luo , Katherine L. Saenger , Chun-Yung Sung , Rajasekhar Venigalla , Haizhou Yin
IPC分类号： H01L21/762
CPC分类号： H01L21/26506 , H01L21/02667 , H01L21/187 , H01L21/76224
摘要： A hybrid orientation direct-semiconductor-bond (DSB) substrate with shallow trench isolation (STI) that is self-aligned to recrystallization boundaries is formed by patterning a hard mask layer for STI, a first amorphization implantation into openings in the hard mask layer, lithographic patterning of portions of a top semiconductor layer, a second amorphization implantation into exposed portions of the DSB substrate, recrystallization of the portions of the top semiconductor layer, and formation of STI utilizing the pattern in the hard mask layer. The edges of patterned photoresist for the second amorphization implantation are located within the openings in the patterned hard mask layer. Defective boundary regions formed underneath the openings in the hard mask layer are removed during the formation of STI to provide a leakage path free substrate. Due to elimination of a requirement for increased STI width, device density is increased compared to non-self-aligning process integration schemes.
摘要翻译：通过将STI的硬掩模层图案化，在硬掩模层的开口中进行第一非晶化注入，形成具有与重结晶边界自对准的浅沟槽隔离（STI）的混合取向直接半导体结合（DSB）顶部半导体层的部分的平版印刷图案化，第二非晶化注入到DSB衬底的暴露部分中，顶部半导体层的部分的再结晶，以及利用硬掩模层中的图案形成STI。用于第二非晶化注入的图案化光致抗蚀剂的边缘位于图案化的硬掩模层的开口内。在形成STI期间去除在硬掩模层中形成在开口下面的有缺陷的边界区域，以提供无泄漏路径的衬底。由于消除了对于增加的STI宽度的要求，与非自对准工艺集成方案相比，器件密度增加。

46. 发明申请

US20080185636A1 SEMICONDUCTOR STRUCTURE INCLUDING DOPED SILICON CARBON LINER LAYER AND METHOD FOR FABRICATION THEREOF 有权
标题翻译：包括掺杂硅碳板层的半导体结构及其制造方法
公开(公告)号：US20080185636A1
公开(公告)日：2008-08-07
申请号：US11672109
申请日：2007-02-07
申请人： Zhijiong Luo , Yaocheng Liu
发明人： Zhijiong Luo , Yaocheng Liu
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66545 , H01L29/1083 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： A semiconductor structure and related method for fabrication thereof includes a liner layer interposed between: (1) a pedestal shaped channel region within a semiconductor substrate; and (2) a source region and a drain region within a semiconductor material layer located upon the liner layer and further laterally separated from the pedestal shaped channel region within the semiconductor substrate. The liner layer comprises an active doped silicon carbon material. The semiconductor material layer may comprises a semiconductor material other than a silicon carbon semiconductor material. The semiconductor material layer may alternatively comprise a silicon carbon semiconductor material having an opposite dopant polarity and lower carbon content in comparison with the liner layer. Due to presence of the silicon carbon material, the liner layer inhibits dopant diffusion therefrom into the pedestal shaped channel region. Electrical performance of a field effect device that uses the pedestal shaped channel region is thus enhanced.
摘要翻译：半导体结构及其相关制造方法包括：衬垫层，介于：（1）半导体衬底内的基座形沟道区; 以及（2）位于衬里层上的半导体材料层内的源极区域和漏极区域，并且与半导体衬底内的基座形状沟道区域进一步横向分离。衬里层包括有源掺杂硅碳材料。半导体材料层可以包括除了硅碳半导体材料之外的半导体材料。可选地，半导体材料层可以包含与衬里层相比具有相反掺杂剂极性和较低碳含量的硅碳半导体材料。由于存在硅碳材料，衬垫层阻止掺杂剂从其中扩散到基座形沟道区域中。因此，增强了使用基座形状的通道区域的场效应装置的电气性能。

47. 发明申请

US20070238276A1 Control of poly-Si depletion in CMOS via gas phase doping 失效
标题翻译：通过气相掺杂控制CMOS中的多晶硅耗尽
公开(公告)号：US20070238276A1
公开(公告)日：2007-10-11
申请号：US11402177
申请日：2006-04-11
申请人： Yaocheng Liu , Alexander Reznicek , Devendra Sadana
发明人： Yaocheng Liu , Alexander Reznicek , Devendra Sadana
IPC分类号： H01L21/4763
CPC分类号： H01L21/823842 , H01L21/28035 , H01L21/32155 , H01L29/4916
摘要： A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.
摘要翻译：提供了一种利用气相掺杂工艺在CMOS结构中控制多晶硅耗尽效应的方法，该方法能够在栅极电介质/多晶硅界面处提供高浓度的掺杂剂原子。本发明还提供了使用本文所述的气相掺杂技术制造的包括例如nFET和/或pFET的CMOS结构。

48. 发明授权

US07279758B1 N-channel MOSFETs comprising dual stressors, and methods for forming the same 有权
标题翻译：包含双重应力的N沟道MOSFET及其形成方法
公开(公告)号：US07279758B1
公开(公告)日：2007-10-09
申请号：US11420047
申请日：2006-05-24
申请人： Jinghong H. Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
发明人： Jinghong H. Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/324 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S257/90
摘要： The present invention relates to a semiconductor device including at least one n-channel field effect transistor (n-FET). Specifically, the n-FET includes first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.
摘要翻译：本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。具体地说，n-FET包括均包含碳取代和拉伸应力单晶半导体的第一和第二图案应力层。第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

49. 发明授权

US06835488B2 Fuel cell with patterned electrolyte/electrode interface 失效
标题翻译：具有图案电解质/电极界面的燃料电池
公开(公告)号：US06835488B2
公开(公告)日：2004-12-28
申请号：US09850411
申请日：2001-05-08
申请人： Jun Sasahara , Suk Won Cha , Amy Chang-Chien , Tadahiro Kubota , Nariaki Kuriyama , Sang-Joon J. Lee , Yaocheng Liu , Ryan O'Hayre , Friedrich B. Prinz , Yuji Saito
发明人： Jun Sasahara , Suk Won Cha , Amy Chang-Chien , Tadahiro Kubota , Nariaki Kuriyama , Sang-Joon J. Lee , Yaocheng Liu , Ryan O'Hayre , Friedrich B. Prinz , Yuji Saito
IPC分类号： H01M214
CPC分类号： H01M4/86 , H01M4/0485 , H01M8/0254 , H01M8/0289 , H01M8/1007 , H01M2008/1293
摘要： A fuel cell contains an electrolyte sheet sandwiched between two electrodes. One or both electrode/electrolyte interfaces includes mesoscopic three-dimensional features in a prescribed pattern. The features increase the surface area-to-volume ratio of the device and can be used as integral channels for directing the flow of reactant gases to the reaction surface area, eliminating the need for channels in sealing plates surrounding the electrodes. The electrolyte can be made by micromachining techniques that allow very precise feature definition. Both selective removal and mold-filling techniques can be used. The fuel cell provides significantly enhanced volumetric power density when compared with conventional fuel cells.
摘要翻译：燃料电池包含夹在两个电极之间的电解质片。一个或两个电极/电解质界面包括规定图案的介观三维特征。这些特征增加了装置的表面积 - 体积比，并且可以用作用于将反应物气体流引导到反应表面区域的整体通道，从而不需要围绕电极的密封板中的通道。电解质可以通过允许非常精确的特征定义的微加工技术制成。可以使用选择性去除和模具填充技术。与常规燃料电池相比，燃料电池提供显着提高的体积功率密度。

50. 发明授权

US07696000B2 Low defect Si:C layer with retrograde carbon profile 有权
标题翻译：低缺陷Si：C层具有逆行碳分布
公开(公告)号：US07696000B2
公开(公告)日：2010-04-13
申请号：US11565793
申请日：2006-12-01
申请人： Yaocheng Liu , Subramanian S. Iyer , Jinghong Li
发明人： Yaocheng Liu , Subramanian S. Iyer , Jinghong Li
IPC分类号： H01L21/00
CPC分类号： H01L29/1054 , H01L21/2022 , H01L21/26506 , H01L29/32 , H01L29/7848 , H01L29/78618 , H01L29/78654 , H01L29/78696
摘要： Formation of carbon-substituted single crystal silicon layer is prone to generation of large number of defects especially at high carbon concentration. The present invention provides structures and methods for providing low defect carbon-substituted single crystal silicon layer even for high concentration of carbon in the silicon. According to the present invention, the active retrograde profile in the carbon implantation reduces the defect density in the carbon-substituted single crystal silicon layer obtained after a solid phase epitaxy. This enables the formation of semiconductor structures with compressive stress and low defect density. When applied to semiconductor transistors, the present invention enables N-type field effect transistors with enhanced electron mobility through the tensile stress that is present into the channel.
摘要翻译：碳取代的单晶硅层的形成容易产生大量的缺陷，特别是在高碳浓度下。本发明提供即使对于硅中的高浓度碳来提供低缺陷碳取代的单晶硅层的结构和方法。根据本发明，碳注入中的主动逆行曲线减少了在固相外延后获得的碳取代单晶硅层中的缺陷密度。这使得能够形成具有压缩应力和低缺陷密度的半导体结构。当应用于半导体晶体管时，本发明能够通过存在于沟道中的拉伸应力使具有增强的电子迁移率的N型场效应晶体管成为可能。

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