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1. 发明授权

US07696000B2 Low defect Si:C layer with retrograde carbon profile 有权
标题翻译：低缺陷Si：C层具有逆行碳分布
公开(公告)号：US07696000B2
公开(公告)日：2010-04-13
申请号：US11565793
申请日：2006-12-01
申请人： Yaocheng Liu , Subramanian S. Iyer , Jinghong Li
发明人： Yaocheng Liu , Subramanian S. Iyer , Jinghong Li
IPC分类号： H01L21/00
CPC分类号： H01L29/1054 , H01L21/2022 , H01L21/26506 , H01L29/32 , H01L29/7848 , H01L29/78618 , H01L29/78654 , H01L29/78696
摘要： Formation of carbon-substituted single crystal silicon layer is prone to generation of large number of defects especially at high carbon concentration. The present invention provides structures and methods for providing low defect carbon-substituted single crystal silicon layer even for high concentration of carbon in the silicon. According to the present invention, the active retrograde profile in the carbon implantation reduces the defect density in the carbon-substituted single crystal silicon layer obtained after a solid phase epitaxy. This enables the formation of semiconductor structures with compressive stress and low defect density. When applied to semiconductor transistors, the present invention enables N-type field effect transistors with enhanced electron mobility through the tensile stress that is present into the channel.
摘要翻译：碳取代的单晶硅层的形成容易产生大量的缺陷，特别是在高碳浓度下。本发明提供即使对于硅中的高浓度碳来提供低缺陷碳取代的单晶硅层的结构和方法。根据本发明，碳注入中的主动逆行曲线减少了在固相外延后获得的碳取代单晶硅层中的缺陷密度。这使得能够形成具有压缩应力和低缺陷密度的半导体结构。当应用于半导体晶体管时，本发明能够通过存在于沟道中的拉伸应力使具有增强的电子迁移率的N型场效应晶体管成为可能。

2. 发明申请

US20080128806A1 LOW DEFECT SI:C LAYER WITH RETROGRADE CARBON PROFILE 有权
标题翻译：低缺陷SI：C层，带有RETROGRADE碳配置文件
公开(公告)号：US20080128806A1
公开(公告)日：2008-06-05
申请号：US11565793
申请日：2006-12-01
申请人： Yaocheng Liu , Subramanian S. Iyer , Jinghong Li
发明人： Yaocheng Liu , Subramanian S. Iyer , Jinghong Li
IPC分类号： H01L29/06 , H01L21/336 , H01L21/225 , H01L29/08
CPC分类号： H01L29/1054 , H01L21/2022 , H01L21/26506 , H01L29/32 , H01L29/7848 , H01L29/78618 , H01L29/78654 , H01L29/78696
摘要： Formation of carbon-substituted single crystal silicon layer is prone to generation of large number of defects especially at high carbon concentration. The present invention provides structures and methods for providing low defect carbon-substituted single crystal silicon layer even for high concentration of carbon in the silicon. According to the present invention, the active retrograde profile in the carbon implantation reduces the defect density in the carbon-substituted single crystal silicon layer obtained after a solid phase epitaxy. This enables the formation of semiconductor structures with compressive stress and low defect density. When applied to semiconductor transistors, the present invention enables N-type field effect transistors with enhanced electron mobility through the tensile stress that is present into the channel.
摘要翻译：碳取代的单晶硅层的形成容易产生大量的缺陷，特别是在高碳浓度下。本发明提供即使对于硅中的高浓度碳来提供低缺陷碳取代的单晶硅层的结构和方法。根据本发明，碳注入中的主动逆行曲线减少了在固相外延后获得的碳取代单晶硅层中的缺陷密度。这使得能够形成具有压缩应力和低缺陷密度的半导体结构。当应用于半导体晶体管时，本发明能够通过存在于沟道中的拉伸应力使具有增强的电子迁移率的N型场效应晶体管成为可能。

3. 发明申请

US20070281413A1 N-CHANNEL MOSFETS COMPRISING DUAL STRESSORS, AND METHODS FOR FORMING THE SAME 有权
标题翻译：包含双重压力机的N沟道MOSFET及其形成方法
公开(公告)号：US20070281413A1
公开(公告)日：2007-12-06
申请号：US11840795
申请日：2007-08-17
申请人： Jinghong Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
发明人： Jinghong Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/324 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S257/90
摘要： The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.
摘要翻译：本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。具体地说，n-FET包括第一和第二图案应力层，它们都包含碳取代和拉伸应力单晶半导体。第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

4. 发明授权

US07888197B2 Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer 有权
标题翻译：使用牺牲应力层形成具有掺杂玻璃盒层的应力SOI FET的方法
公开(公告)号：US07888197B2
公开(公告)日：2011-02-15
申请号：US11622056
申请日：2007-01-11
申请人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
发明人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
IPC分类号： H01L21/8238
CPC分类号： H01L29/78696 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/7849
摘要： A method is provided for fabricating a semiconductor-on-insulator (“SOI”) substrate. In such method an SOI substrate is formed to include (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (iii) a buried oxide (“BOX”) layer including a layer of doped silicate glass. A sacrificial stressed layer is deposited onto the SOI substrate to overlie the SOI layer. Trenches are then etched through the sacrificial stressed layer and into the SOI layer. The SOI substrate is heated with the sacrificial stressed layer sufficiently to cause the glass layer to soften and the sacrificial stressed layer to relax, to thereby apply a stress to the SOI layer to form a stressed SOI layer. The trenches in the stressed SOI layer are then filled with a dielectric material to form trench isolation regions contacting peripheral edges of the stressed SOI layer, the trench isolation regions extending downwardly from a major surface of the stressed SOI layer towards the BOX layer. The sacrificial stressed layer is then removed to expose the stressed SOI layer. Field effect transistors can then be formed in the stressed SOI layer.
摘要翻译：提供了一种用于制造绝缘体上半导体（“SOI”）衬底的方法。在这种方法中，形成SOI衬底，其包括（i）通过（iii）包含掺杂硅酸盐玻璃层的掩埋氧化物（“BOX”）层从（ii）体半导体层分离的单晶硅的SOI层。牺牲应力层沉积在SOI衬底上以覆盖SOI层。然后将沟槽蚀刻穿过牺牲应力层并进入SOI层。用牺牲应力层将SOI衬底充分加热，使玻璃层软化，牺牲应力层松弛，从而向SOI层施加应力以形成受应力的SOI层。然后用电介质材料填充受应力的SOI层中的沟槽，以形成接触应力SOI层的外围边缘的沟槽隔离区，沟槽隔离区域从受应力的SOI层的主表面向BOX层向下延伸。然后去除牺牲应力层以暴露受应力的SOI层。然后可以在受应力的SOI层中形成场效应晶体管。

5. 发明授权

US07838932B2 Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon 有权
标题翻译：用嵌入式硅碳纳米管技术，提高了STIFET结构和超级马赛克纳米管的性能提升
公开(公告)号：US07838932B2
公开(公告)日：2010-11-23
申请号：US12028191
申请日：2008-02-08
申请人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
发明人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
IPC分类号： H01L29/76257
CPC分类号： H01L21/823864 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.
摘要翻译：通过过度填充由晶体管栅极结构形成的间隙或沟槽，实现了通过向NFET的沟道区域施加张力来有效地增加电子迁移率的具有超过1％的取代碳含量的嵌入式硅碳（Si：C）用Si：C，并在超级马赛克法中抛光将Si：C蚀刻到升高的栅极结构的表面或之下，即使在晶体管源极和漏极之上的选定区域中仅保留Si：C，即使能够沉积具有足够高的替代碳含量的Si：C固有地是非选择性的。

6. 发明授权

US07655551B2 Control of poly-Si depletion in CMOS via gas phase doping 失效
标题翻译：通过气相掺杂控制CMOS中的多晶硅耗尽
公开(公告)号：US07655551B2
公开(公告)日：2010-02-02
申请号：US12127171
申请日：2008-05-27
申请人： Yaocheng Liu , Alexander Reznicek , Devendra K. Sadana
发明人： Yaocheng Liu , Alexander Reznicek , Devendra K. Sadana
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823842 , H01L21/28035 , H01L21/32155 , H01L29/4916
摘要： A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.
摘要翻译：提供了一种利用气相掺杂工艺在CMOS结构中控制多晶硅耗尽效应的方法，该方法能够在栅极电介质/多晶硅界面处提供高浓度的掺杂剂原子。本发明还提供了包括例如nFET和/或pFET的CMOS结构，其利用本文所述的气相掺杂技术制造。

7. 发明授权

US07598147B2 Method of forming CMOS with Si:C source/drain by laser melting and recrystallization 有权
标题翻译：通过激光熔融和重结晶用Si：C源极/漏极形成CMOS的方法
公开(公告)号：US07598147B2
公开(公告)日：2009-10-06
申请号：US11860127
申请日：2007-09-24
申请人： Yaocheng Liu , Qiqing C. Ouyang , Kathryn T. Schonenberg , Chun-Yung Sung
发明人： Yaocheng Liu , Qiqing C. Ouyang , Kathryn T. Schonenberg , Chun-Yung Sung
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/268 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/665 , H01L29/66545 , H01L29/7848
摘要： A method of forming crystalline Si:C in source and drain regions is provided. After formation of shallow trench isolation and gate electrodes of field effect transistors, gate spacers are formed on gate electrodes. Preamorphization implantation is performed in the source and drain regions, followed by carbon implantation. The upper portion of the source and drain regions comprises an amorphous mixture of silicon, germanium, and/or carbon. An anti-reflective layer is deposited to enhance the absorption of a laser beam into the silicon substrate. The laser beam is scanned over the silicon substrate including the upper source and drain region with the amorphous mixture. The energy of the laser beam is controlled so that the temperature of the semiconductor substrate is above the melting temperature of the amorphous mixture but below the glass transition temperature of silicon oxide so that structural integrity of the semiconductor structure is preserved.
摘要翻译：提供了在源极和漏极区域中形成晶体Si：C的方法。在形成浅沟槽隔离和场效应晶体管的栅电极之后，在栅电极上形成栅极间隔物。在源极和漏极区域中进行前置放电，随后进行碳注入。源区和漏区的上部包括硅，锗和/或碳的无定形混合物。沉积抗反射层以增强激光束到硅衬底中的吸收。激光束在包括具有无定形混合物的上源极和漏极区域的硅衬底上扫描。控制激光束的能量使得半导体衬底的温度高于无定形混合物的熔融温度但低于氧化硅的玻璃化转变温度，从而保持半导体结构的结构完整性。

8. 发明授权

US07473626B2 Control of poly-Si depletion in CMOS via gas phase doping 失效
标题翻译：通过气相掺杂控制CMOS中的多晶硅耗尽
公开(公告)号：US07473626B2
公开(公告)日：2009-01-06
申请号：US11402177
申请日：2006-04-11
申请人： Yaocheng Liu , Alexander Reznicek , Devendra K. Sadana
发明人： Yaocheng Liu , Alexander Reznicek , Devendra K. Sadana
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823842 , H01L21/28035 , H01L21/32155 , H01L29/4916
摘要： A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.
摘要翻译：提供了一种利用气相掺杂工艺在CMOS结构中控制多晶硅耗尽效应的方法，该方法能够在栅极电介质/多晶硅界面处提供高浓度的掺杂剂原子。本发明还提供了使用本文所述的气相掺杂技术制造的包括例如nFET和/或pFET的CMOS结构。

9. 发明授权

US07473594B2 Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon 失效
标题翻译：用嵌入式硅碳纳米管技术，提高了STIFET结构和超级马赛克纳米管的性能提升
公开(公告)号：US07473594B2
公开(公告)日：2009-01-06
申请号：US11459730
申请日：2006-07-25
申请人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
发明人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.
摘要翻译：通过过度填充由晶体管栅极结构形成的间隙或沟槽，实现了通过向NFET的沟道区施加张力来有效地增加电子迁移率的具有超过1％的取代碳含量的嵌入式硅碳（Si：C）用Si：C，并在超级马赛克法中抛光将Si：C蚀刻到升高的栅极结构的表面或之下，即使在晶体管源极和漏极之上的选定区域中仅保留Si：C，即使能够沉积具有足够高的替代碳含量的Si：C固有地是非选择性的。

10. 发明申请

US20080224218A1 CMOS STRUCTURE INCLUDING DIFFERENTIAL CHANNEL STRESSING LAYER COMPOSITIONS 有权
标题翻译： CMOS结构包括差分通道应力层组成
公开(公告)号：US20080224218A1
公开(公告)日：2008-09-18
申请号：US11685458
申请日：2007-03-13
申请人： Yaocheng Liu , Ricardo A. Donaton , Kern Rim
发明人： Yaocheng Liu , Ricardo A. Donaton , Kern Rim
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/66545 , H01L29/66636
摘要： A CMOS structure includes an n-FET device comprising an n-FET channel region and a p-FET device comprising a p-FET channel region. The n-FET channel region includes a first silicon material layer located upon a silicon-germanium alloy material layer. The p-FET channel includes a second silicon material layer located upon a silicon-germanium-carbon alloy material layer. The silicon-germanium alloy material layer induces a desirable tensile strain within the n-FET channel. The silicon-germanium-carbon alloy material layer suppresses an undesirable tensile strain within the p-FET channel region. A silicon-germanium-carbon alloy material from which is comprised the silicon-germanium-carbon alloy material layer may be formed by selectively incorporating carbon into a silicon-germanium alloy material from which is formed the silicon-germanium alloy material layer.
摘要翻译： CMOS结构包括包括n-FET沟道区的n-FET器件和包括p-FET沟道区的p-FET器件。 n-FET沟道区包括位于硅 - 锗合金材料层上的第一硅材料层。 p-FET沟道包括位于硅 - 锗 - 碳合金材料层上的第二硅材料层。硅 - 锗合金材料层在n-FET通道内引起所需的拉伸应变。硅 - 锗 - 合金材料层抑制了p-FET沟道区内的不希望的拉伸应变。可以通过选择性地将碳包含在形成硅 - 锗合金材料层的硅 - 锗合金材料中来形成由硅 - 锗 - 碳合金材料层构成的硅 - 锗 - 碳合金材料。

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