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41. 发明授权

US07471553B2 Phase change memory device and program method thereof 有权
标题翻译：相变存储器件及其编程方法
公开(公告)号：US07471553B2
公开(公告)日：2008-12-30
申请号：US11319373
申请日：2005-12-29
申请人： Kwang-Jin Lee , Du-Eung Kim , Sang-Beom Kang , Woo-Yeong Cho
发明人： Kwang-Jin Lee , Du-Eung Kim , Sang-Beom Kang , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C5/145 , G11C7/1078 , G11C7/1096 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during a programming interval, and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval. The pump circuit is activated prior to the programming interval in response to an external control signal.
摘要翻译：相变存储器件包括具有相变材料的存储单元，适于在编程间隔期间向存储单元提供编程电流的写入驱动器，以及用于在写入驱动器期间增强写入驱动器的电流供应容量的泵电路编程间隔。泵电路响应于外部控制信号在编程间隔之前被激活。

42. 发明授权

US07570511B2 Semiconductor memory device having a three-dimensional cell array structure 有权
标题翻译：具有三维单元阵列结构的半导体存储器件
公开(公告)号：US07570511B2
公开(公告)日：2009-08-04
申请号：US11755329
申请日：2007-05-30
申请人： Woo-Yeong Cho , Sang-Beom Kang , Du-Eung Kim
发明人： Woo-Yeong Cho , Sang-Beom Kang , Du-Eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C11/1655 , G11C11/1657 , G11C13/0004 , G11C2213/71 , G11C2213/72
摘要： A semiconductor memory device includes a plurality of cell array layers including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction that intersects the first direction, and a plurality of memory cells disposed at intersections of the word lines and the bit lines. Each of the word lines has a word line position, each of the bit lines has a bit line position, and each of the memory cells includes a variable resistance device in series with a diode. The cell array layers are arranged in layers in a third direction that is perpendicular to the first and second directions. The bit lines of each of the cell array layers having a same bit line position are connected to a common column selector transistor, or the word lines of the cell array layers having a same word line position are connected to a common word line driver.
摘要翻译：半导体存储器件包括多个单元阵列层，包括沿第一方向延伸的多个字线，沿与第一方向相交的第二方向延伸的多个位线，以及设置在第一方向的交点处的多个存储单元字线和位线。每个字线具有字线位置，每个位线具有位线位置，并且每个存储单元包括与二极管串联的可变电阻器件。单元阵列层在垂直于第一和第二方向的第三方向上排列成层。具有相同位线位置的每个单元阵列层的位线连接到公共列选择晶体管，或者具有相同字线位置的单元阵列层的字线连接到公共字线驱动器。

43. 发明申请

US20070064473A1 Phase change memory device and program method thereof 有权
标题翻译：相变存储器件及其编程方法
公开(公告)号：US20070064473A1
公开(公告)日：2007-03-22
申请号：US11319373
申请日：2005-12-29
申请人： Kwang-Jin Lee , Du-Eung Kim , Sang-Beom Kang , Woo-Yeong Cho
发明人： Kwang-Jin Lee , Du-Eung Kim , Sang-Beom Kang , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C5/145 , G11C7/1078 , G11C7/1096 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during a programming interval, and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval. The pump circuit is activated prior to the programming interval in response to an external control signal.
摘要翻译：相变存储器件包括具有相变材料的存储单元，适于在编程间隔期间向存储单元提供编程电流的写入驱动器，以及用于在写入驱动器期间增强写入驱动器的电流供应容量的泵电路编程间隔。泵电路响应于外部控制信号在编程间隔之前被激活。

44. 发明申请

US20050007843A1 Redundancy circuit in semiconductor memory device having a multiblock structure 有权
标题翻译：具有多块结构的半导体存储器件中的冗余电路
公开(公告)号：US20050007843A1
公开(公告)日：2005-01-13
申请号：US10889194
申请日：2004-07-12
申请人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak
发明人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/812 , G11C29/806
摘要： A redundancy circuit in a semiconductor memory device having a multiblock structure in which a memory cell array is classified into a plurality of memory cell blocks, an integrated redundancy circuit having a plurality of fuse boxes for storing, per block, addresses of defective memory cells provided in the plurality of memory cell blocks, the plurality of fuse boxes being connected to the common precharge unit and being selectively activated in response to a block distinction selection signal.
摘要翻译：一种具有多块结构的半结构存储器件中的冗余电路，其中存储单元阵列被分为多个存储单元块，集成冗余电路具有多个保险丝盒，用于存储每块所提供的不良存储器单元的地址在所述多个存储单元块中，所述多个保险丝盒连接到所述公共预充电单元，并且响应于块区别选择信号被选择性地激活。

45. 发明授权

US06456547B1 Semiconductor memory device with function of repairing stand-by current failure 有权
标题翻译：具有修复备用电流故障功能的半导体存储器件
公开(公告)号：US06456547B1
公开(公告)日：2002-09-24
申请号：US09689098
申请日：2000-10-12
申请人： Hyun-Sun Mo , Du-Eung Kim , Choong-Keun Kwak
发明人： Hyun-Sun Mo , Du-Eung Kim , Choong-Keun Kwak
IPC分类号： G11C700
CPC分类号： G11C29/83 , G11C7/12
摘要： A semiconductor memory device having memory cells connected with pairs of bit lines and word lines comprises a pre-charging part for pre-charging a pair of bit lines in response to a first state control signal at a stand-by mode of the semiconductor memory device; a bit line charging control part for generating a second state control signal to the pre-charging part when a stand-by current failure occurs due to defect in the pair of bit lines, wherein the second state control signal is independent of a pre-charge relating signal externally applied and the pre-charging part cuts-off a supply voltage from being applied to the pair of bit lines with defect; and a bit line floating prevent part for compensatively fixing potential values of the pair of bit lines with defect so that a cell supply voltage is prevented from being applied to the pair of bit lines with defect at a memory access mode of the semiconductor memory device, so that a hard type defect like a stand-by current failure can be repaired regardless of a logic state of a pre-charge control signal, thereby reducing the probability of occurrence of defect in a semiconductor memory device.
摘要翻译：具有与位线对和字线对连接的存储单元的半导体存储器件包括预充电部分，用于响应于半导体存储器件的待机模式下的第一状态控制信号对一对位线进行预充电 ; 位线充电控制部分，用于当由于一对位线中的缺陷而发生待机电流故障时，向预充电部分产生第二状态控制信号，其中第二状态控制信号独立于预充电相关信号外部施加，并且预充电部分切断电源电压而不被施加到一对位线; 以及位线浮动防止部件，用于以缺陷补偿地固定一对位线的电位值，使得防止单元电源电压被施加到半导体存储器件的存储器访问模式下的缺陷的位线对，使得像预备电流故障那样的硬型缺陷可以被修复，而不管预充电控制信号的逻辑状态如何，从而降低了半导体存储器件中的缺陷的发生概率。

46. 发明授权

US5959907A Semiconductor memory device having a redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器件
公开(公告)号：US5959907A
公开(公告)日：1999-09-28
申请号：US28150
申请日：1998-02-23
申请人： Du-Eung Kim , Choong-Keun Kwak
发明人： Du-Eung Kim , Choong-Keun Kwak
IPC分类号： G11C29/04 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C11/418 , G11C29/785 , G11C29/83
摘要： A redundancy circuit for a semiconductor device comprises a circuit having variable impedance changed in accordance with a chip selecting signal. The variable impedance circuit has a low impedance when the chip selecting signal is at a low level and a high impedance when the chip selecting signal is at a high level. Therefore, when the device is in a standby state, no static current flows, and when the chip is in an active state current of less than several micro amperes flows. Thus, the power dissipation of the redundancy circuit can be reduced.
摘要翻译：用于半导体器件的冗余电路包括根据芯片选择信号而改变可变阻抗的电路。当芯片选择信号处于低电平时，可变阻抗电路具有低阻抗，并且当芯片选择信号处于高电平时具有高阻抗。因此，当器件处于待机状态时，不会流动静电流，并且当芯片处于活动状态时，电流小于几微安流动。因此，可以减少冗余电路的功率消耗。

47. 发明授权

US07075848B2 Redundancy circuit in semiconductor memory device having a multiblock structure 有权
标题翻译：具有多块结构的半导体存储器件中的冗余电路
公开(公告)号：US07075848B2
公开(公告)日：2006-07-11
申请号：US10889194
申请日：2004-07-12
申请人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak
发明人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak
IPC分类号： G11C17/18
CPC分类号： G11C29/812 , G11C29/806
摘要： A redundancy circuit in a semiconductor memory device having a multiblock structure in which a memory cell array is classified into a plurality of memory cell blocks, an integrated redundancy circuit having a plurality of fuse boxes for storing, per block, addresses of defective memory cells provided in the plurality of memory cell blocks, the plurality of fuse boxes being connected to the common precharge unit and being selectively activated in response to a block distinction selection signal.
摘要翻译：一种具有多块结构的半结构存储器件中的冗余电路，其中存储单元阵列被分为多个存储单元块，集成冗余电路具有多个保险丝盒，用于存储每块所提供的不良存储器单元的地址在所述多个存储单元块中，所述多个保险丝盒连接到所述公共预充电单元，并且响应于块区别选择信号被选择性地激活。

48. 发明申请

US20060120148A1 Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell 有权
标题翻译：具有堆叠存储单元的半导体存储器件和制造堆叠存储单元的方法
公开(公告)号：US20060120148A1
公开(公告)日：2006-06-08
申请号：US11238381
申请日：2005-09-29
申请人： Sung-Min Kim , Eun-Jung Yun , Jong-Soo Seo , Du-Eung Kim , Beak-Hyung Cho , Byung-Seo Kim
发明人： Sung-Min Kim , Eun-Jung Yun , Jong-Soo Seo , Du-Eung Kim , Beak-Hyung Cho , Byung-Seo Kim
IPC分类号： G11C11/00
CPC分类号： H01L27/2436 , G11C13/0004 , G11C13/003 , G11C2213/74 , G11C2213/79
摘要： In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the phase-change memory cells of each of the phase-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the phase-change memory cells.
摘要翻译：在半导体存储器件和方法中，提供了相变存储单元，每个都包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。在一个示例中，控制晶体管的数量是两个。半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个相变存储单元组。每个相变存储单元组的每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。因此，可以增加半导体存储器件的集成密度和流过每个相变存储单元的电流量。

49. 发明授权

US07005748B2 Flip chip interface circuit of a semiconductor memory device 失效
标题翻译：半导体存储器件的倒装芯片接口电路
公开(公告)号：US07005748B2
公开(公告)日：2006-02-28
申请号：US10435024
申请日：2003-05-12
申请人： Du-Eung Kim , Beak-Hyung Cho
发明人： Du-Eung Kim , Beak-Hyung Cho
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L25/0657 , H01L23/49575 , H01L2224/48091 , H01L2225/06527 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A flip chip interface circuit for combining two identical semiconductor chips on upper and lower surfaces of an assembling lead frame into one flip chip package includes at least first and second address pads and first and second bonding option pads formed symmetrically on the chips in a mirror type arrangement to each other. The first and second address pads are input with a signal for selecting operations of the first and second semiconductor chips. The first and second input pad selection and chip selection signals are output in response to signals from the first and second address pads and first and second bonding option pads of the chips, the first and second semiconductor chip selection signals are output in response to the first and second input pad and chip selection signals, and an interface enable signal is output in response to the first and second semiconductor chip selection signals.
摘要翻译：一种用于将组装引线框架的上表面和下表面上的两个相同的半导体芯片组合成一个倒装芯片封装的倒装芯片接口电路包括至少第一和第二寻址焊盘以及以镜型对称地形成在芯片上的第一和第二焊接选择焊盘相互安排第一和第二地址焊盘输入用于选择第一和第二半导体芯片的操作的信号。响应于来自第一和第二地址焊盘以及芯片的第一和第二焊接选择焊盘的信号而输出第一和第二输入焊盘选择和芯片选择信号，第一和第二半导体芯片选择信号响应于第一和第二输入焊盘和芯片选择信号，并且响应于第一和第二半导体芯片选择信号而输出接口使能信号。

50. 发明授权

US06288926B1 Static semiconductor memory device and fabricating method thereof 有权
标题翻译：静态半导体存储器件及其制造方法
公开(公告)号：US06288926B1
公开(公告)日：2001-09-11
申请号：US09535871
申请日：2000-03-27
申请人： Du-Eung Kim , Byung-Gil Choi , Sang-Jib Han , Choong-Keun Kwak , Soon-Moon Jung , Sung-Bong Kim
发明人： Du-Eung Kim , Byung-Gil Choi , Sang-Jib Han , Choong-Keun Kwak , Soon-Moon Jung , Sung-Bong Kim
IPC分类号： G11C506
CPC分类号： G11C5/063 , G11C11/412
摘要： A semiconductor memory device is disclosed. The device is comprised of a plurality of word lines; a plurality of bit lines arranged in perpendicular to the word lines. In addition, a plurality of supply voltage lines extend in the same direction as the bit lines. Also, a plurality of first ground voltage lines are arranged in the same direction as the bit lines. Further, a plurality of second ground voltage lines are arranged in the same direction as the word lines. A plurality of memory cells are each connected between one of the word lines and one of the bit lines. Here, the ground voltage lines are arranged in a matrix shape to reduce the resistance of the ground voltage line and secure the margin between the supply voltage level and the ground voltage level of the data latched by the memory cells to thereby prevent an operational failure of the device.
摘要翻译：公开了一种半导体存储器件。该装置由多条字线组成; 垂直于字线布置的多个位线。此外，多个电源电压线沿与位线相同的方向延伸。此外，多个第一接地电压线被布置在与位线相同的方向上。此外，多个第二接地电压线布置在与字线相同的方向上。多个存储单元分别连接在一条字线和一条位线之间。这里，接地电压线被布置成矩阵形状以减小接地电压线的电阻并且确保由存储器单元锁存的数据的电源电压电平和接地电压电平之间的裕度，从而防止装置。

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