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1. 发明授权

US07110286B2 Phase-change memory device and method of writing a phase-change memory device 有权
公开(公告)号：US07110286B2
公开(公告)日：2006-09-19
申请号：US10919371
申请日：2004-08-17
申请人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0023 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

2. 发明申请

US20050007843A1 Redundancy circuit in semiconductor memory device having a multiblock structure 有权
标题翻译：具有多块结构的半导体存储器件中的冗余电路
公开(公告)号：US20050007843A1
公开(公告)日：2005-01-13
申请号：US10889194
申请日：2004-07-12
申请人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak
发明人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/812 , G11C29/806
摘要： A redundancy circuit in a semiconductor memory device having a multiblock structure in which a memory cell array is classified into a plurality of memory cell blocks, an integrated redundancy circuit having a plurality of fuse boxes for storing, per block, addresses of defective memory cells provided in the plurality of memory cell blocks, the plurality of fuse boxes being connected to the common precharge unit and being selectively activated in response to a block distinction selection signal.
摘要翻译：一种具有多块结构的半结构存储器件中的冗余电路，其中存储单元阵列被分为多个存储单元块，集成冗余电路具有多个保险丝盒，用于存储每块所提供的不良存储器单元的地址在所述多个存储单元块中，所述多个保险丝盒连接到所述公共预充电单元，并且响应于块区别选择信号被选择性地激活。

3. 发明授权

US07463511B2 Phase change memory device using multiprogramming method 有权
标题翻译：相变存储器件采用多重编程方式
公开(公告)号：US07463511B2
公开(公告)日：2008-12-09
申请号：US11723361
申请日：2007-03-19
申请人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Woo-Yeong Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/72
摘要： A phase change memory device includes a memory cell array and a write driver circuit, and a column selection circuit. The memory cell array includes a plurality of block units each connected between a corresponding pair of word line drivers. The write driver circuit includes a plurality of write driver units each comprising a plurality of write drivers adapted to provide respective programming currents to a corresponding block unit among the plurality of block units. The column selection circuit is connected between the memory cell array and the write driver circuit and is adapted to select at least one of the plurality of memory blocks in response to a column selection signal to provide corresponding programming currents to the at least one of the plurality of memory blocks.
摘要翻译：相变存储器件包括存储单元阵列和写入驱动器电路以及列选择电路。存储单元阵列包括多个块单元，每个块单元连接在相应的一对字线驱动器之间。写驱动器电路包括多个写驱动器单元，每个写驱动器单元包括多个写驱动器，其适于向多个块单元中的相应块单元提供相应的编程电流。列选择电路连接在存储单元阵列和写驱动器电路之间，并且适于响应于列选择信号选择多个存储器块中的至少一个，以向多个存储单元阵列中的至少一个提供对应的编程电流的内存块。

4. 发明申请

US20070242503A1 Phase change memory device using multiprogramming method 有权
标题翻译：相变存储器件采用多重编程方式
公开(公告)号：US20070242503A1
公开(公告)日：2007-10-18
申请号：US11723361
申请日：2007-03-19
申请人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Woo-Yeong Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/72
摘要： A phase change memory device comprises a memory cell array and a write driver circuit, and a column selection circuit. The memory cell array comprises a plurality of block units each connected between a corresponding pair of word line drivers. The write driver circuit comprises a plurality of write driver units each comprising a plurality of write drivers adapted to provide respective programming currents to a corresponding block unit among the plurality of block units. The column selection circuit is connected between the memory cell array and the write driver circuit and is adapted to select at least one of the plurality of memory blocks in response to a column selection signal to provide corresponding programming currents to the at least one of the plurality of memory blocks.
摘要翻译：相变存储器件包括存储单元阵列和写入驱动器电路以及列选择电路。存储单元阵列包括多个块单元，每个块单元连接在对应的一对字线驱动器之间。写驱动器电路包括多个写驱动器单元，每个写驱动器单元包括多个写驱动器，其适于向多个块单元中的相应块单元提供相应的编程电流。列选择电路连接在存储单元阵列和写驱动器电路之间，并且适于响应于列选择信号选择多个存储器块中的至少一个，以向多个存储单元阵列中的至少一个提供对应的编程电流的内存块。

5. 发明申请

US20060274574A1 Phase-change memory device and method of writing a phase-change memory device 有权
公开(公告)号：US20060274574A1
公开(公告)日：2006-12-07
申请号：US11502563
申请日：2006-08-11
申请人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C2013/0078 , G11C2013/0092
摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

6. 发明授权

US07075848B2 Redundancy circuit in semiconductor memory device having a multiblock structure 有权
标题翻译：具有多块结构的半导体存储器件中的冗余电路
公开(公告)号：US07075848B2
公开(公告)日：2006-07-11
申请号：US10889194
申请日：2004-07-12
申请人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak
发明人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak
IPC分类号： G11C17/18
CPC分类号： G11C29/812 , G11C29/806
摘要： A redundancy circuit in a semiconductor memory device having a multiblock structure in which a memory cell array is classified into a plurality of memory cell blocks, an integrated redundancy circuit having a plurality of fuse boxes for storing, per block, addresses of defective memory cells provided in the plurality of memory cell blocks, the plurality of fuse boxes being connected to the common precharge unit and being selectively activated in response to a block distinction selection signal.
摘要翻译：一种具有多块结构的半结构存储器件中的冗余电路，其中存储单元阵列被分为多个存储单元块，集成冗余电路具有多个保险丝盒，用于存储每块所提供的不良存储器单元的地址在所述多个存储单元块中，所述多个保险丝盒连接到所述公共预充电单元，并且响应于块区别选择信号被选择性地激活。

7. 发明申请

US20050195633A1 Method for programming phase-change memory array to set state and circuit of a phase-change memory device 有权
标题翻译：用于编程相变存储器阵列以设置相变存储器件的状态和电路的方法
公开(公告)号：US20050195633A1
公开(公告)日：2005-09-08
申请号：US11070196
申请日：2005-03-03
申请人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak , Beak-Hyung Cho
发明人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak , Beak-Hyung Cho
IPC分类号： G11C13/02 , G11C13/00 , G11C16/02 , G11C16/10 , G11C19/08 , H01L27/10 , H01L27/105 , H01L27/115
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0088 , G11C2013/0092
摘要： A method for programming a phase-change memory array and circuit of a phase-change memory device, each having a plurality of phase-change memory cells, may enable all the phase-change memory cells therein to be changed or set at a set resistance state, and may reduce the time needed to change the phase-change memory array to the set resistance state. In the method, a set current pulse having first through nth stages may be applied to the cells of the array to change the cells to the set resistance state. A minimum current level of the set current pulse applied to the phase-change memory cells in any stage may be higher than a reference current level for the cells of the array. A given current level of the set current pulse may be sequentially reduced from stage to stage.
摘要翻译：一种用于编程相变存储器阵列和相变存储器件的电路的方法，每个相变存储器件具有多个相变存储器单元，可以使其中的所有相变存储器单元能够被改变或设置为设定电阻状态，并且可以减少将相变存储器阵列改变为设定电阻状态所需的时间。在该方法中，可以将具有第一至第n个阶段的设定电流脉冲施加到阵列的单元以将单元改变为设定电阻状态。施加到任何阶段中的相变存储器单元的设定电流脉冲的最小电流电平可以高于阵列的单元的参考电流电平。设定电流脉冲的给定电流电平可以从一个阶段顺序地减少。

8. 发明授权

US07502251B2 Phase-change memory device and method of writing a phase-change memory device 有权
标题翻译：相变存储器件以及相变存储器件的写入方法
公开(公告)号：US07502251B2
公开(公告)日：2009-03-10
申请号：US11502563
申请日：2006-08-11
申请人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C2013/0078 , G11C2013/0092
摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.
摘要翻译：相变单元存储器件包括多个相变存储器单元，地址电路，写入驱动器和写入驱动器控制电路。相变存储单元各自包括可在非晶态和晶态之间编程的材料体积。地址电路选择存储单元中的至少一个，并且写入驱动器产生复位脉冲电流以将由地址电路选择的存储单元编程为非晶状态，以及设置脉冲电流以对由地址选择的存储单元进行编程电路进入结晶状态。写入驱动器控制电路根据写入驱动器和由地址电路选择的存储器单元之间的负载来改变至少一个复位和设置的脉冲电流的脉冲宽度和脉冲计数中的至少一个。

9. 发明授权

US07274586B2 Method for programming phase-change memory array to set state and circuit of a phase-change memory device 有权
标题翻译：用于编程相变存储器阵列以设置相变存储器件的状态和电路的方法
公开(公告)号：US07274586B2
公开(公告)日：2007-09-25
申请号：US11070196
申请日：2005-03-03
申请人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak , Beak-Hyung Cho
发明人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak , Beak-Hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0088 , G11C2013/0092
摘要： A method for programming a phase-change memory array and circuit of a phase-change memory device, each having a plurality of phase-change memory cells, may enable all the phase-change memory cells therein to be changed or set at a set resistance state, and may reduce the time needed to change the phase-change memory array to the set resistance state. In the method, a set current pulse having first through nth stages may be applied to the cells of the array to change the cells to the set resistance state. A minimum current level of the set current pulse applied to the phase-change memory cells in any stage may be higher than a reference current level for the cells of the array. A given current level of the set current pulse may be sequentially reduced from stage to stage.
摘要翻译：一种用于编程相变存储器阵列和相变存储器件的电路的方法，每个相变存储器件具有多个相变存储器单元，可以使其中的所有相变存储器单元能够被改变或设置为设定电阻状态，并且可以减少将相变存储器阵列改变为设定电阻状态所需的时间。在该方法中，可以将具有第一至第n个阶段的设定电流脉冲施加到阵列的单元以将单元改变为设定电阻状态。施加到任何阶段中的相变存储器单元的设定电流脉冲的最小电流电平可以高于阵列的单元的参考电流电平。设定电流脉冲的给定电流电平可以从一个阶段顺序地减少。

10. 发明申请

US20050169093A1 Phase-change memory device and method of writing a phase-change memory device 有权
标题翻译：相变存储器件以及相变存储器件的写入方法
公开(公告)号：US20050169093A1
公开(公告)日：2005-08-04
申请号：US10919371
申请日：2004-08-17
申请人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
IPC分类号： G11C13/02 , G11C8/00 , G11C16/02
CPC分类号： G11C13/0004 , G11C13/0023 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.
摘要翻译：相变单元存储器件包括多个相变存储器单元，地址电路，写入驱动器和写入驱动器控制电路。相变存储单元各自包括可在非晶态和晶态之间编程的材料体积。地址电路选择存储单元中的至少一个，并且写入驱动器产生复位脉冲电流以将由地址电路选择的存储单元编程为非晶状态，以及设置脉冲电流以对由地址选择的存储单元进行编程电路进入结晶状态。写入驱动器控制电路根据写入驱动器和由地址电路选择的存储器单元之间的负载来改变复位和设置脉冲电流中的至少一个的脉冲宽度和脉冲计数中的至少一个。

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