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1. 发明授权

US06456547B1 Semiconductor memory device with function of repairing stand-by current failure 有权
标题翻译：具有修复备用电流故障功能的半导体存储器件
公开(公告)号：US06456547B1
公开(公告)日：2002-09-24
申请号：US09689098
申请日：2000-10-12
申请人： Hyun-Sun Mo , Du-Eung Kim , Choong-Keun Kwak
发明人： Hyun-Sun Mo , Du-Eung Kim , Choong-Keun Kwak
IPC分类号： G11C700
CPC分类号： G11C29/83 , G11C7/12
摘要： A semiconductor memory device having memory cells connected with pairs of bit lines and word lines comprises a pre-charging part for pre-charging a pair of bit lines in response to a first state control signal at a stand-by mode of the semiconductor memory device; a bit line charging control part for generating a second state control signal to the pre-charging part when a stand-by current failure occurs due to defect in the pair of bit lines, wherein the second state control signal is independent of a pre-charge relating signal externally applied and the pre-charging part cuts-off a supply voltage from being applied to the pair of bit lines with defect; and a bit line floating prevent part for compensatively fixing potential values of the pair of bit lines with defect so that a cell supply voltage is prevented from being applied to the pair of bit lines with defect at a memory access mode of the semiconductor memory device, so that a hard type defect like a stand-by current failure can be repaired regardless of a logic state of a pre-charge control signal, thereby reducing the probability of occurrence of defect in a semiconductor memory device.
摘要翻译：具有与位线对和字线对连接的存储单元的半导体存储器件包括预充电部分，用于响应于半导体存储器件的待机模式下的第一状态控制信号对一对位线进行预充电 ; 位线充电控制部分，用于当由于一对位线中的缺陷而发生待机电流故障时，向预充电部分产生第二状态控制信号，其中第二状态控制信号独立于预充电相关信号外部施加，并且预充电部分切断电源电压而不被施加到一对位线; 以及位线浮动防止部件，用于以缺陷补偿地固定一对位线的电位值，使得防止单元电源电压被施加到半导体存储器件的存储器访问模式下的缺陷的位线对，使得像预备电流故障那样的硬型缺陷可以被修复，而不管预充电控制信号的逻辑状态如何，从而降低了半导体存储器件中的缺陷的发生概率。

2. 发明授权

US5956279A Static random access memory device with burn-in test circuit 失效
标题翻译：具有老化测试电路的静态随机存取存储器
公开(公告)号：US5956279A
公开(公告)日：1999-09-21
申请号：US19519
申请日：1998-02-05
申请人： Hyun-Sun Mo , Choong-Keun Kwak
发明人： Hyun-Sun Mo , Choong-Keun Kwak
IPC分类号： G11C11/413 , G11C29/34 , G11C7/00
CPC分类号： G11C29/34
摘要： A static random access memory (SRAM) device comprises an array of memory cells, a plurality of bit line precharge circuit for selectively delivering current to bit lines in response to a pair of control signals, during normal and burn-in test modes, and a burn-in current source circuit for selectively delivering current to the memory cells selected by the word lines along with the precharge circuit, in response to the control signals, during the burn-in test mode. In burn-in write operation, memory cells can be supplied with enough cell current without large increasing of chip size and power consumption in normal operation mode.
摘要翻译：静态随机存取存储器（SRAM）装置包括存储器单元阵列，多个位线预充电电路，用于在正常和老化测试模式期间响应于一对控制信号选择性地将电流输送到位线;以及老化电流源电路，用于在老化测试模式期间响应于控制信号选择性地将电流与预充电电路一起输送到由字线选择的存储器单元。在老化写入操作中，在正常操作模式下，存储单元可以提供足够的单元电流，而不会大大增加芯片尺寸和功耗。

3. 发明授权

US07684238B2 Methods of programming multi-bit flash memory devices and related devices 有权
标题翻译：编程多位闪存设备及相关设备的方法
公开(公告)号：US07684238B2
公开(公告)日：2010-03-23
申请号：US11843219
申请日：2007-08-22
申请人： Hyun-Sun Mo
发明人： Hyun-Sun Mo
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： Methods of programming a multi-bit non-volatile memory device are provided. The multi-bit non-volatile memory device includes a memory cell array including a plurality of memory cells and a storage unit electrically coupled to the memory cell array. A first bit (FB) of multi-bit data is programmed from the storage unit into one of the plurality of memory cells in the memory cell array. A second bit (SB) of multi-bit data is programmed from the storage unit into one of the plurality of memory cells in the memory cell array using data inversion. Related memory devices are also provided.
摘要翻译：提供了对多位非易失性存储器件进行编程的方法。该多位非易失性存储器件包括存储单元阵列，该存储单元阵列包括多个存储单元和与该存储单元阵列电耦合的存储单元。多位数据的第一位（FB）从存储单元被编程为存储单元阵列中的多个存储单元之一。使用数据反转，多位数据的第二位（SB）从存储单元编程到存储单元阵列中的多个存储单元之一。还提供了相关的存储器件。

4. 发明申请

US20080052445A1 FLASH MEMORY DEVICES INCLUDING BLOCK INFORMATION BLOCKS AND METHODS OF OPERATING SAME 审中-公开
标题翻译：包括块信息块的闪存存储器件及其操作方法
公开(公告)号：US20080052445A1
公开(公告)日：2008-02-28
申请号：US11669553
申请日：2007-01-31
申请人： Eun-Kyoung Kim , Hyun-Sun Mo , Sang-Chul Kang
发明人： Eun-Kyoung Kim , Hyun-Sun Mo , Sang-Chul Kang
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G11C16/04 , G11C29/76 , G11C2229/723
摘要： Disclosed is a semiconductor memory device including pluralities of memory blocks each of which is segmented into main and spare regions, and a block information storing region storing block information of the memory blocks.
摘要翻译：公开了一种半导体存储器件，其包括多个存储块，每个存储块被分割成主区域和备用区域，以及块信息存储区域，存储存储块的块信息。

5. 发明申请

US20070177434A1 Three-level nonvolatile semiconductor memory device and associated method of operation 有权
标题翻译：三级非易失性半导体存储器件及其相关操作方法
公开(公告)号：US20070177434A1
公开(公告)日：2007-08-02
申请号：US11595923
申请日：2006-11-13
申请人： Hyun-Sun Mo , Ho-Jung Kim
发明人： Hyun-Sun Mo , Ho-Jung Kim
IPC分类号： G11C7/10
CPC分类号： G11C7/18 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C2211/5642
摘要： A nonvolatile semiconductor memory device comprises a memory array of 3-level nonvolatile memory cells. The memory array comprises first even and odd strings of memory cells connected to respective first even and odd bit lines and second even and odd strings of memory cells connected to respective second even and odd bit lines. The first even and odd bit lines are selectively connected to a first common bit line during data programming and read operations, and the second even and odd bit lines are selectively connected to a second common bit line during data programming and read operations. The device programs and reads data in a pair of memory cells using three bits of data corresponding to three threshold voltage distributions of the 3-level nonvolatile memory cells.
摘要翻译：非易失性半导体存储器件包括3级非易失性存储单元的存储器阵列。存储器阵列包括连接到相应的第一偶数和奇数位线以及连接到相应的第二偶数和奇数位线的存储器单元的第二偶数和奇数串的存储器单元的第一奇偶串。在数据编程和读取操作期间，第一偶数和奇数位线选择性地连接到第一公共位线，并且在数据编程和读取操作期间，第二偶数和奇数位线选择性地连接到第二公共位线。器件使用对应于3级非易失性存储器单元的三个阈值电压分布的三位数据来编程和读取一对存储器单元中的数据。

6. 发明授权

US07142045B2 Circuit for generating internal voltage 有权
标题翻译：产生内部电压的电路
公开(公告)号：US07142045B2
公开(公告)日：2006-11-28
申请号：US10881937
申请日：2004-06-30
申请人： Hyun-Sun Mo , Sang-Ki Hwang
发明人： Hyun-Sun Mo , Sang-Ki Hwang
IPC分类号： G05F3/02
CPC分类号： G11C5/147
摘要： There is provided an internal voltage generating circuit that reliably supplies a constant internal voltage to the interior of a semiconductor device without regard to an external voltage, where the internal voltage generating circuit compares a first reference voltage with a first internal voltage fed back to generate the first internal voltage following the first reference voltage, receives the first internal voltage to generate a second reference voltage which is more insensitive to fluctuation of the external voltage than the first reference voltage, and compares the second reference voltage with a second internal voltage fed back to generate the second internal voltage which follows the second reference voltage and has a variation gradient smaller than that of the first internal voltage when the external voltage is changed, thereby supplying the second internal voltage to a circuit requiring stabilized internal voltage, which is obtained to increase stability and durability of the operation of the semiconductor device.
摘要翻译：提供内部电压发生电路，其可靠地将外部电压与内部电压产生电路进行比较，将第一参考电压与反馈的第一内部电压进行比较，从而可靠地将恒定的内部电压提供给半导体器件的内部，第一内部电压跟随第一参考电压，接收第一内部电压以产生比第一参考电压对外部电压的波动更不敏感的第二参考电压，并将第二参考电压与反馈到第二参考电压的第二内部电压进行比较产生跟随第二参考电压的第二内部电压，并且当外部电压改变时具有小于第一内部电压的变化梯度的变化梯度，从而将第二内部电压提供给需要稳定的内部电压的电路，从而增加稳定性和耐久性半导体器件的操作。

7. 发明申请

US20050017704A1 Circuit for generating internal voltage 有权
标题翻译：产生内部电压的电路
公开(公告)号：US20050017704A1
公开(公告)日：2005-01-27
申请号：US10881937
申请日：2004-06-30
申请人： Hyun-Sun Mo , Sang-Ki Hwang
发明人： Hyun-Sun Mo , Sang-Ki Hwang
IPC分类号： G11C5/14 , G11C5/00
CPC分类号： G11C5/147
摘要： There is provided an internal voltage generating circuit that reliably supplies a constant internal voltage to the interior of a semiconductor device without regard to an external voltage, where the internal voltage generating circuit compares a first reference voltage with a first internal voltage fed back to generate the first internal voltage following the first reference voltage, receives the first internal voltage to generate a second reference voltage which is more insensitive to fluctuation of the external voltage than the first reference voltage, and compares the second reference voltage with a second internal voltage fed back to generate the second internal voltage which follows the second reference voltage and has a variation gradient smaller than that of the first internal voltage when the external voltage is changed, thereby supplying the second internal voltage to a circuit requiring stabilized internal voltage, which is obtained to increase stability and durability of the operation of the semiconductor device.
摘要翻译：提供内部电压发生电路，其可靠地将外部电压与内部电压产生电路进行比较，将第一参考电压与反馈的第一内部电压进行比较，从而可靠地将恒定的内部电压提供给半导体器件的内部，第一内部电压跟随第一参考电压，接收第一内部电压以产生比第一参考电压对外部电压的波动更不敏感的第二参考电压，并将第二参考电压与反馈到第二参考电压的第二内部电压进行比较产生跟随第二参考电压的第二内部电压，并且当外部电压改变时具有小于第一内部电压的变化梯度的变化梯度，从而将第二内部电压提供给需要稳定的内部电压的电路，从而增加稳定性和耐久性半导体器件的操作。

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