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41. 发明申请

US20090250760A1 METHODS OF FORMING HIGH-K/METAL GATES FOR NFETS AND PFETS 审中-公开
标题翻译：形成用于NFET和PFET的高K /金属栅的方法
公开(公告)号：US20090250760A1
公开(公告)日：2009-10-08
申请号：US12061081
申请日：2008-04-02
申请人： Michael P. Chudzik , William K. Henson , Naim Moumen , Dae-Gyu Park , Hongwen Yan
发明人： Michael P. Chudzik , William K. Henson , Naim Moumen , Dae-Gyu Park , Hongwen Yan
IPC分类号： H01L27/088 , H01L21/4763
CPC分类号： H01L21/84 , H01L21/823842 , H01L21/823857
摘要： Methods of forming high-k/metal gates for an NFET and PFET and a related structure are disclosed. One method includes recessing a PFET region; forming a first high-k dielectric layer and a first metal layer over the substrate; removing the first high-k dielectric layer and the first metal over the NFET region using a mask; forming a forming a second high-k dielectric layer and a second metal layer over the substrate, the first high-k dielectric layer being different then the second high-k dielectric layer and the first metal being different than the second metal; removing the second high-k dielectric layer and the second metal over the PFET region using a mask; depositing a polysilicon over the substrate; and forming a gate over the NFET region and the PFET region by simultaneously etching the polysilicon, the first high-k dielectric layer, the first metal, the second high-k dielectric layer and the second metal.
摘要翻译：公开了形成用于NFET和PFET的高k /金属栅极和相关结构的方法。一种方法包括使PFET区域凹陷; 在所述衬底上形成第一高k电介质层和第一金属层; 使用掩模在NFET区域上去除第一高k电介质层和第一金属; 在所述衬底上形成第二高k电介质层和第二金属层，所述第一高k电介质层与所述第二高k电介质层不同，所述第一金属与所述第二金属不同; 使用掩模在PFET区域上去除第二高k电介质层和第二金属; 在衬底上沉积多晶硅; 以及通过同时蚀刻多晶硅，第一高k电介质层，第一金属，第二高k电介质层和第二金属，在NFET区域和PFET区域上形成栅极。

42. 发明申请

US20090186455A1 DISPOSABLE METALLIC OR SEMICONDUCTOR GATE SPACER 失效
标题翻译：可拆卸金属或半导体门间隔
公开(公告)号：US20090186455A1
公开(公告)日：2009-07-23
申请号：US12016326
申请日：2008-01-18
申请人： Stephen W. Bedell , Michael Chudzik , William K. Henson , Naim Moumen , Vijay Narayanan , Devendra K. Sadana , Kathryn T. Schonenberg , Ghavam Shahidi
发明人： Stephen W. Bedell , Michael Chudzik , William K. Henson , Naim Moumen , Vijay Narayanan , Devendra K. Sadana , Kathryn T. Schonenberg , Ghavam Shahidi
IPC分类号： H01L21/8238
CPC分类号： H01L29/7847 , H01L21/324 , H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A disposable spacer is formed directly on or in close proximity to the sidewalls of a gate electrode and a gate dielectric. The disposable spacer comprises a material that scavenges oxygen such as a metal, a metal nitride, or a semiconductor material having high reactivity with oxygen. The disposable gate spacer absorbs any oxygen during subsequent high temperature processing such as a stress memorization anneal. A metal is deposited over, and reacted with, the gate electrode and source and drain regions to form metal semiconductor alloy regions. The disposable gate spacer is subsequently removed selective to the metal semiconductor alloy regions. A porous or non-porous low-k dielectric material is deposited to provide a low parasitic capacitance between the gate electrode and the source and drain regions. The gate dielectric maintains the original dielectric constant since the disposable gate spacer prevents absorption of additional oxygen during high temperature processes.
摘要翻译：一次性间隔物直接形成在栅极电极和栅极电介质的侧壁上或紧邻栅电极的侧壁上。一次性间隔物包括清除氧的材料，例如金属，金属氮化物或具有高氧反应性的半导体材料。一次性栅极间隔件在随后的高温处理例如应力记忆退火期间吸收任何氧气。将金属沉积在栅电极和源极和漏极区上并与其反应以形成金属半导体合金区域。一次性栅极间隔物随后被选择性地移除到金属半导体合金区域。沉积多孔或非多孔低k电介质材料以在栅极电极和源极和漏极区域之间提供低的寄生电容。栅极电介质保持原始介电常数，因为一次性栅极间隔物可防止在高温过程中吸收额外的氧。

43. 发明授权

US07550323B2 Electrical fuse with a thinned fuselink middle portion 失效
标题翻译：电熔丝带有细长的中间部分
公开(公告)号：US07550323B2
公开(公告)日：2009-06-23
申请号：US11835800
申请日：2007-08-08
申请人： Dureseti Chidambarrao , William K. Henson , Deok-kee Kim , Chandrasekharan Kothandaraman
发明人： Dureseti Chidambarrao , William K. Henson , Deok-kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A metal layer is deposited on the patterned semiconductor material layer containing a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. The metal layer may be patterned so that a middle portion of the fuselink semiconductor portion has a thin metal layer, which upon annealing produces a thinner metal semiconductor alloy portion than surrounding metal semiconductor alloy portion on the fuselink semiconductor portion. Alternatively, a middle portion of the metal semiconductor alloy having a uniform thickness throughout the fuselink may be lithographically patterned and etched to form a thin metal semiconductor alloy portion in the middle of the fuselink, while thick metal semiconductor alloy portions are formed on the end portions of the fuselink. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink to enhance the divergence of electrical current.
摘要翻译：在包含阴极半导体部分，熔丝半导体部分和阳极半导体部分的图案化的半导体材料层上沉积金属层。可以对金属层进行图案化，使得熔融半导体部分的中间部分具有薄金属层，其在退火时产生比在熔融半导体部分上的周围金属半导体合金部分更薄的金属半导体合金部分。或者，在整个整体中具有均匀厚度的金属半导体合金的中间部分可以被光刻图案化和蚀刻，以在熔丝中间形成薄金属半导体合金部分，同时在端部形成厚金属半导体合金部分的fuselink。所产生的本发明的电熔丝具有界面，在该界面上，较薄的金属半导体合金与所述富熔体中较厚的金属半导体合金相接触以增强电流的发散。

44. 发明申请

US20090042341A1 ELECTRICAL FUSE WITH A THINNED FUSELINK MIDDLE PORTION 失效
标题翻译：带有薄型熔断器中间部分的电气保险丝
公开(公告)号：US20090042341A1
公开(公告)日：2009-02-12
申请号：US11835800
申请日：2007-08-08
申请人： Dureseti Chidambarrao , William K. Henson , Deok-kee Kim , Chandrasekharan Kothandaraman
发明人： Dureseti Chidambarrao , William K. Henson , Deok-kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A metal layer is deposited on the patterned semiconductor material layer containing a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. The metal layer may be patterned so that a middle portion of the fuselink semiconductor portion has a thin metal layer, which upon annealing produces a thinner metal semiconductor alloy portion than surrounding metal semiconductor alloy portion on the fuselink semiconductor portion. Alternatively, a middle portion of the metal semiconductor alloy having a uniform thickness throughout the fuselink may be lithographically patterned and etched to form a thin metal semiconductor alloy portion in the middle of the fuselink, while thick metal semiconductor alloy portions are formed on the end portions of the fuselink. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink to enhance the divergence of electrical current.
摘要翻译：在包含阴极半导体部分，熔丝半导体部分和阳极半导体部分的图案化的半导体材料层上沉积金属层。可以对金属层进行图案化，使得熔融半导体部分的中间部分具有薄金属层，其在退火时产生比在熔融半导体部分上的周围金属半导体合金部分更薄的金属半导体合金部分。或者，在整个整体中具有均匀厚度的金属半导体合金的中间部分可以被光刻图案化和蚀刻，以在熔丝中间形成薄金属半导体合金部分，同时在端部形成厚金属半导体合金部分的fuselink。所产生的本发明的电熔丝具有界面，在该界面上，较薄的金属半导体合金与所述富熔体中较厚的金属半导体合金相接触以增强电流的发散。

45. 发明申请

US20080169529A1 EFUSE CONTAINING SIGE STACK 有权
标题翻译： EFUSE包含信号堆栈
公开(公告)号：US20080169529A1
公开(公告)日：2008-07-17
申请号：US11622616
申请日：2007-01-12
申请人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
发明人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.
摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

46. 发明申请

US20080054357A1 SEMICONDUCTOR STRUCTURE WITH ENHANCED PERFORMANCE USING A SIMPLIFIED DUAL STRESS LINER CONFIGURATION 失效
标题翻译：使用简化的双应力衬里配置提高性能的半导体结构
公开(公告)号：US20080054357A1
公开(公告)日：2008-03-06
申请号：US11468958
申请日：2006-08-31
申请人： Dureseti Chidambarrao , Yaocheng Liu , William K. Henson
发明人： Dureseti Chidambarrao , Yaocheng Liu , William K. Henson
IPC分类号： H01L27/12
CPC分类号： H01L21/28097 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/4908 , H01L29/4975 , H01L29/665 , H01L29/66545 , H01L29/7843
摘要： A semiconductor structure including an nFET having a fully silicided gate electrode wherein a new dual stress liner configuration is used to enhance the stress in the channel region that lies beneath the gate electrode is provided. The new dual stress liner configuration includes a first stress liner that has an upper surface that is substantially planar with an upper surface of a fully silicided gate electrode of the nFET. In accordance with the present invention, the first stress liner is not present atop the nFET including the fully silicided gate electrode. Instead, the first stress liner of the present invention partially wraps around, i.e., surrounds the sides of, the nFET with the fully silicided gate electrode. A second stress liner having an opposite polarity as that of the first stress liner (i.e., of an opposite stress type) is located on the upper surface of the first stress liner as well as atop the nFET that contains the fully silicided FET. In accordance with the present invention, the first stress liner is a tensile stress liner and the second stress liner is a compressive stress liner.
摘要翻译：提供了包括具有完全硅化栅电极的nFET的半导体结构，其中使用新的双应力衬垫配置来增强位于栅电极下方的沟道区中的应力。新的双应力衬垫构造包括第一应力衬垫，其具有与nFET的完全硅化栅电极的上表面基本上平面的上表面。根据本发明，第一应力衬垫不存在于包括全硅化物栅电极的nFET顶部。相反，本发明的第一应力衬垫部分地包裹着nFET的侧面，即用完全硅化的栅电极包围nFET。具有与第一应力衬垫相反极性（即相反应力类型）的第二应力衬垫位于第一应力衬垫的上表面上以及位于包含完全硅化FET的nFET顶上。根据本发明，第一应力衬垫是拉伸应力衬垫，第二应力衬垫是压应力衬垫。

47. 发明授权

US08598009B2 Self-aligned embedded SiGe structure and method of manufacturing the same 失效
标题翻译：自对准嵌入式SiGe结构及其制造方法
公开(公告)号：US08598009B2
公开(公告)日：2013-12-03
申请号：US13456633
申请日：2012-04-26
申请人： Brian J. Greene , William K. Henson , Judson R. Holt , Michael D. Steigerwalt , Kuldeep Amarnath , Rohit Pal , Johan W. Weijtmans
发明人： Brian J. Greene , William K. Henson , Judson R. Holt , Michael D. Steigerwalt , Kuldeep Amarnath , Rohit Pal , Johan W. Weijtmans
IPC分类号： H01L21/8222
CPC分类号： H01L29/66636 , H01L21/3247 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/7848
摘要： A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.
摘要翻译：低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

48. 发明申请

US20130105894A1 THRESHOLD VOLTAGE ADJUSTMENT FOR THIN BODY MOSFETS 有权
标题翻译：用于薄体MOSFET的阈值电压调整
公开(公告)号：US20130105894A1
公开(公告)日：2013-05-02
申请号：US13282619
申请日：2011-10-27
申请人： MaryJane Brodsky , Ming Cai , Dechao Guo , William K. Henson , Shreesh Narasimha , Yue Liang , Liyang Song , Yanfeng Wang , Chun-Chen Yeh
发明人： MaryJane Brodsky , Ming Cai , Dechao Guo , William K. Henson , Shreesh Narasimha , Yue Liang , Liyang Song , Yanfeng Wang , Chun-Chen Yeh
IPC分类号： H01L27/12 , H01L21/04
CPC分类号： H01L29/66803
摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.
摘要翻译：一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。还公开了制造FinFET晶体管的方法。还公开了具有碳注入阱的平面晶体管，其中选择阱内的碳浓度以建立晶体管的期望电压阈值。

49. 发明授权

US08222673B2 Self-aligned embedded SiGe structure and method of manufacturing the same 失效
标题翻译：自对准嵌入式SiGe结构及其制造方法
公开(公告)号：US08222673B2
公开(公告)日：2012-07-17
申请号：US12795683
申请日：2010-06-08
申请人： Brian J. Greene , William K. Henson , Judson R. Holt , Michael D. Steigerwalt , Kuldeep Amarnath , Rohit Pal , Johan W. Weijtmans
发明人： Brian J. Greene , William K. Henson , Judson R. Holt , Michael D. Steigerwalt , Kuldeep Amarnath , Rohit Pal , Johan W. Weijtmans
IPC分类号： H01L21/02
CPC分类号： H01L29/66636 , H01L21/3247 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/7848
摘要： A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.
摘要翻译：低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

50. 发明授权

US08138037B2 Method and structure for gate height scaling with high-k/metal gate technology 有权
标题翻译：使用高k /金属栅极技术的栅极高度缩放的方法和结构
公开(公告)号：US08138037B2
公开(公告)日：2012-03-20
申请号：US12715781
申请日：2010-03-02
申请人： Michael P. Chudzik , Ricardo A. Donaton , William K. Henson , Yue Liang
发明人： Michael P. Chudzik , Ricardo A. Donaton , William K. Henson , Yue Liang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823437 , H01L21/28088 , H01L27/0629 , H01L27/0802 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor. The method also includes selectively removing the dummy gate while protecting the at least one polysilicon feature. The method further includes forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature.
摘要翻译：一种在高k /金属栅极晶体管中缩放金属栅极高度的方法和结构。一种方法包括形成伪栅极和至少一个多晶硅特征，所述多晶硅特征全部由相同的多晶硅层形成，并且其中所述伪栅极形成在与晶体管相关联的栅极金属层上。该方法还包括选择性地去除伪栅极，同时保护至少一个多晶硅特征。该方法还包括在栅极金属层上形成栅极接触，从而形成高度小于至少一个多晶硅特征的一半高度的金属栅极。

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