专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08004059B2 eFuse containing SiGe stack 有权
标题翻译： eFuse包含SiGe堆栈
公开(公告)号：US08004059B2
公开(公告)日：2011-08-23
申请号：US11622616
申请日：2007-01-12
申请人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
发明人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.
摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

2. 发明授权

US07960809B2 eFuse with partial SiGe layer and design structure therefor 有权
标题翻译： eFuse部分SiGe层及其设计结构
公开(公告)号：US07960809B2
公开(公告)日：2011-06-14
申请号：US12354996
申请日：2009-01-16
申请人： Chandrasekharan Kothandaraman , Deok-kee Kim , Dureseti Chidambarrao , William K. Henson
发明人： Chandrasekharan Kothandaraman , Deok-kee Kim , Dureseti Chidambarrao , William K. Henson
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse includes a fuse link region, a first region and a second region. The fuse link region electrically connects the first region to the second region. A SiGe layer is disposed only in the fuse link region and the first region.
摘要翻译：熔丝包括熔丝链接区域，第一区域和第二区域。熔丝链路区域将第一区域电连接到第二区域。 SiGe层仅设置在熔丝连接区域和第一区域中。

3. 发明授权

US08299570B2 Efuse containing sige stack 有权
标题翻译： Efuse包含sige堆栈
公开(公告)号：US08299570B2
公开(公告)日：2012-10-30
申请号：US13189016
申请日：2011-07-22
申请人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
发明人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.
摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

4. 发明授权

US07838963B2 Electrical fuse having a fully silicided fuselink and enhanced flux divergence 有权
标题翻译：电熔丝具有完全硅化的富熔体和增强的焊剂分散
公开(公告)号：US07838963B2
公开(公告)日：2010-11-23
申请号：US11925164
申请日：2007-10-26
申请人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
发明人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L29/86
CPC分类号： H01L23/5256 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.
摘要翻译：在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。

5. 发明申请

US20090040006A1 ELECTRICAL FUSE WITH ENHANCED PROGRAMMING CURRENT DIVERGENCE 审中-公开
标题翻译：电子保险丝与增强编程电流分流
公开(公告)号：US20090040006A1
公开(公告)日：2009-02-12
申请号：US11835846
申请日：2007-08-08
申请人： Dureseti Chidambarrao , William K. Henson , Deok-kee Kim , Chandrasekharan Kothandaraman
发明人： Dureseti Chidambarrao , William K. Henson , Deok-kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01H85/143 , B23P19/00
CPC分类号： G11C17/16 , Y10T29/49117
摘要： A layer of semiconductor material is patterned to form a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. A first metal layer is deposited on the patterned semiconductor material layer. A dielectric material layer is deposited and lithographically patterned to cover a middle portion of the fuselink, followed by a deposition of a second metal layer. A thin metal semiconductor alloy is formed in the middle of the fuselink and thick metal semiconductor alloy alloys are formed abutting the thin metal semiconductor alloy alloy. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink. The divergence of electrical current is enhanced at the interfaces due to a sudden change of a cross-sectional area available for current conduction.
摘要翻译：图案化半导体材料层以形成阴极半导体部分，熔丝半导体部分和阳极半导体部分。在图案化的半导体材料层上沉积第一金属层。介电材料层被沉积并且被光刻图案化以覆盖该熔丝的中间部分，随后沉积第二金属层。在熔体中间形成有薄金属半导体合金，并且与金属半导体合金合金形成邻接的厚金属半导体合金合金。所产生的本发明的电熔丝具有界面，在该界面处，较薄的金属半导体合金与所述熔丝中的较厚的金属半导体合金相邻。由于可用于电流传导的横截面积的突然变化，在接口处的电流的发散度增强。

6. 发明申请

US20110272779A1 EFUSE CONTAINING SIGE STACK 有权
标题翻译： EFUSE包含信号堆栈
公开(公告)号：US20110272779A1
公开(公告)日：2011-11-10
申请号：US13189016
申请日：2011-07-22
申请人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
发明人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.
摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

7. 发明授权

US07943493B2 Electrical fuse having a fully silicided fuselink and enhanced flux divergence 有权
标题翻译：电熔丝具有完全硅化的富熔体和增强的焊剂分散
公开(公告)号：US07943493B2
公开(公告)日：2011-05-17
申请号：US12873882
申请日：2010-09-01
申请人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
发明人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L21/20
CPC分类号： H01L23/5256 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.
摘要翻译：在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。

8. 发明申请

US20100330783A1 ELECTRICAL FUSE HAVING A FULLY SILICIDED FUSELINK AND ENHANCED FLUX DIVERGENCE 有权
标题翻译：全自动充电式电熔炉和增强型流量分流器
公开(公告)号：US20100330783A1
公开(公告)日：2010-12-30
申请号：US12873882
申请日：2010-09-01
申请人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
发明人： Dureseti Chidambarrao , William K. Henson , Deok-Kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L21/20
CPC分类号： H01L23/5256 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.
摘要翻译：在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。

9. 发明申请

US20100181643A1 EFUSE WITH PARTIAL SIGE LAYER AND DESIGN STRUCTURE THEREFOR 有权
标题翻译：具有部分信号层及其设计结构
公开(公告)号：US20100181643A1
公开(公告)日：2010-07-22
申请号：US12354996
申请日：2009-01-16
申请人： Chandrasekharan Kothandaraman , Deok-kee Kim , Dureseti Chidambarrao , William K. Henson
发明人： Chandrasekharan Kothandaraman , Deok-kee Kim , Dureseti Chidambarrao , William K. Henson
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse includes a fuse link region, a first region and a second region. The fuse link region electrically connects the first region to the second region. A SiGe layer is disposed only in the fuse link region and the first region.
摘要翻译：熔丝包括熔丝链接区域，第一区域和第二区域。熔丝链路区域将第一区域电连接到第二区域。 SiGe层仅设置在熔丝连接区域和第一区域中。

10. 发明授权

US07550323B2 Electrical fuse with a thinned fuselink middle portion 失效
标题翻译：电熔丝带有细长的中间部分
公开(公告)号：US07550323B2
公开(公告)日：2009-06-23
申请号：US11835800
申请日：2007-08-08
申请人： Dureseti Chidambarrao , William K. Henson , Deok-kee Kim , Chandrasekharan Kothandaraman
发明人： Dureseti Chidambarrao , William K. Henson , Deok-kee Kim , Chandrasekharan Kothandaraman
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A metal layer is deposited on the patterned semiconductor material layer containing a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. The metal layer may be patterned so that a middle portion of the fuselink semiconductor portion has a thin metal layer, which upon annealing produces a thinner metal semiconductor alloy portion than surrounding metal semiconductor alloy portion on the fuselink semiconductor portion. Alternatively, a middle portion of the metal semiconductor alloy having a uniform thickness throughout the fuselink may be lithographically patterned and etched to form a thin metal semiconductor alloy portion in the middle of the fuselink, while thick metal semiconductor alloy portions are formed on the end portions of the fuselink. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink to enhance the divergence of electrical current.
摘要翻译：在包含阴极半导体部分，熔丝半导体部分和阳极半导体部分的图案化的半导体材料层上沉积金属层。可以对金属层进行图案化，使得熔融半导体部分的中间部分具有薄金属层，其在退火时产生比在熔融半导体部分上的周围金属半导体合金部分更薄的金属半导体合金部分。或者，在整个整体中具有均匀厚度的金属半导体合金的中间部分可以被光刻图案化和蚀刻，以在熔丝中间形成薄金属半导体合金部分，同时在端部形成厚金属半导体合金部分的fuselink。所产生的本发明的电熔丝具有界面，在该界面上，较薄的金属半导体合金与所述富熔体中较厚的金属半导体合金相接触以增强电流的发散。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式