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1. 发明申请

US20090250760A1 METHODS OF FORMING HIGH-K/METAL GATES FOR NFETS AND PFETS 审中-公开
标题翻译：形成用于NFET和PFET的高K /金属栅的方法
公开(公告)号：US20090250760A1
公开(公告)日：2009-10-08
申请号：US12061081
申请日：2008-04-02
申请人： Michael P. Chudzik , William K. Henson , Naim Moumen , Dae-Gyu Park , Hongwen Yan
发明人： Michael P. Chudzik , William K. Henson , Naim Moumen , Dae-Gyu Park , Hongwen Yan
IPC分类号： H01L27/088 , H01L21/4763
CPC分类号： H01L21/84 , H01L21/823842 , H01L21/823857
摘要： Methods of forming high-k/metal gates for an NFET and PFET and a related structure are disclosed. One method includes recessing a PFET region; forming a first high-k dielectric layer and a first metal layer over the substrate; removing the first high-k dielectric layer and the first metal over the NFET region using a mask; forming a forming a second high-k dielectric layer and a second metal layer over the substrate, the first high-k dielectric layer being different then the second high-k dielectric layer and the first metal being different than the second metal; removing the second high-k dielectric layer and the second metal over the PFET region using a mask; depositing a polysilicon over the substrate; and forming a gate over the NFET region and the PFET region by simultaneously etching the polysilicon, the first high-k dielectric layer, the first metal, the second high-k dielectric layer and the second metal.
摘要翻译：公开了形成用于NFET和PFET的高k /金属栅极和相关结构的方法。一种方法包括使PFET区域凹陷; 在所述衬底上形成第一高k电介质层和第一金属层; 使用掩模在NFET区域上去除第一高k电介质层和第一金属; 在所述衬底上形成第二高k电介质层和第二金属层，所述第一高k电介质层与所述第二高k电介质层不同，所述第一金属与所述第二金属不同; 使用掩模在PFET区域上去除第二高k电介质层和第二金属; 在衬底上沉积多晶硅; 以及通过同时蚀刻多晶硅，第一高k电介质层，第一金属，第二高k电介质层和第二金属，在NFET区域和PFET区域上形成栅极。

2. 发明申请

US20100038725A1 CHANGING EFFECTIVE WORK FUNCTION USING ION IMPLANTATION DURING DUAL WORK FUNCTION METAL GATE INTEGRATION 有权
标题翻译：在双功能金属门整合期间使用离子植入改变有效的工作功能
公开(公告)号：US20100038725A1
公开(公告)日：2010-02-18
申请号：US12190220
申请日：2008-08-12
申请人： Michael P. Chudzik , Martin M. Frank , Herbert L. Ho , Mark J. Hurley , Rashmi Jha , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
发明人： Michael P. Chudzik , Martin M. Frank , Herbert L. Ho , Mark J. Hurley , Rashmi Jha , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/49 , H01L21/28079 , H01L21/28088 , H01L21/823842 , H01L27/092 , H01L29/4958 , H01L29/517
摘要： Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.
摘要翻译：提出了离子注入来改变双功能金属栅极整合的有效功函数。一种方法可以包括在第一类型场效应晶体管（FET）区域和第二类型FET区域上形成高介电常数（高k）层; 在第一型FET区域和第二类型FET区域上形成具有与第一型FET兼容的第一有效功函数的金属层; 以及通过在第二类型FET区域上将金属注入到金属层中，将第一有效功函数改变为第二类不同的有效功函数。

3. 发明授权

US08753936B2 Changing effective work function using ion implantation during dual work function metal gate integration 有权
标题翻译：在双功能金属门集成中，使用离子注入来改变有效的功函数
公开(公告)号：US08753936B2
公开(公告)日：2014-06-17
申请号：US12190220
申请日：2008-08-12
申请人： Michael P. Chudzik , Martin M. Frank , Herbert L. Ho , Mark J. Hurley , Rashmi Jha , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
发明人： Michael P. Chudzik , Martin M. Frank , Herbert L. Ho , Mark J. Hurley , Rashmi Jha , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
IPC分类号： H01L21/8234
CPC分类号： H01L29/49 , H01L21/28079 , H01L21/28088 , H01L21/823842 , H01L27/092 , H01L29/4958 , H01L29/517
摘要： Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.
摘要翻译：提出了离子注入来改变双功能金属栅极整合的有效功函数。一种方法可以包括在第一类型场效应晶体管（FET）区域和第二类型FET区域上形成高介电常数（高k）层; 在第一型FET区域和第二类型FET区域上形成具有与第一型FET兼容的第一有效功函数的金属层; 以及通过在第二类型FET区域上将金属注入到金属层中，将第一有效功函数改变为第二类不同的有效功函数。

4. 发明申请

US20110121401A1 Gate Effective-Workfunction Modification for CMOS 有权
标题翻译：门有效功能修改CMOS
公开(公告)号：US20110121401A1
公开(公告)日：2011-05-26
申请号：US13019949
申请日：2011-02-02
申请人： Dae-Gyu Park , Michael P. Chudzik , Rashmi Jha , Siddarth A. Krishnan , Naim Moumen , Vijay Narayanan , Vamsi Paruchuri
发明人： Dae-Gyu Park , Michael P. Chudzik , Rashmi Jha , Siddarth A. Krishnan , Naim Moumen , Vijay Narayanan , Vamsi Paruchuri
IPC分类号： H01L27/092
CPC分类号： H01L21/823857 , H01L21/823842 , H01L29/785
摘要： CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.
摘要翻译：公开了CMOS电路结构，其中PFET和NFET器件具有由相同的栅极绝缘体材料构成的高k电介质层以及由相同栅极金属材料组成的金属栅极层。 PFET器件具有能够沿p方向移动栅极的有效功能的“p”接口控制层。在本发明的代表性实施例中，“p”界面控制层是氧化铝。 NFET器件可以具有“n”个界面控制层。 “p”和“n”界面控制层的材料是不同的材料。 “p”和“n”界面控制层位于其相应的高k电介质层的相对侧。还公开了制造具有相对定位的“p”和“n”界面控制层的CMOS电路结构的方法。

5. 发明授权

US09236314B2 High-K/metal gate stack using capping layer methods, IC and related transistors 有权
标题翻译：高K /金属栅极堆叠采用封盖层法，IC及相关晶体管
公开(公告)号：US09236314B2
公开(公告)日：2016-01-12
申请号：US13433659
申请日：2012-03-29
申请人： Michael P. Chudzik , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
发明人： Michael P. Chudzik , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
IPC分类号： H01L21/8238 , H01L29/49 , H01L29/51
CPC分类号： H01L21/823857 , H01L21/823842 , H01L29/4966 , H01L29/4975 , H01L29/517
摘要： Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.
摘要翻译：公开了使用具有高k /金属栅极叠层的封盖层的IC和相关晶体管。在一个实施例中，IC包括具有包括第一金属，第二金属和第一介电层的栅电极的第一类型晶体管，第一介电层包括氧; 通过隔离区与第一型晶体管分离的第二类型晶体管，第二类型晶体管具有包括具有适合于第二类型晶体管和第一介电层的功函数的第二金属的栅电极; 并且其中所述第一类型晶体管的栅极包括在所述第一金属和所述第二金属之间的稀土金属，并且所述第二类型晶体管的栅电极包括由所述稀土金属的氧化物制成的第二电介质层。

6. 发明申请

US20080203485A1 STRAINED METAL GATE STRUCTURE FOR CMOS DEVICES WITH IMPROVED CHANNEL MOBILITY AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有改进的通道移动性的CMOS器件的应变金属栅结构及其形成方法
公开(公告)号：US20080203485A1
公开(公告)日：2008-08-28
申请号：US11680108
申请日：2007-02-28
申请人： Michael P. Chudzik , Wei He , Renee T. Mo , Naim Moumen , Vijay Narayanan , Dae-gyu Park , Vamsi Paruchuri
发明人： Michael P. Chudzik , Wei He , Renee T. Mo , Naim Moumen , Vijay Narayanan , Dae-gyu Park , Vamsi Paruchuri
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/78 , H01L29/7845
摘要： A gate structure for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack having a first gate dielectric layer formed over a substrate, and a first metal layer formed over the first gate dielectric layer. A second gate stack includes a second gate dielectric layer formed over the substrate and a second metal layer formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate.
摘要翻译：用于互补金属氧化物半导体（CMOS）器件的栅极结构包括具有形成在衬底上的第一栅极介电层的第一栅极堆叠和形成在第一栅极介电层上的第一金属层。第二栅极堆叠包括形成在衬底上的第二栅极电介质层和形成在第二栅极介电层上的第二金属层。第一金属层形成为在基板上施加拉伸应力，并且第二金属层以使得在基板上施加压应力的方式形成。

7. 发明申请

US20120184093A1 HIGH-K/METAL GATE STACK USING CAPPING LAYER METHODS, IC AND RELATED TRANSISTORS 有权
标题翻译：使用覆盖层方法，IC和相关晶体管的高K /金属栅极堆叠
公开(公告)号：US20120184093A1
公开(公告)日：2012-07-19
申请号：US13433659
申请日：2012-03-29
申请人： Michael P. Chudzik , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
发明人： Michael P. Chudzik , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
IPC分类号： H01L21/28
CPC分类号： H01L21/823857 , H01L21/823842 , H01L29/4966 , H01L29/4975 , H01L29/517
摘要： Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.
摘要翻译：公开了使用具有高k /金属栅极叠层的封盖层的IC和相关晶体管。在一个实施例中，IC包括具有包括第一金属，第二金属和第一介电层的栅电极的第一类型晶体管，第一介电层包括氧; 通过隔离区与第一型晶体管分离的第二类型晶体管，第二类型晶体管具有包括具有适合于第二类型晶体管和第一介电层的功函数的第二金属的栅电极; 并且其中所述第一类型晶体管的栅极包括在所述第一金属和所述第二金属之间的稀土金属，并且所述第二类型晶体管的栅电极包括由所述稀土金属的氧化物制成的第二电介质层。

8. 发明申请

US20090212369A1 Gate Effective-Workfunction Modification for CMOS 有权
标题翻译：门有效功能修改CMOS
公开(公告)号：US20090212369A1
公开(公告)日：2009-08-27
申请号：US12037158
申请日：2008-02-26
申请人： Dae-Gyu Park , Michael P. Chudzik , Rashmi Jha , Siddarth A. Krishnan , Naim Moumen , Vijay Narayanan , Vamsi Paruchuri
发明人： Dae-Gyu Park , Michael P. Chudzik , Rashmi Jha , Siddarth A. Krishnan , Naim Moumen , Vijay Narayanan , Vamsi Paruchuri
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842 , H01L29/785
摘要： CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.
摘要翻译：公开了CMOS电路结构，其中PFET和NFET器件具有由相同的栅极绝缘体材料构成的高k电介质层以及由相同栅极金属材料组成的金属栅极层。 PFET器件具有能够沿p方向移动栅极的有效功能的“p”接口控制层。在本发明的代表性实施例中，“p”界面控制层是氧化铝。 NFET器件可以具有“n”个界面控制层。 “p”和“n”界面控制层的材料是不同的材料。 “p”和“n”界面控制层位于其相应的高k电介质层的相对侧。还公开了制造具有相对定位的“p”和“n”界面控制层的CMOS电路结构的方法。

9. 发明申请

US20090152636A1 HIGH-K/METAL GATE STACK USING CAPPING LAYER METHODS, IC AND RELATED TRANSISTORS 审中-公开
标题翻译：使用覆盖层方法，IC和相关晶体管的高K /金属栅极堆叠
公开(公告)号：US20090152636A1
公开(公告)日：2009-06-18
申请号：US11954749
申请日：2007-12-12
申请人： Michael P. Chudzik , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
发明人： Michael P. Chudzik , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
IPC分类号： H01L21/336 , H01L27/092 , H01L29/78
CPC分类号： H01L21/823857 , H01L21/823842 , H01L29/4966 , H01L29/4975 , H01L29/517
摘要： Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.
摘要翻译：公开了使用具有高k /金属栅极叠层的封盖层的IC和相关晶体管。在一个实施例中，IC包括具有包括第一金属，第二金属和第一介电层的栅电极的第一类型晶体管，第一介电层包括氧; 通过隔离区与第一型晶体管分离的第二类型晶体管，第二类型晶体管具有包括具有适合于第二类型晶体管和第一介电层的功函数的第二金属的栅电极; 并且其中所述第一类型晶体管的栅极包括在所述第一金属和所述第二金属之间的稀土金属，并且所述第二类型晶体管的栅电极包括由所述稀土金属的氧化物制成的第二电介质层。

10. 发明申请

US20120286374A1 HIGH-K DIELECTRIC GATE STRUCTURES RESISTANT TO OXIDE GROWTH AT THE DIELECTRIC/SILICON SUBSTRATE INTERFACE AND METHODS OF MANUFACTURE THEREOF 失效
标题翻译：介电/硅基板界面上耐高氧氧化物生长的高K电介质栅结构及其制造方法
公开(公告)号：US20120286374A1
公开(公告)日：2012-11-15
申请号：US13556795
申请日：2012-07-24
申请人： Huiming Bu , Michael P. Chudzik , Wei He , William K. Henson , Siddarth A. Krishnan , Unoh Kwon , Naim Moumen , Wesley C. Natzle
发明人： Huiming Bu , Michael P. Chudzik , Wei He , William K. Henson , Siddarth A. Krishnan , Unoh Kwon , Naim Moumen , Wesley C. Natzle
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L21/28088 , H01L21/2822 , H01L29/4966 , H01L29/51 , H01L29/66575
摘要： Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.
摘要翻译：用于制造栅电极/高k电介质栅极结构的方法，其具有改善的耐电介质/硅基衬底界面处二氧化硅（氧化物）生长的能力。在一个实施例中，形成晶体管栅极结构的方法包括：将氮掺入靠近衬底表面的硅基衬底中; 在所述硅基衬底上沉积高k栅极电介质; 以及在高k电介质上沉积栅电极以形成栅极结构。在一个实施例中，栅电极包含富含钛的氮化钛以抑制氧的扩散。

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