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    • 41. 发明授权
    • Method of fabricating self-aligned cross-point memory array
    • 制造自对准交叉点存储器阵列的方法
    • US06746910B2
    • 2004-06-08
    • US10262222
    • 2002-09-30
    • Sheng Teng HsuWei PanWei-Wei Zhuang
    • Sheng Teng HsuWei PanWei-Wei Zhuang
    • H01L218234
    • H01L27/24G11C11/5685G11C13/0007G11C2213/31G11C2213/77H01L27/101
    • A method of fabricating a self-aligned cross-point memory array includes preparing a substrate, including forming any supporting electronic structures; forming a p-well area on the substrate; implanting ions to form a deep N+ region; implanting ions to form a shallow P+ region on the N+ region to form a P+/N junction; depositing a barrier metal layer on the P+ region; depositing a bottom electrode layer on the barrier metal layer; depositing a sacrificial layer or silicon nitride layer on the bottom electrode layer; patterning and etching the structure to remove portions of the sacrificial layer, the bottom electrode layer, the barrier metal layer, the P+ region and the N+ region to form a trench; depositing oxide to fill the trench; patterning and etching the sacrificial layer; depositing a PCMO layer which is self-aligned with the remaining bottom electrode layer; depositing a top electrode layer, patterning and etching the top electrode layer, and completing the memory array structure.
    • 制造自对准交叉点存储器阵列的方法包括制备衬底,包括形成任何支撑电子结构; 在衬底上形成p阱区; 注入离子形成深N +区; 注入离子以形成N +区上的浅P +区以形成P + / N结; 在P +区上沉积阻挡金属层; 在阻挡金属层上沉积底部电极层; 在所述底部电极层上沉积牺牲层或氮化硅层; 图案化和蚀刻结构以去除牺牲层,底部电极层,阻挡金属层,P +区域和N +区域的部分以形成沟槽; 沉积氧化物以填充沟槽; 图案化和蚀刻牺牲层; 沉积与剩下的底部电极层自对准的PCMO层; 沉积顶部电极层,图案化和蚀刻顶部电极层,以及完成存储器阵列结构。
    • 42. 发明授权
    • Method for chemical mechanical polishing of thin films using end-point indicator structures
    • 使用端点指示器结构对薄膜进行化学机械抛光的方法
    • US06723643B1
    • 2004-04-20
    • US10391435
    • 2003-03-17
    • Wei PanDavid R. EvansAllen W. Burmaster
    • Wei PanDavid R. EvansAllen W. Burmaster
    • H01L2100
    • G11C13/0007G11C2213/31H01L45/04H01L45/1233H01L45/147H01L45/1683
    • A method of CMP thin films during fabrication of IC devices includes preparing a substrate, including building IC component structures on the substrate; depositing a bottom electrode on the substrate; depositing a first CMP layer having a first known CMP selectivity on the substrate; patterning the first CMP layer to form a pattern having a lower margin; forming indicator structures on the first CMP layer in the pattern; depositing a second CMP layer having a second known CMP selectivity relative to that of the first CMP layer, including depositing portions of the second CMP layer in the pattern of the first CMP layer; CMP the structure so that the indicator structures are removed and any portion of the first CMP layer and second CMP layer are removed to a level corresponding to the lower margin; and completing the IC structure.
    • 在IC器件制造期间的CMP薄膜的方法包括制备衬底,包括在衬底上建立IC组件结构; 在底物上沉积底部电极; 在衬底上沉积具有第一已知CMP选择性的第一CMP层; 图案化第一CMP层以形成具有较低边缘的图案; 在图案中的第一CMP层上形成指示器结构; 沉积相对于第一CMP层具有第二已知CMP选择性的第二CMP层,包括以第一CMP层的图案沉积第二CMP层的部分; CMP结构,使得指示器结构被去除,并且第一CMP层和第二CMP层的任何部分被去除到对应于下边缘的水平; 并完成IC结构。
    • 43. 发明授权
    • Method of fabricating copper interconnects with very low-k inter-level insulator
    • 制造具有极低k级绝缘体的铜互连的方法
    • US06686273B2
    • 2004-02-03
    • US09965582
    • 2001-09-26
    • Sheng Teng HsuWei Pan
    • Sheng Teng HsuWei Pan
    • H01L214763
    • H01L21/76811H01L21/76801
    • A method of forming a low-k inter-level insulator structure is provided comprising the steps of: providing a first metal layer; depositing a sacrificial insulator layer overlying the first metal layer; producing a second metal layer; removing the sacrificial insulator layer; and depositing a low-k inter-level insulator, whereby low-k material replaces the sacrificial insulator. An intermediate insulator layer structure is also provided comprising a sacrificial insulator layer overlying a low-k insulator layer, such that the sacrificial insulator layer may be subjected to processes, including CMP, which may be incompatible with low-k insulator materials.
    • 提供一种形成低k层间绝缘体结构的方法,包括以下步骤:提供第一金属层; 沉积覆盖在第一金属层上的牺牲绝缘体层; 产生第二金属层; 去除牺牲绝缘体层; 以及沉积低k级绝缘体,由此低k材料代替牺牲绝缘体。 还提供了一种中间绝缘体层结构,其包括覆盖低k绝缘体层的牺牲绝缘体层,使得牺牲绝缘体层可以经历可能与低k绝缘体材料不相容的包括CMP的工艺。
    • 44. 发明授权
    • Thin encapsulation process for making thin film read/write heads
    • 用于制造薄膜读/写头的薄封装工艺
    • US6099699A
    • 2000-08-08
    • US64212
    • 1998-04-22
    • Wei PanAnn KangJerome Marcelino
    • Wei PanAnn KangJerome Marcelino
    • C23C14/34G11B5/31G11B5/39
    • G11B5/3163C23C14/34G11B5/3106G11B5/313G11B5/3967
    • A process for providing a thin encapsulation layer for thin film heads includes controlling the bias voltage of the substrate and head during the encapsulation layer deposition process. The bias voltage is first maintained at approximately 60 volts while the standard encapsulation overcoat portion of the layer is deposited. This may take approximately one hour. Over the next thirty minutes, the bias voltage is ramped from approximately 60 volts to approximately 200 volts in a gradual, linear manner to reduce the stress on the wafer and heads. The bias voltage is then maintained at approximately 200 volts for the next three hours while the remainder of the encapsulation layer is deposited. Because of the higher bias voltage, the layer is deposited in a substantially planar manner so that there is no need for a lapping back process. Stress to the head is minimized by ramping the bias voltage. In addition, relatively short studs can be used for routing signals to and from the read/write elements of the head. The encapsulation layer is etched back in the vicinity of the studs with an NaOH/EDTA solution which produces via sidewalls with shallow angles, in the range of 20 degrees from horizontal.
    • 提供用于薄膜头的薄封装层的工艺包括在封装层沉积工艺期间控制衬底和头的偏置电压。 首先将偏置电压保持在约60伏,同时沉积该层的标准封装外涂层部分。 这可能需要大约一个小时。 在接下来的三十分钟内,偏置电压以逐渐的线性方式从大约60伏斜升到大约200伏,以减小晶片和磁头上的应力。 然后在接下来的三个小时内将偏置电压维持在约200伏,同时沉积封装层的其余部分。 由于偏置电压较高,所以该层以基本上平面的方式沉积,使得不需要回扫工艺。 通过斜坡偏置电压来减小头部的压力。 此外,可以使用相对较短的螺柱将信号路由到头部的读/写元件和/从头的读/写元件路由。 密封层在柱头附近用NaOH / EDTA溶液回蚀,NaOH / EDTA溶液通过具有较小角度的侧壁产生水平20度的范围。
    • 47. 发明申请
    • Solution-Processed Metal Selenide Semiconductor using Deposited Selenium Film
    • 使用沉积的硒膜的溶液加工的金属硒化物半导体
    • US20140134792A1
    • 2014-05-15
    • US13719052
    • 2012-12-18
    • Sean Andrew VailAlexey KoposovWei PanGary D. FoleyJong-Jan Lee
    • Sean Andrew VailAlexey KoposovWei PanGary D. FoleyJong-Jan Lee
    • H01L21/02
    • H01L21/02628H01L21/02491H01L21/02568H01L21/02614H01L31/0322Y02E10/541
    • Methods are provided for fabricating a solution-processed metal and mixed-metal selenide semiconductor using a selenium (Se) film layer. One aspect provides a conductive substrate and deposits a first Se film layer over the conductive substrate. A first solution, including a first material set of metal salts, metal complexes, or combinations thereof, is dissolved in a solvent and deposited on the first Se film layer. A first intermediate film comprising metal precursors is formed from corresponding members of the first material set. In one aspect, a plurality of intermediate films is formed using metal precursors from the first material set or a different material set. In another aspect, a second Se film layer is formed overlying the intermediate film(s). Thermal annealing is performed in an environment including hydrogen (H2), hydrogen selenide (H2Se), or Se/H2. The metal precursors are transformed in the intermediate film(s), and a metal selenide-containing semiconductor is formed.
    • 提供了使用硒(Se)膜层制造溶液处理金属和混合金属硒化物半导体的方法。 一个方面提供一种导电衬底并且在导电衬底上沉积第一Se膜层。 包括金属盐,金属络合物或其组合的第一材料组合的第一溶液溶解在溶剂中并沉积在第一Se膜层上。 包含金属前体的第一中间膜由第一材料组的相应构件形成。 在一个方面,使用来自第一材料组或不同材料组的金属前体形成多个中间膜。 在另一方面,形成覆盖中间膜的第二Se膜层。 在包括氢(H 2),硒化氢(H 2 Se)或Se / H 2的环境中进行热退火。 金属前体在中间膜中转变,形成含金属硒化物的半导体。
    • 48. 发明申请
    • Solid-State Dye-Sensitized Solar Cell Using Oxidative Dopant
    • 使用氧化掺杂剂的固态染料敏化太阳能电池
    • US20140116509A1
    • 2014-05-01
    • US13664256
    • 2012-10-30
    • Sean Andrew VailAlexey KoposovWei PanGary D. FoleyJong-Jan Lee
    • Sean Andrew VailAlexey KoposovWei PanGary D. FoleyJong-Jan Lee
    • H01L51/00H01B1/12
    • H01L51/4226H01L51/002H01L51/0058Y02E10/549
    • A solid-state hole transport composite material (ssHTM) is provided. The ssHTM is made from a neutral charge first p-type organic semiconductor, and a chemically oxidized first p-type semiconductor, where the dopants are silver(I) containing materials. A reduced form of the silver(I) containing material is also retained as functional component in the ssHTM. In one aspect, the silver(I) containing material is silver bis(trifluoromethanesulfonyl)imide (TFSI). In another aspect, the first p-type organic semiconductor is 2,2′,7,7′-tetrakis(N,N-di-p-methoxyphenylamine)-9,9′-spirobifluorene (Spiro-OMeTAD). In one variation, the ssHTM additionally includes a first p-type organic semiconductor doped with an ionic dopant such as lithium (Li+), sodium (Na+), potassium (K+), or combinations of the above-mentioned materials. Also provided are a method for synthesizing the above-described ssHTM, and a solid-state dye solar cell (ssDSC) fabricated from the ssHTM.
    • 提供固态空穴传输复合材料(ssHTM)。 ssHTM由中性电荷第一p型有机半导体和化学氧化的第一p型半导体制成,其中掺杂剂是含银(I)的材料。 含有银(I)的材料的还原形式也作为ssHTM中的功能组分保留。 一方面,含有银(I)的材料是双(三氟甲磺酰)酰亚胺(TFSI)。 另一方面,第一p型有机半导体是2,2',7,7'-四(N,N-二 - 对甲氧基苯胺)-9,9'-螺二芴(Spiro-OMeTAD)。 在一个实施方案中,ssHTM还包括掺杂有离子掺杂剂如锂(Li +),钠(Na +),钾(K +)或上述材料的组合的第一p型有机半导体。 还提供了合成上述ssHTM的方法和由ssHTM制造的固态染料太阳能电池(ssDSC)。
    • 50. 发明授权
    • Multilayered barrier metal thin-films
    • 多层阻隔金属薄膜
    • US08264081B2
    • 2012-09-11
    • US11311546
    • 2005-12-19
    • Wei PanYoshi OnoDavid R. EvansSheng Teng Hsu
    • Wei PanYoshi OnoDavid R. EvansSheng Teng Hsu
    • H01L23/48H01L23/52
    • H01L21/28562H01L21/76841H01L2221/1078
    • A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.
    • 通过原子层化学气相沉积(ALCVD)将多层阻挡金属薄膜沉积在衬底上。 多层膜可以包括单个化学物质的几个不同层,或者各个不同的或交替的化学物质的几个层。 在优选实施例中,多层阻挡薄膜包括在衬底上的氮化钽层,其上沉积有氮化钛层。 整个多层膜的厚度可以是大约50埃。 当与通过常规化学气相沉积(CVD)沉积的膜相比时,该膜具有优异的膜特性,例如抗扩散能力,低电阻率,高密度和台阶覆盖。 本发明的多层阻挡金属薄膜具有改善的粘合特性,特别适用于其上的铜膜的金属化。