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41. 发明授权

US6049489A Methods using a data read latch circuit in a semiconductor device 有权
标题翻译：在半导体器件中使用数据读取锁存电路的方法
公开(公告)号：US6049489A
公开(公告)日：2000-04-11
申请号：US374663
申请日：1999-08-16
申请人： Todd A. Merritt
发明人： Todd A. Merritt
IPC分类号： G11C7/10 , G11C29/12 , G11C29/48 , G11C8/00
CPC分类号： G11C7/106 , G11C29/12 , G11C29/48 , G11C7/1006 , G11C7/103 , G11C7/1051
摘要： A method and circuit for self-latching data read lines that are used to transfer data that is read from a memory array of a memory device to a data output register of the memory device, wherein a self-latching latch circuit is connected to each data read line The latch circuits are located physically near the output of the memory array, for latching data that is read from the memory array as soon as the data is applied to the data read lines, and prior to the data being latched in the data output register, thereby minimizing the effects of propagation delay so that the memory cycle time can be decreased. In one embodiment wherein the memory is organized in a ".times.4" configuration, different groups of the data read lines are selected in alternate read cycles, and the data read lines of the non-selected data read group are equilibrated automatically during the read cycle using the conventional test circuits of the memory device.
摘要翻译：一种用于自锁存数据读取线的方法和电路，用于将从存储器件的存储器阵列读取的数据传送到存储器件的数据输出寄存器，其中自锁存锁存电路连接到每个数据读线锁存电路位于物理靠近存储器阵列的输出处，用于锁存从存储器阵列读取的数据，一旦将数据应用于数据读取线，并且在数据被锁存在数据输出之前寄存器，从而最小化传播延迟的影响，使得可以减少存储器周期时间。在其中存储器被组织成“x4”配置的一个实施例中，在备用读取周期中选择不同组的数据读取行，并且在读取周期期间自动平衡未选择的数据读取组的数据读取行存储器件的常规测试电路。

42. 发明授权

US5986916A On-chip program voltage generator for antifuse repair 失效
标题翻译：用于反熔丝维修的片上程序电压发生器
公开(公告)号：US5986916A
公开(公告)日：1999-11-16
申请号：US915341
申请日：1997-08-20
申请人： Todd A. Merritt , Kevin Duesman
发明人： Todd A. Merritt , Kevin Duesman
IPC分类号： G11C11/401 , G11C5/14 , G11C11/4074 , G11C17/16 , G11C29/04 , G11C13/00
CPC分类号： G11C5/145 , G11C11/4074 , G11C17/16
摘要： A voltage generator is provided in a DRAM to generate the appropriate voltage for programming antifuses. In one embodiment of the present invention, a high voltage charge pump is provided on a DRAM product to generate the high voltage necessary for programming antifuses. In one embodiment, the high voltage charge pump includes a plurality of transistors in series to produce a programming voltage that is some multiple of the supply voltage to the memory less.
摘要翻译：在DRAM中提供电压发生器以产生用于编程反熔丝的适当电压。在本发明的一个实施例中，高电压电荷泵设置在DRAM产品上以产生编程反熔丝所需的高电压。在一个实施例中，高电压电荷泵包括串联的多个晶体管，以产生对存储器的电源电压的几倍的编程电压。

43. 发明授权

US5790448A On-chip program voltage generator for antifuse repair 失效
标题翻译：用于反熔丝维修的片上程序电压发生器
公开(公告)号：US5790448A
公开(公告)日：1998-08-04
申请号：US742809
申请日：1996-11-01
申请人： Todd A. Merritt , Kevin Duesman
发明人： Todd A. Merritt , Kevin Duesman
IPC分类号： G11C11/401 , G11C5/14 , G11C11/4074 , G11C17/16 , G11C29/04 , G11C13/00
CPC分类号： G11C5/145 , G11C11/4074 , G11C17/16
摘要： A memory chip having an on-chip high voltage generator and charge pump.
摘要翻译：具有片上高电压发生器和电荷泵的存储芯片。

44. 发明授权

US5444408A Active pull-up voltage spike reducer 失效
标题翻译：主动上拉电压尖峰减速器
公开(公告)号：US5444408A
公开(公告)日：1995-08-22
申请号：US167262
申请日：1993-12-13
申请人： Todd A. Merritt
发明人： Todd A. Merritt
IPC分类号： G05F3/24 , H03K3/356 , H03K19/003 , H03K19/0185 , H03L5/00 , G05F1/10 , H03K3/00 , H03K19/0175
CPC分类号： G05F3/247 , G05F3/24 , H03K19/00361 , H03K19/018521 , H03K3/356026 , H03K3/356121
摘要： An embodiment of the present invention provides a method to reduce a regulated power source voltage spike during operation of a dynamic random access memory by the steps of: providing a voltage spike reducer enabling pulse via a pulse generator circuit responsive to a pulse generator input signal; translating the voltage level of an unregulated power source via a level translation stage during the presence of the voltage spike reducer enabling pulse; amplifying a translated voltage level; and providing a measure of current from the unregulated power supply to the regulated power supply via a current driver stage that is responsive to the amplified translated voltage level translation. The method is realize by in a CMOS active pull-up voltage spike reducing circuit for a semiconductor device comprising: first, second and third potentials for powering the active pull-up voltage spike reducing circuitry; a pulse generator stage responsive to a pulse generator input signal; a level translator stage responsive to an output pulse of the pulse generator circuit; a translated driver stage responsive to an output of the level translator stage; and a current driver stage responsive to said translated driver stage to thereby provide additional current to the third potential.
摘要翻译：本发明的实施例提供了一种通过以下步骤来减小动态随机存取存储器操作期间稳定的电源电压尖峰的方法：提供响应于脉冲发生器输入信号的经由脉冲发生器电路的电压尖峰减速器使能脉冲; 在存在电压尖峰减速器使能脉冲期间经由电平转换级平移未调节电源的电压电平; 放大翻译电压电平; 以及通过响应于放大的转换电压电平转换的电流驱动级，提供从未调节电源到稳压电源的电流测量。该方法通过在用于半导体器件的CMOS有源上拉电压尖峰减少电路中实现，包括：用于为有源上拉电压尖峰减少电路供电的第一，第二和第三电位; 响应于脉冲发生器输入信号的脉冲发生器级; 响应于脉冲发生器电路的输出脉冲的电平转换器级; 响应于电平转换器级的输出的翻译驱动器级; 以及响应于所述转换的驱动器级的电流驱动器级，从而向第三电位提供额外的电流。

45. 发明授权

US5331593A Read circuit for accessing dynamic random access memories (DRAMS) 失效
标题翻译：用于访问动态随机存取存储器（DRAMS）的读电路
公开(公告)号：US5331593A
公开(公告)日：1994-07-19
申请号：US25554
申请日：1993-03-03
申请人： Todd A. Merritt , Greg A. Blogett
发明人： Todd A. Merritt , Greg A. Blogett
IPC分类号： G11C7/10 , G11C11/4093 , G11C11/4096 , H03K19/00 , H03K17/08
CPC分类号： G11C7/1057 , G11C11/4093 , G11C11/4096 , G11C7/1051 , G11C7/106 , H03K19/0013
摘要： DRAM read accessing circuitry having two parallel connected control lines, one of which includes a level translator stage and the other of which includes an enable gate. Both the level translator stage and the enable gate are connected to receive 0.0 to 3 volt small logic swings from output buffer logic utilized in reading data out of the DRAM. Output signals from the level translator stage are applied to a pull up output transistor in an output driver stage, and output signals from the enable gate are connected to a pull down output transistor in the output driver stage. A feedback connection is provided between the output of the level translator stage and one input to the enable gate to ensure that the enable gate does not generate an enabling output signal for turning on the pull down output transistor until the pull up output transistor is completely turned off. Not only does this novel operation completely eliminate crossing or crossover currents in the output driver stage, but it also introduces minimum time delays in logic swings at the output node of the output driver stage.
摘要翻译： DRAM读取存取电路具有两个并联的控制线，其中一个包括电平转换器级，另一个包括一个使能门。电平转换器级和使能栅都被连接以从用于从DRAM读出数据中使用的输出缓冲器逻辑接收0.0至3伏小的逻辑摆幅。来自电平转换器级的输出信号被施加到输出驱动级中的上拉输出晶体管，并且来自使能栅极的输出信号连接到输出驱动级中的下拉输出晶体管。在电平转换器级的输出和允许栅极的一个输入之间提供反馈连接，以确保使能栅极不产生用于导通下拉输出晶体管的使能输出信号，直到上拉输出晶体管完全转向关闭这种新颖的操作不仅完全消除了输出驱动级中的交叉或交叉电流，而且还在输出驱动级的输出节点的逻辑摆幅中引入了最小的时间延迟。

46. 发明申请

US20130039132A1 LINE DRIVER CIRCUITS, METHODS, AND APPARATUSES 有权
标题翻译：线路驱动电路，方法和装置
公开(公告)号：US20130039132A1
公开(公告)日：2013-02-14
申请号：US13204994
申请日：2011-08-08
申请人： Tae H. Kim , Howard C. Kirsch , Yu-Wen Huang , Mingshiang Wang , Todd A. Merritt
发明人： Tae H. Kim , Howard C. Kirsch , Yu-Wen Huang , Mingshiang Wang , Todd A. Merritt
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C11/4085 , G11C7/18 , G11C8/08
摘要： Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed.
摘要翻译：描述的实施例涉及线路驱动器，例如用于在存储器阵列中提供减小的栅极感应漏极泄漏的线路驱动器。还公开了线路驱动器的相应的操作方法。

47. 再颁专利

USRE41441E1 Output buffer having inherently precise data masking 有权
标题翻译：具有固有精确数据掩蔽的输出缓冲器
公开(公告)号：USRE41441E1
公开(公告)日：2010-07-13
申请号：US10006785
申请日：2001-11-09
申请人： Todd A. Merritt
发明人： Todd A. Merritt
IPC分类号： G06F12/00 , G06F13/00 , G06F5/00 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1009 , G11C7/1051 , G11C7/1057
摘要： A maskable data output buffer includes an output stage receiving data signals from a data coder. The signals output from the data coder are normally complementary data signals corresponding to complementary data input signals. However, in response to receiving a mask signal, the data coder forces the output signals to be other than complementary. The output stage normally generates a data output signal corresponding to the complementary data input signals. However, when the data input signals are other than complementary, the output of the output stage assumes a high impedance condition. Since the timing of the high impedance condition is determined from the data signals themselves, the timing of the mask operation is inherently properly timed to the output of the data from the data output buffer.
摘要翻译：可屏蔽数据输出缓冲器包括从数据编码器接收数据信号的输出级。从数据编码器输出的信号通常是对应于互补数据输入信号的互补数据信号。然而，响应于接收到掩码信号，数据编码器迫使输出信号不是互补的。输出级通常产生对应于互补数据输入信号的数据输出信号。然而，当数据输入信号不是互补时，输出级的输出呈现高阻抗状态。由于高阻抗条件的定时是从数据信号本身确定的，所以掩蔽操作的定时固有地适当地定时到来自数据输出缓冲器的数据的输出。

48. 发明授权

US07681005B1 Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation 失效
公开(公告)号：US07681005B1
公开(公告)日：2010-03-16
申请号：US08650719
申请日：1996-05-20
申请人： Jeffrey S. Mailloux , Kevin J. Ryan , Todd A. Merritt , Brett L. Williams
发明人： Jeffrey S. Mailloux , Kevin J. Ryan , Todd A. Merritt , Brett L. Williams
IPC分类号： G06F13/00
CPC分类号： G11C7/1027 , G11C7/1015 , G11C7/1024 , G11C7/1039 , G11C7/1045 , G11C7/20
摘要： An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs. Additionally, a DRAM is provided having both pipelined and burst Extended Data Out modes of operation and the ability to switch between them.

49. 发明授权

US07376025B2 Method and apparatus for semiconductor device repair with reduced number of programmable elements 有权
标题翻译：减少可编程元件数量的半导体器件修复方法和装置
公开(公告)号：US07376025B2
公开(公告)日：2008-05-20
申请号：US11340886
申请日：2006-01-27
申请人： Todd A. Merritt , Timothy B. Cowles , Vikram K. Bollu
发明人： Todd A. Merritt , Timothy B. Cowles , Vikram K. Bollu
IPC分类号： G11C7/00
CPC分类号： G11C29/806 , G11C29/81
摘要： An apparatus and method using a reduced number of fuses for enabling redundant memory blocks in a semiconductor memory is disclosed. In one embodiment, a redundancy selection module may be configured using selection fuses, wherein each selection fuse selects a pair of repair modules. In another embodiment, a redundancy selection module may be configured using selection fuses, wherein each selection fuse may select a power of two (i.e., 1, 2, 4, 8, etc.) number of repair modules. Each repair module includes fuses programmed with a selected address, such that the repair module may respond when an address input matches the selected address. However, the Least Significant Bit (LSB) is uninvolved in the address programming. Instead, the LSB is compared to the values of the selection fuses. As a result, repair modules select a redundant memory block based on a combination of the selected address comparison and the separate LSB comparison.
摘要翻译：公开了一种使用减少数量的保险丝来实现半导体存储器中的冗余存储块的装置和方法。在一个实施例中，可以使用选择熔丝配置冗余选择模块，其中每个选择熔丝选择一对修复模块。在另一个实施例中，冗余选择模块可以使用选择熔丝来配置，其中每个选择熔丝可以选择两个（即1,2,4,8等）数量的修复模块的功率。每个修理模块包括用所选地址编程的保险丝，使得当地址输入与选择的地址匹配时，修复模块可以响应。但是，最低有效位（LSB）不涉及地址编程。而是将LSB与选择保险丝的值进行比较。因此，修复模块基于所选地址比较和单独的LSB比较的组合来选择冗余存储块。

50. 发明授权

US06750695B2 Voltage pump and a level translator circuit 失效
标题翻译：电压泵和电平转换电路
公开(公告)号：US06750695B2
公开(公告)日：2004-06-15
申请号：US10338191
申请日：2003-01-07
申请人： Greg A. Blodgett , Todd A. Merritt
发明人： Greg A. Blodgett , Todd A. Merritt
IPC分类号： H03L500
CPC分类号： G11C5/145 , H02M3/07 , H02M3/073
摘要： A voltage pump and method of driving a node to an increased potential. A periodic input signal is fed into a precharged small capacitor to create a level shifted periodic intermediate potential at an intermediate node. The intermediate node is a supply node to a level translator circuit. The output of the level translator circuit controls the actuation of a pass transistor. When actuated the pass transistor drives a boosted potential to an output node of the voltage pump circuit. In one embodiment the level translator circuit has a delay element which maintains the deactivation of a pull down portion of the level translator circuit until a pull up portion of the level translator circuit is deactivated. A first diode clamp is used to limit the output of the level translator circuit and the boosted potential to within 1 threshold voltage (of the diode clamp) of each other. A second diode clamp is connected between the terminals of the pass transistor so that the boosted potential does not need to climb above the output potential plus a Vt of the second diode clamp. This in turn limits the gate potential of the transistor through the first diode clamp. In a further embodiment a precharge circuit precharges the first terminal of the transistor to a potential equal to the intermediate potential minus a threshold voltage of the precharge circuit.
摘要翻译：一种电压泵和将节点驱动到增加电位的方法。周期性输入信号被馈送到预充电的小电容器中以在中间节点处产生电平移位的周期性中间电位。中间节点是电平转换器电路的电源节点。电平转换器电路的输出控制传输晶体管的致动。当致动时，通过晶体管将升压电位驱动到电压泵电路的输出节点。在一个实施例中，电平转换器电路具有延迟元件，其维持电平转换器电路的下拉部分的去激活，直到电平转换器电路的上拉部分被去激活。第一个二极管钳位用于将电平转换器电路的输出和升压电位限制在彼此的二极管钳位电压的1阈值以内。第二个二极管钳位连接在传输晶体管的端子之间，使得升压电位不需要爬升到高于输出电位加上第二二极管钳位的Vt。这又通过第一个二极管钳位来限制晶体管的栅极电位。在另一实施例中，预充电电路将晶体管的第一端子预充电到等于中间电位的电位减去预充电电路的阈值电压。

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