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41. 发明授权

US07222244B2 Semiconductor device including a prediction circuit to control a power status control circuit which controls the power status of a function circuit 有权
标题翻译：半导体器件包括用于控制功率状态控制电路的预测电路，其控制功能电路的电源状态
公开(公告)号：US07222244B2
公开(公告)日：2007-05-22
申请号：US09932099
申请日：2001-08-20
申请人： Takayuki Kawahara , Takehiro Shimizu , Fumio Arakawa , Hiroyuki Mizuno , Takao Watanabe , Koichiro Ishibashi
发明人： Takayuki Kawahara , Takehiro Shimizu , Fumio Arakawa , Hiroyuki Mizuno , Takao Watanabe , Koichiro Ishibashi
IPC分类号： G06F1/32
CPC分类号： H03K19/0016 , H03K19/1735
摘要： A semiconductor device having a functional circuit block with predictive power controller is provided so as to construct a system LSI manufactured in a practicable number of design steps, which is extensible and in which power is reduced. The functional circuit block includes a prediction circuit and a predictive power shutdown circuit having a power status control circuit. The prediction circuit controls a power status of the functional circuit block by using the power status control circuit, based on input information thereto. When no information is inputted for a predetermined a period of time, the power status control circuit shifts from a power status of the functional circuit block to a low-power status.
摘要翻译：提供具有预测功率控制器的具有功能电路块的半导体器件，以便构建以可实施的数量的设计步骤制造的系统LSI，其是可扩展的并且功率减小。功能电路块包括具有电源状态控制电路的预测电路和预测功率关断电路。预测电路根据其输入信息，通过使用电源状态控制电路来控制功能电路块的电源状态。当在预定的一段时间内没有输入信息时，电源状态控制电路从功能电路块的电源状态转换为低功率状态。

42. 发明申请

US20060198183A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20060198183A1
公开(公告)日：2006-09-07
申请号：US11337648
申请日：2006-01-24
申请人： Takayuki Kawahara , Kenichi Osada , Riichiro Takemura
发明人： Takayuki Kawahara , Kenichi Osada , Riichiro Takemura
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C13/0004 , G11C29/50016 , G11C2213/79
摘要： With a semiconductor device using a phase change material, in particular, an increase in the number of circuit elements associated with a testing function is checked to the minimum, and an easier test on the semiconductor device is implemented. When a retention test and so forth are conducted on a phase change element, for example, a generated voltage VS1 of a set bit-line voltage power supply, VG_set, provided originally for use in a set operation, is used as a voltage to be applied to the phase change element, and timing when the voltage VS1 is applied to the phase change element is generated by a read/test timing generation circuit TG_rd_test, provided originally to execute a read operation of the phase change element. By so doing, it becomes possible to check an increase in the number of circuit elements, and to conduct the retention test accelerated on a voltage basis with ease.
摘要翻译：对于使用相变材料的半导体器件，特别地，将与测试功能相关联的电路元件的数量的增加最小化，并且实现对半导体器件的更容易的测试。当在相变元件上进行保持测试等时，例如，原来用于设定操作的设定位线电压电源VG_set的发电电压VS 1被用作电压应用于相变元件，并且通过最初为执行相变元件的读取操作而提供的读取/测试定时产生电路TG_rd_test产生电压VS1施加到相变元件的定时。通过这样做，可以检查电路元件的数量的增加，并且容易地在基于电压的基础上进行加速的保持测试。

43. 发明申请

US20060062055A1 Semiconductor memory 失效
公开(公告)号：US20060062055A1
公开(公告)日：2006-03-23
申请号：US11268471
申请日：2005-11-08
申请人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
发明人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C5/025 , G11C7/02 , G11C7/1006 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C11/405 , G11C11/4096 , G11C2207/107
摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

44. 发明授权

US06970391B2 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions 失效
标题翻译：内置电源的半导体器件用于补偿工作条件和制造工艺条件的偏差
公开(公告)号：US06970391B2
公开(公告)日：2005-11-29
申请号：US10441207
申请日：2003-05-20
申请人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
发明人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
IPC分类号： G11C5/14 , G11C7/00 , G11C7/12 , G11C8/00 , G11C8/10 , G11C11/4094 , H03K5/08 , H03K17/00 , H03K17/693 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0944 , G11C7/04 , G11C7/02 , G11C11/34
CPC分类号： G11C7/12 , G11C5/14 , G11C5/147 , G11C8/10 , G11C11/4094 , G11C11/413 , H03K5/08 , H03K17/693 , H03K19/00376 , H03K19/00384 , H03K19/017 , H03K19/01707 , H03K19/017518 , H03K19/09448 , H03K2217/0036
摘要： A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.
摘要翻译：半导体集成电路包括半导体芯片，设置在半导体芯片上用于接收来自外部电源的电压的电源端子，设置在半导体芯片上的内部电路，设置在半导体芯片上的电源电路，用于将从所述电源端子接收用于向所述内部电路提供由所述电压变换产生的源极电压的外部电源电压;以及控制电路，设置在所述半导体芯片上用于控制所述电源电路，其中，所述控制电路包括外部电源电压检测装置和/或温度检测装置，通过改变对内部电路的电源电压来响应来自外部电源电压检测装置和/或温度检测装置的信号，从而将内部电路的操作速度保持为不变。

45. 发明授权

US06894912B2 Semiconductor memory 失效
公开(公告)号：US06894912B2
公开(公告)日：2005-05-17
申请号：US10760402
申请日：2004-01-21
申请人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
发明人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/404 , G11C11/409 , G11C11/4096 , G11C15/00 , G11C8/00
CPC分类号： G11C7/1051 , G11C5/025 , G11C7/02 , G11C7/1006 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C11/405 , G11C11/4096 , G11C2207/107
摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

46. 发明授权

US06721194B2 Semiconductor memory 有权
公开(公告)号：US06721194B2
公开(公告)日：2004-04-13
申请号：US10287678
申请日：2002-11-05
申请人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
发明人： Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata , Kazushige Ayukawa , Takayuki Kawahara
IPC分类号： G11C1500
CPC分类号： G11C7/1051 , G11C5/025 , G11C7/02 , G11C7/1006 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C11/405 , G11C11/4096 , G11C2207/107
摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

47. 发明授权

US06504402B2 Semiconductor integrated circuit device having power reduction mechanism 失效
公开(公告)号：US06504402B2
公开(公告)日：2003-01-07
申请号：US10051013
申请日：2002-01-22
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： H03K19094
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H01L27/0218 , H03K3/356113 , H03K19/0013 , H03K19/0016 , H03K19/01721
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

48. 发明授权

US06496418B2 Semiconductor integrated circuit and data processing system 失效
公开(公告)号：US06496418B2
公开(公告)日：2002-12-17
申请号：US09985188
申请日：2001-11-01
申请人： Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
发明人： Takayuki Kawahara , Hiroshi Sato , Atsushi Nozoe , Keiichi Yoshida , Satoshi Noda , Shoji Kubono , Hiroaki Kotani , Katsutaka Kimura
IPC分类号： G11C1134
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C29/00 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.

49. 发明授权

US06404239B1 Semiconductor integrated circuit device having power reduction mechanism 失效
标题翻译：具有功率降低机构的半导体集成电路装置
公开(公告)号：US06404239B1
公开(公告)日：2002-06-11
申请号：US09613594
申请日：2000-07-10
申请人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
发明人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
IPC分类号： H03K1920
CPC分类号： H03K3/356113 , H01L27/0218 , H03K19/0016
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译：半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。逻辑门连接到第一电势点和第二电位点。半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值逻辑门。该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

50. 发明授权

US06222763B1 Nonvolatile semiconductor memory and read method 有权
公开(公告)号：US06222763B1
公开(公告)日：2001-04-24
申请号：US09497212
申请日：2000-02-03
申请人： Hiroshi Sato , Shoji Kubono , Toshinori Harada , Takayuki Kawahara , Naoki Miyamoto
发明人： Hiroshi Sato , Shoji Kubono , Toshinori Harada , Takayuki Kawahara , Naoki Miyamoto
IPC分类号： G11C1134
CPC分类号： G11C11/5621 , G11C7/1048 , G11C11/5642 , G11C2211/5642
摘要： In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.

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