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41. 发明申请

US20120261793A1 ELECTRICAL FUSE AND METHOD OF MAKING THE SAME 有权
标题翻译：电保险丝及其制造方法
公开(公告)号：US20120261793A1
公开(公告)日：2012-10-18
申请号：US13085568
申请日：2011-04-13
申请人： Chih-Chao Yang , Stephen M. Gates , Baozhen Li , Daniel C. Edelstein
发明人： Chih-Chao Yang , Stephen M. Gates , Baozhen Li , Daniel C. Edelstein
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An improved electrical-fuse (e-fuse) device including a dielectric layer having a first top surface, two conductive features embedded in the dielectric layer and a fuse element. Each conductive feature has a second top surface and a metal cap directly on the second top surface. Each metal cap has a third top surface that is above the first top surface of the dielectric layer. The fuse element is on the third top surface of each metal cap and on the first top surface of the dielectric layer. A method of forming the e-fuse device is also provided.
摘要翻译：一种改进的电熔丝（e-fuse）装置，包括具有第一顶表面的电介质层，嵌入介质层中的两个导电特征和熔丝元件。每个导电特征具有第二顶表面和直接在第二顶表面上的金属帽。每个金属盖具有在介电层的第一顶表面之上的第三顶表面。熔丝元件位于每个金属盖的第三顶表面上，并位于介质层的第一顶表面上。还提供了形成电熔丝装置的方法。

42. 发明授权

US07955968B2 Pseudo hybrid structure for low K interconnect integration 有权
标题翻译：用于低K互连集成的伪混合结构
公开(公告)号：US07955968B2
公开(公告)日：2011-06-07
申请号：US12399372
申请日：2009-03-06
申请人： Pak K. Leung , Terry G. Sparks , David V. Horak , Stephen M. Gates
发明人： Pak K. Leung , Terry G. Sparks , David V. Horak , Stephen M. Gates
IPC分类号： H01L21/4763
CPC分类号： H01L21/76828 , H01L21/76808 , H01L21/76814 , H01L21/76825 , H01L21/76835 , H01L2221/1036 , Y10T29/49224
摘要： A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK material, selectively etching a via opening (62) and trench opening (72) with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer (51) and the underlying cured via layer (43), and then curing the second trench layer (83) before forming an interconnect structure (91) by filling the trench opening (72) and via opening (62) with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.
摘要翻译：描述了通过沉积和固化超低介电常数（ULK）材料的第一通孔层（43）来制造超低k互连结构的方法和装置，沉积相同ULK材料的第二未固化沟槽层（51）通过使用来自未固化沟槽层（51）和下面的固化通孔层（43）之间的化学差异的沟槽蚀刻终点信号的双镶嵌蚀刻工艺来选择性地蚀刻通孔开口（62）和沟槽开口（72）然后在通过用互连材料填充沟槽开口（72）和通孔开口（62）形成互连结构（91）之前固化第二沟槽层（83），使得不存在附加的界面或更高的介电常数材料留下。

43. 发明申请

US20080277796A1 ELECTRONIC STRUCTURES UTILIZING ETCH RESISTANT BORON AND PHOSPHORUS MATERIALS AND METHODS TO FORM SAME 有权
标题翻译：使用耐蚀性硼和磷光体材料的电子结构及其形成方法
公开(公告)号：US20080277796A1
公开(公告)日：2008-11-13
申请号：US12180010
申请日：2008-07-25
申请人： Stephen M. Gates , Robert D. Miller
发明人： Stephen M. Gates , Robert D. Miller
IPC分类号： H01L23/48 , H01L21/31
CPC分类号： H01L21/02112 , H01L21/02205 , H01L21/31116 , H01L21/31144 , H01L21/31604 , H01L21/318 , H01L21/3212 , H01L21/76807 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A dense boron-based or phosphorus-based dielectric material is provided. Specifically, the present invention provides a dense boron-based dielectric material comprised of boron and at least one of carbon, nitrogen, and hydrogen or a dense phosphorus-based dielectric comprised of phosphorus and nitrogen. The present invention also provides electronic structures containing the dense boron-based or phosphorus-based dielectric as an etch stop, a dielectric Cu capping material, a CMP stop layer, and/or a reactive ion etching mask in a ULSI back-end-of-the-line (BEOL) interconnect structure. A method of forming the inventive boron-based or phosphorus-based dielectric as well as the electronic structure containing the same are also described in the present invention.
摘要翻译：提供了一种致密的硼基或磷基介电材料。具体地说，本发明提供由硼和碳，氮和氢中的至少一种构成的致密的硼基介电材料或由磷和氮组成的致密的磷基电介质。本发明还提供了电子结构，其包含致密的硼基或磷基电介质作为蚀刻停止层，电介质铜封盖材料，CMP停止层和/或ULSI后端的反应离子蚀刻掩模（BEOL）互连结构。在本发明中还描述了形成本发明的硼基或磷基电介质的方法以及含有它们的电子结构。

44. 发明申请

US20070249156A1 METHOD FOR ENABLING HARD MASK FREE INTEGRATION OF ULTRA LOW-K MATERIALS AND STRUCTURES PRODUCED THEREBY 审中-公开
标题翻译：用于实现超低K材料和生产的结构的硬掩模自由集成的方法
公开(公告)号：US20070249156A1
公开(公告)日：2007-10-25
申请号：US11672608
申请日：2007-02-08
申请人： Griselda Bonilla , Stephen M. Gates , Shom Ponoth , Satyanarayana V. Nitta , Sampath Purushothaman
发明人： Griselda Bonilla , Stephen M. Gates , Shom Ponoth , Satyanarayana V. Nitta , Sampath Purushothaman
IPC分类号： H01L21/4763
CPC分类号： H01L21/76826 , H01L21/02074 , H01L21/3105 , H01L21/31058 , H01L21/76883
摘要： A method is described for the repair of process induced damage sustained by low-k organosilicate dielectrics as a result of reactive ion etch, resist strip, wet clean and CMP operations in a hard mask free integration of these dielectrics into microelectronic interconnect structures incorporating a dielectric cap which is an etch stop and barrier layer. In situ reaction of the damaged regions with a suitable silylation agent just prior to a passivation barrier cap deposition is proposed as the most efficacious means to repair all the damage sustained by the dielectric. Variations of this method which include ex situ rather than in situ silylation are also described for use with hard mask free integration with selective barrier caps.
摘要翻译：描述了一种用于修复由低k有机硅酸盐电介质持续的过程诱导的损伤作为反应离子蚀刻，抗蚀剂条，湿清洁和CMP操作在将这些电介质纳入包含电介质的微电子互连结构的硬掩模中的CMP操作的方法盖是蚀刻停止层和阻挡层。在钝化阻挡层沉积之前，损伤区域与合适的甲硅烷基化剂的原位反应被提出作为修复由电介质所承受的所有损伤的最有效手段。还描述了包括异位原位甲硅烷基化的这种方法的变化，用于与选择性屏障帽的硬掩模自由积分。

45. 发明授权

US06897650B2 Magnetic-field sensor device 有权
标题翻译：磁场传感器装置
公开(公告)号：US06897650B2
公开(公告)日：2005-05-24
申请号：US10073755
申请日：2002-02-11
申请人： Charles T. Black , Stephen M. Gates , Christopher B. Murray , Robert L. Sandstrom
发明人： Charles T. Black , Stephen M. Gates , Christopher B. Murray , Robert L. Sandstrom
IPC分类号： G01R33/09 , G01R33/02 , G11B5/66
CPC分类号： B82Y25/00 , G01R33/093 , Y10T29/49032 , Y10T29/49069 , Y10T29/49155 , Y10T428/25 , Y10T428/265
摘要： A magnetic-field sensor device comprises at least two electrodes; an insulating layer separating the at least two electrodes; at least one layer of chemically-synthesized magnetic nanoparticles disposed at or above a level with the insulating layer, and disposed between the at least two electrodes; and an organic spacer surrounding each of the chemically-synthesized magnetic nanoparticles. A deviation between diameters of different ones of the nanoparticles is less than 15%. Moreover, the chemically-synthesized magnetic nanoparticles range in size between 2 nm and 20 nm in diameter.
摘要翻译：磁场传感器装置包括至少两个电极; 分离所述至少两个电极的绝缘层; 至少一层化学合成的磁性纳米颗粒设置在与绝缘层的水平面上或之上，并且设置在至少两个电极之间; 以及围绕每个化学合成的磁性纳米颗粒的有机间隔物。不同纳米颗粒的直径之间的偏差小于15％。此外，化学合成的磁性纳米粒子的尺寸范围在2nm和20nm之间。

46. 发明授权

US06803660B1 Patterning layers comprised of spin-on ceramic films 有权
标题翻译：图案层由旋涂陶瓷膜组成
公开(公告)号：US06803660B1
公开(公告)日：2004-10-12
申请号：US10627790
申请日：2003-07-25
申请人： Stephen M. Gates , Jeffrey C. Hedrick , Elbert E. Huang , Dirk Pfeiffer
发明人： Stephen M. Gates , Jeffrey C. Hedrick , Elbert E. Huang , Dirk Pfeiffer
IPC分类号： H01L2348
CPC分类号： H01L21/02126 , H01L21/02222 , H01L21/02282 , H01L21/31144 , H01L21/3121 , H01L21/3122 , H01L21/3125 , H01L21/316 , Y10S430/146 , Y10T428/31663
摘要： The present invention comprises a method for forming a hardmask including the steps of depositing a polymeric preceramic precursor film atop a substrate; converting the polymeric preceramic precursor film into at least one ceramic layer, where the ceramic layer has a composition of SivNwCxOyHz where 0.1≦v≦0.9, 0≦w≦0.5, 0.05≦x≦0.9, 0≦y≦0.5, 0.05≦z≦0.8 for v+w+x+y+z=1; forming a patterned photoresist atop the ceramic layer; patterning the ceramic layer to expose regions of the underlying substrate, where a remaining region of the underlying substrate is protected by the patterned ceramic layer; and etching the exposed region of the underlying substrate. Another aspect of the present invention is a buried etch stop layer having a composition of SivNwCxOyHz where 0.05
摘要翻译：本发明包括一种用于形成硬掩模的方法，包括以下步骤：在基底顶上沉积聚合物预陶瓷前体膜; 将聚合物前陶瓷前体膜转化为至少一个陶瓷层，其中陶瓷层具有SivNwCxOyHh的组成，其中0.1≤v≤0.9,0≤w≤0.5,0.05≤x≤0.9,0≤ 对于v + w + x + y + z = 1，y <= 0.5,0.05 <= z <= 0.8; 在陶瓷层顶部形成图案化的光刻胶; 图案化陶瓷层以暴露下面的衬底的区域，其中下面的衬底的剩余区域被图案化的陶瓷层保护; 并蚀刻下面的衬底的暴露区域。本发明的另一方面是具有SivNwCxOyHz组成的掩埋蚀刻停止层，其中0.05≤v≤0.8,0

47. 发明授权

US6162532A Magnetic storage medium formed of nanoparticles 失效
标题翻译：由纳米颗粒形成的磁存储介质
公开(公告)号：US6162532A
公开(公告)日：2000-12-19
申请号：US127453
申请日：1998-07-31
申请人： Charles T. Black , Stephen M. Gates , Christopher B. Murray , Shouheng Sun
发明人： Charles T. Black , Stephen M. Gates , Christopher B. Murray , Shouheng Sun
IPC分类号： G11B5/712 , G11B5/62 , G11B5/738 , G11B5/842 , H01F1/00 , H01F1/047 , G11B5/66
CPC分类号： B82Y25/00 , G11B5/62 , H01F1/0054 , H01F1/0063 , H01F1/009 , Y10S428/90 , Y10T428/25 , Y10T428/256 , Y10T428/257
摘要： A magnetic storage medium is disclosed which is formed from a layer of substantially uniformly spaced-apart magnetic nanoparticles of substantially uniform diameter disposed upon a surface of a substrate, with a coating, preferably of abrasion-resistant material, applied to adhere the nanoparticles to the substrate and to maintain their substantially uniform spaced-apart relationship. The nanoparticles are formed from a magnetic material selected from the group consisting of elements Co, Fe, Ni, Mn, Sm, Nd, Pr, Pt, Gd, an intermetallic compound of the aforesaid elements, a binary alloy of said elements, a ternary alloy of said elements, an oxide of Fe further comprising at least one of said elements other than Fe, barium ferrite, and strontium ferrite.
摘要翻译：公开了一种磁性存储介质，其由基本上均匀间隔开的基本上均匀的直径的磁性纳米颗粒层形成，其设置在基底的表面上，涂覆有优选耐磨材料，以将纳米颗粒粘附到并保持其基本均匀的间隔关系。纳米颗粒由选自元素Co，Fe，Ni，Mn，Sm，Nd，Pr，Pt，Gd，上述元素的金属间化合物，所述元素的二元合金，三元元素所述元素的合金，Fe的氧化物还包含除Fe以外的所述元素中的至少一种，钡铁氧体和铁酸锶。

48. 发明授权

US5593249A Diverless flowline connection system 失效
标题翻译：无水流线连接系统
公开(公告)号：US5593249A
公开(公告)日：1997-01-14
申请号：US433240
申请日：1995-05-02
申请人： David S. Cox , Stephen M. Gates
发明人： David S. Cox , Stephen M. Gates
IPC分类号： E21B41/04 , E21B43/013 , F16L1/26 , F16L1/12
CPC分类号： F16L1/26 , E21B41/04 , E21B43/0135
摘要： A diverless flowline connection system for connecting a flowline to a subsea wellhead or other subsea structure. The diverless flowline connection system is used with a remotely operated vehicle. The diverless flowline connection system includes a frame assembly including clamping arms for mounting the frame assembly to the flowline. A pair of winches are mounted to the frame assembly. Each winch includes a winch line for attachment to the wellhead to which the flowline is to be connected. Each winch is independently controlled so that the lateral position of the flowline may be variously adjusted by controlling each of the winches. The diverless flowline connection system is of modular design to accommodate a wide variety of flowline diameters. The connection system can also be used to pull from the wellhead. Winch line guillotines are provided for severing the winch lines and the clamping arms release the flowline in the event of hydraulic system failure.
摘要翻译：用于将流线连接到海底井口或其他海底结构的不连续流线连接系统。无级流线连接系统与遥控车辆一起使用。不连续流线连接系统包括框架组件，该框架组件包括用于将框架组件安装到流动管线的夹持臂。一对绞车安装在框架组件上。每个绞车包括一个连接到流线连接的井口的绞车线。每个绞盘被独立地控制，使得可以通过控制每个绞盘来不同地调节流线的横向位置。不连续流线连接系统采用模块化设计，适应各种流线直径。连接系统也可用于从井口拉出。提供绞车线路断头用于切断绞车线，并且在液压系统故障的情况下夹紧臂释放流路。

49. 发明申请

US20140042628A1 STRUCTURE WITH SUB-LITHOGRAPHIC RANDOM CONDUCTORS AS A PHYSICAL UNCLONABLE FUNCTION 有权
标题翻译：具有次平面随机导体作为物理不可靠函数的结构
公开(公告)号：US20140042628A1
公开(公告)日：2014-02-13
申请号：US13570972
申请日：2012-08-09
申请人： Daniel C. Edelstein , Gregory M. Fritz , Stephen M. Gates , Dirk Pfeiffer
发明人： Daniel C. Edelstein , Gregory M. Fritz , Stephen M. Gates , Dirk Pfeiffer
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/5228 , H01L21/0332 , H01L21/32139 , H01L23/52 , H01L23/522 , H01L23/576 , H01L2924/0002 , H04L9/3278 , H04L2209/12 , H01L2924/00
摘要： A secure electronic structure including a plurality of sub-lithographic conductor features having non-repeating random shapes as a physical unclonable function (PUF) and an integrated circuit including the same are provided. Some of the conductor features of the plurality of conductor features form ohmic electrical contact to a fraction of regularly spaced array of conductors that are located above or beneath the plurality of conductor features having the non-repeating shapes, while other conductor features of the plurality of conductor features do not form ohmic electrical contact with any of the regularly spaced array of conductors. Thus, a unique signature of electrical continuity is provided which can be used as a PUF within an integrated circuit.
摘要翻译：提供一种包括具有非重复随机形状作为物理不可克隆功能（PUF）的多个亚光刻导体特征的安全电子结构以及包括该非亚光刻导体特征的集成电路。多个导体特征中的一些导体特征形成欧姆电接触到位于具有非重复形状的多个导体特征的上方或下方的规则间隔的导体阵列的一部分，而多个导体特征的其它导体特征导体特征不与任何规则间隔的导体阵列形成欧姆电接触。因此，提供了可以在集成电路内用作PUF的电连续性的唯一签名。

50. 发明授权

US08386859B2 On-chip non-volatile storage of a test-time profile for efficiency and performance control 有权
标题翻译：用于效率和性能控制的片上非易失性存储测试时间配置文件
公开(公告)号：US08386859B2
公开(公告)日：2013-02-26
申请号：US12771387
申请日：2010-04-30
申请人： Eren Kursun , Philip G. Emma , Stephen M. Gates
发明人： Eren Kursun , Philip G. Emma , Stephen M. Gates
IPC分类号： G11C29/00 , G11C7/00 , G01R31/28 , G01R27/28 , G01R31/00 , G01R31/14 , G06F11/00
CPC分类号： G06F11/3062 , G06F11/24 , G06F11/3024 , G06F11/3089
摘要： Mechanisms for controlling an operation of one or more cores on an integrated circuit chip are provided. The mechanisms retrieve, from an on-chip non-volatile memory of the integrated circuit chip, baseline chip characteristics data representing operational characteristics of the one or more cores prior to the integrated circuit chip being operational in the data processing system. Current operational characteristics data of the one or more cores are compared with the baseline chip characteristics data. Deviations of the current operational characteristics data from the baseline chip characteristics data are determined and used to determine modifications to an operation of the one or more cores. Control signals are sent to one or more on-chip management units based on the determined modifications to cause the operation of the one or more cores to be modified.
摘要翻译：提供了用于控制集成电路芯片上的一个或多个芯的操作的机构。该机制从集成电路芯片的片上非易失性存储器中检索表示集成电路芯片在数据处理系统中操作之前的一个或多个核的操作特性的基准芯片特性数据。将一个或多个核的当前操作特征数据与基线芯片特性数据进行比较。确定当前操作特性数据与基线芯片特性数据的偏差并用于确定对一个或多个芯的操作的修改。基于所确定的修改，控制信号被发送到一个或多个片上管理单元，以使得修改一个或多个核的操作。

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