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41. 发明授权

US07005703B2 Metal-oxide-semiconductor device having improved performance and reliability 有权
标题翻译：具有提高的性能和可靠性的金属氧化物半导体器件
公开(公告)号：US07005703B2
公开(公告)日：2006-02-28
申请号：US10688231
申请日：2003-10-17
申请人： Muhammed Ayman Shibib , Shuming Xu
发明人： Muhammed Ayman Shibib , Shuming Xu
IPC分类号： H01L29/94
CPC分类号： H01L29/0634 , H01L29/1083 , H01L29/402 , H01L29/407 , H01L29/4175 , H01L29/7816 , H01L29/7835
摘要： An MOS device includes a semiconductor layer comprising a substrate of a first conductivity type and a second layer of a second conductivity type formed on at least a portion of the substrate. First and second source/drain regions of the second conductivity type are formed in the second layer proximate an upper surface of the second layer, the second layer being spaced laterally from the first source/drain region. A gate is formed above the second layer proximate the upper surface of the second layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one electrically conductive trench formed in the second layer between the gate and the second source/drain region, the trench being formed proximate the upper surface of the semiconductor layer and extending substantially vertically through the second layer to the substrate. The MOS device exhibits reduced HCI effects and/or improved high-frequency performance.
摘要翻译： MOS器件包括半导体层，该半导体层包括形成在衬底的至少一部分上的第一导电类型的衬底和第二导电类型的第二层。第二导电类型的第一和第二源极/漏极区域在靠近第二层的上表面的第二层中形成，第二层与第一源极/漏极区域横向隔开。栅极形成在靠近第二层的上表面的第二层上方，并且至少部分地在第一和第二源/漏区之间。 MOS器件还包括形成在栅极和第二源极/漏极区域之间的第二层中的至少一个导电沟槽，沟槽在半导体层的上表面附近形成并且基本上垂直延伸穿过第二层到衬底。 MOS器件表现出降低的HCI效应和/或改善的高频性能。

42. 发明申请

US20060038224A1 Metal-oxide-semiconductor device having an enhanced shielding structure 有权
公开(公告)号：US20060038224A1
公开(公告)日：2006-02-23
申请号：US10920656
申请日：2004-08-18
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： H01L29/76
CPC分类号： H01L29/4175 , H01L29/407 , H01L29/66704 , H01L29/7816 , H01L29/7825 , H01L29/7835
摘要： An MOS device includes a semiconductor layer formed on a substrate, the substrate defining a horizontal plane and a vertical direction normal to the horizontal plane. First and second source/drain regions are formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A gate is formed proximate the upper surface of the semiconductor layer and disposed at least partially between the first and second source/drain regions. A first dielectric region is formed in the MOS device, the first dielectric region defining a trench extending downward from the upper surface of the semiconductor layer to a first distance into the semiconductor layer, the first dielectric region being formed between the first and second source/drain regions. The MOS device further includes a shielding structure formed primarily in the first dielectric region, at least a portion of the shielding structure being disposed adjacent a bottom wall of the first dielectric region and/or one or more sidewalls of the first dielectric region.

43. 发明授权

US06890804B1 Metal-oxide-semiconductor device formed in silicon-on-insulator 有权
标题翻译：形成在绝缘体上硅的金属氧化物半导体器件
公开(公告)号：US06890804B1
公开(公告)日：2005-05-10
申请号：US10719195
申请日：2003-11-21
申请人： Muhammed Ayman Shibib , Shuming Xu
发明人： Muhammed Ayman Shibib , Shuming Xu
IPC分类号： H01L21/336 , H01L21/84 , H01L29/417 , H01L29/76 , H01L29/78 , H01L29/786
CPC分类号： H01L29/78609 , H01L29/402 , H01L29/41741 , H01L29/66772 , H01L29/7835 , H01L29/78624 , H01L29/78645
摘要： A semiconductor device includes a substrate of a first conductivity type, an insulating layer formed on at least a portion of the substrate, and an epitaxial layer of a second conductivity type formed on at least a portion of the insulating layer. First and second source/drain regions of the second conductivity type are formed in the epitaxial layer proximate an upper surface of the epitaxial layer, the first and second source/drain regions being spaced laterally from one another. A gate is formed above the epitaxial layer proximate the upper surface of the epitaxial layer and at least partially between the first and second source/drain regions. The device further includes a first source/drain contact formed through the epitaxial layer and insulating layer, the first source/drain contact configured so as to be in direct electrical connection with the substrate, the first source/drain region and the epitaxial layer, and a second source/drain contact formed through the epitaxial layer, the second source/drain contact configured so as to be in direct electrical connection with the second source/drain region.
摘要翻译：半导体器件包括第一导电类型的衬底，形成在衬底的至少一部分上的绝缘层和形成在绝缘层的至少一部分上的第二导电类型的外延层。第二导电类型的第一和第二源极/漏极区域在接近外延层的上表面的外延层中形成，第一和第二源极/漏极区域彼此横向间隔开。栅极形成在邻近外延层的上表面的外延层的上方，并且至少部分地在第一和第二源/漏区之间。该器件还包括通过外延层和绝缘层形成的第一源极/漏极接触点，第一源极/漏极接触构造成与衬底，第一源极/漏极区域和外延层直接电连接，以及通过所述外延层形成的第二源极/漏极接触，所述第二源极/漏极接触构造成与所述第二源极/漏极区域直接电连接。

44. 发明授权

US06423987B1 Self-protect thyristor 失效
标题翻译：自保晶闸管
公开(公告)号：US06423987B1
公开(公告)日：2002-07-23
申请号：US09424367
申请日：2000-04-19
申请人： Rainer Constapel , Heinrich Sciilangenotto , Shuming Xu
发明人： Rainer Constapel , Heinrich Sciilangenotto , Shuming Xu
IPC分类号： H01L2974
CPC分类号： H01L29/7455 , H01L29/7436 , H01L29/749
摘要： With a self-protect thyristor, having a MOSFET (M1) that is connected in series with the thyristor and a second, self-controlled MOSFET (M2) between the p-base of the thyristor and the external cathode (KA), several unit cells for the thyristor are arranged parallel connected in a semiconductor wafer. The voltage at the series MOSFET (M1) functions as an indicator for the overcurrent and excess temperature, and an additional MOSFET (M4) is provided where source (region) is connected conducting to the source of the series MOSFET (M1), where drain is conductivity connected with the gate of the series MOSFET (M1) and where gate conductivity connected with the drain of the series MOSFET (M1). A resistance (Rg) is provided between the gate electrode (G1) of the series MOSFET (M1) and the gate (G) of the thyristor.
摘要翻译：具有自保护晶闸管，具有与晶闸管串联连接的MOSFET（M1）和晶闸管的p基极与外部阴极（KA）之间的第二个自控MOSFET（M2），多个单元用于晶闸管的单元被并联连接在半导体晶片中。串联MOSFET（M1）的电压用作过电流和过温的指示器，并且提供一个额外的MOSFET（M4），其中源极（区域）连接到串联MOSFET（M1）的源极，其中漏极是与串联MOSFET（M1）的栅极连接的导电性，栅极电导率与串联MOSFET（M1）的漏极连接。在串联MOSFET（M1）的栅电极（G1）和晶闸管的栅极（G）之间提供电阻（Rg）。

45. 发明授权

US11107914B2 Metal-oxide semiconductor for field-effect transistor having enhanced high-frequency performance 有权
公开(公告)号：US11107914B2
公开(公告)日：2021-08-31
申请号：US16774498
申请日：2020-01-28
申请人： Shuming Xu
发明人： Shuming Xu
IPC分类号： H01L29/78 , H01L29/66 , H01L29/51 , H01L29/423 , H01L29/40 , H01L29/10 , H01L29/08 , H01L29/06 , H01L21/265 , H01L21/762
摘要： An LDMOS device includes a doped drift region of a first conductivity type formed on an upper surface of a substrate having a second conductivity type. A body region of the second conductivity type is formed proximate an upper surface of the doped drift region. Source and drain regions of the first conductivity type are formed proximate an upper surface of the body region and doped drift region, respectively, and spaced laterally from one another. A gate is formed over the body region and between the source and drain regions. The gate is formed on a first insulating layer for electrically isolating the gate from the body region. A shielding structure is formed over at least a portion of the doped drift region on a second insulating layer. The gate and shielding structure are spaced laterally from one another to thereby reduce parasitic gate-to-drain capacitance.

46. 发明授权

US08153484B2 Metal-oxide-semiconductor device having trenched diffusion region and method of forming same 有权
标题翻译：具有沟槽扩散区域的金属氧化物半导体器件及其形成方法
公开(公告)号：US08153484B2
公开(公告)日：2012-04-10
申请号：US11999168
申请日：2007-12-04
申请人： Muhammed Ayman Shibib , Shuming Xu
发明人： Muhammed Ayman Shibib , Shuming Xu
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L21/223 , H01L21/2253 , H01L21/266 , H01L29/0653 , H01L29/0657 , H01L29/0886 , H01L29/1037 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.
摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的靠近半导体层的上表面的第二导电类型的第一和第二源极/漏极区域。第一和第二源极/漏极区域相对于彼此间隔开。至少部分地在第一和第二源极/漏极区之间形成栅极，并与半导体层电隔离。第一和第二源极/漏极区域中的至少一个被配置为具有基本上大于半导体层和给定源极/漏极区域之间的结的宽度的有效宽度。

47. 发明申请

US20120012982A1 CAPACITORS AND METHODS OF FORMING 有权
标题翻译：电容器和形成方法
公开(公告)号：US20120012982A1
公开(公告)日：2012-01-19
申请号：US13184854
申请日：2011-07-18
申请人： Jacek Korec , Shuming Xu , Jun Wang , Boyi Yang
发明人： Jacek Korec , Shuming Xu , Jun Wang , Boyi Yang
IPC分类号： H01L27/06 , H01L21/77
CPC分类号： H01L29/945 , H01L29/66181
摘要： Capacitors and methods of forming semiconductor device capacitors are disclosed. Trenches are formed to define a capacitor bottom plate in a doped upper region of a semiconductor substrate, a dielectric layer is formed conformally over the substrate within the trenches, and a polysilicon layer is formed over the dielectric layer to define a capacitor top plate. A guard ring region of opposite conductivity and peripheral recessed areas may be added to avoid electric field crowding. A central substrate of lower doping concentration may be provided to provide a resistor in series below the capacitor bottom plate. A series resistor may also be provided in a resistivity region of the polysilicon layer laterally extending from the trenched area region. Contact for the capacitor bottom plate may be made through a contact layer formed on a bottom of the substrate. A top contact may be formed laterally spaced from the trenched area by patterning laterally extended portions of one or more of the dielectric, polysilicon and top metal contact layers.
摘要翻译：公开了形成半导体器件电容器的电容器和方法。形成沟槽以在半导体衬底的掺杂上部区域中限定电容器底板，电介质层在沟槽内的衬底上共形地形成，并且在电介质层上形成多晶硅层以限定电容器顶板。可以添加相反导电性和周边凹陷区域的保护环区域，以避免电场拥挤。可以提供较低掺杂浓度的中心衬底以在电容器底板下方串联提供串联的电阻器。也可以在从沟槽区域侧向延伸的多晶硅层的电阻率区域中提供串联电阻器。电容器底板的接触可以通过形成在基板的底部上的接触层制成。可以通过对电介质，多晶硅和顶部金属接触层中的一个或多个的横向延伸部分进行图案来形成顶部接触件与沟槽区域横向间隔开。

48. 发明申请

US20090267145A1 MOSFET DEVICE HAVING DUAL INTERLEVEL DIELECTRIC THICKNESS AND METHOD OF MAKING SAME 审中-公开
标题翻译：具有双重交互电导厚度的MOSFET器件及其制造方法
公开(公告)号：US20090267145A1
公开(公告)日：2009-10-29
申请号：US12108045
申请日：2008-04-23
申请人： Charles Walter Pearce , Simon J. Molloy , Shuming Xu , Xiao Rui Li
发明人： Charles Walter Pearce , Simon J. Molloy , Shuming Xu , Xiao Rui Li
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/402 , H01L29/66659 , H01L29/7835
摘要： A method of forming a metal-oxide-semiconductor (MOS) device includes the following steps: forming a semiconductor layer of a first conductivity type having source and drain regions of a second conductivity type, a channel region and a lightly-doped drain region formed therein; forming a gate over the channel region proximate an upper surface of the semiconductor layer; after the forming steps, depositing a first dielectric layer having a first thickness over an upper surface of the semiconductor layer; etching the first dielectric layer in a region over the lightly-doped drain proximate to the gate to reduce its thickness; conformably depositing a second dielectric layer having a second thickness over the first dielectric layer, including in the etched region, the second thickness being less than the first thickness; and forming a shielding electrode over the second dielectric layer.
摘要翻译：形成金属氧化物半导体（MOS）器件的方法包括以下步骤：形成第一导电类型的半导体层，其具有第二导电类型的源极和漏极区域，沟道区域和形成的轻掺杂漏极区域其中在靠近半导体层的上表面的沟道区上形成栅极; 在形成步骤之后，在半导体层的上表面上沉积具有第一厚度的第一介电层; 在靠近栅极的轻掺杂漏极上的区域中蚀刻第一介电层以减小其厚度; 在所述第一介电层上沉积具有第二厚度的第二介电层，所述第二介电层包括在所述蚀刻区域中，所述第二厚度小于所述第一厚度; 以及在所述第二电介质层上形成屏蔽电极。

49. 发明授权

US07446375B2 Quasi-vertical LDMOS device having closed cell layout 有权
标题翻译：具有闭孔布局的准垂直LDMOS器件
公开(公告)号：US07446375B2
公开(公告)日：2008-11-04
申请号：US11376470
申请日：2006-03-14
申请人： Shuming Xu , Jacek Korec
发明人： Shuming Xu , Jacek Korec
IPC分类号： H01L29/76 , H01L31/62
CPC分类号： H01L29/7816 , H01L29/0692 , H01L29/0878 , H01L29/0886 , H01L29/1045 , H01L29/4175 , H01L29/4238 , H01L29/7802 , H01L29/7835
摘要： A low voltage power device includes a plurality of quasi-vertical LDMOS device cells. A conductive trench sinker is formed through the epitaxial layer and adjacent a selected one of the source and drain regions in each cell. The trench sinker electrically couples the selected one of the source and drain regions to the substrate for coupling current from the channel to the substrate. The resulting device exhibits a vertical current flow between the metal electrode covering the front surface and the second electrode formed at the back side of the wafer. The device cells are arranged in a closed cell configuration.
摘要翻译：低压功率器件包括多个准垂直LDMOS器件单元。导电沟槽沉积片通过外延层形成并且与每个单元中的源极和漏极区域中的一个相邻。沟槽沉积片将所选择的源极和漏极区之一电耦合到衬底，以将电流从沟道耦合到衬底。所得到的器件在覆盖前表面的金属电极和形成在晶片背面的第二电极之间呈现垂直的电流。设备单元被布置成闭孔配置。

50. 发明申请

US20080246086A1 SEMICONDUCTOR DEVICES HAVING CHARGE BALANCED STRUCTURE 有权
标题翻译：具有电荷平衡结构的半导体器件
公开(公告)号：US20080246086A1
公开(公告)日：2008-10-09
申请号：US12139984
申请日：2008-06-16
申请人： Jacek Korec , Shuming Xu , Christopher Boguslaw Kocon
发明人： Jacek Korec , Shuming Xu , Christopher Boguslaw Kocon
IPC分类号： H01L27/06
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4933 , H01L29/7811 , H01L29/7816 , H01L29/7823
摘要： A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.
摘要翻译：横向扩散的金属氧化物半导体晶体管器件包括具有在衬底上形成的半导体层的第一导电类型的衬底。在半导体层中形成第一导电类型的源极区域和漏极延伸区域。在半导体层中形成第二导电类型的体区。导电栅极形成在沟道区域上形成的栅极电介质层上。漏极接触将漏极延伸区域电连接到衬底并且与沟道区域横向间隔开。漏极接触包括形成在半导体层中的衬底和漏极延伸区域之间的高掺杂漏极接触区域，其中高掺杂漏极接触区域的最高部分与半导体层的上表面间隔开。源极触点将源极区域电连接到主体区域。

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