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1. 发明授权

US08614480B2 Power MOSFET with integrated gate resistor and diode-connected MOSFET 有权
标题翻译：功率MOSFET集成栅极电阻和二极管连接的MOSFET
公开(公告)号：US08614480B2
公开(公告)日：2013-12-24
申请号：US13540862
申请日：2012-07-03
申请人： Jun Wang , Shuming Xu , Jacek Korec
发明人： Jun Wang , Shuming Xu , Jacek Korec
IPC分类号： H01L29/66
CPC分类号： H01L27/0629 , H01L27/0727 , H01L29/1083 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/456 , H01L29/66659 , H01L29/7835 , H01L29/861
摘要： A power MOSFET is formed in a semiconductor device with a parallel combination of a shunt resistor and a diode-connected MOSFET between a gate input node of the semiconductor device and a gate of the power MOSFET. A gate of the diode-connected MOSFET is connected to the gate of the power MOSFET. Source and drain nodes of the diode-connected MOSFET are connected to a source node of the power MOSFET through diodes. The drain node of the diode-connected MOSFET is connected to the gate input node of the semiconductor device. The source node of the diode-connected MOSFET is connected to the gate of the power MOSFET. The power MOSFET and the diode-connected MOSFET are integrated into the substrate of the semiconductor device so that the diode-connected MOSFET source and drain nodes are electrically isolated from the power MOSFET source node through a pn junction.
摘要翻译：在半导体器件的栅极输入节点和功率MOSFET的栅极之间，在半导体器件中形成并联组合的分流电阻器和二极管连接的MOSFET的功率MOSFET。二极管连接的MOSFET的栅极连接到功率MOSFET的栅极。二极管连接的MOSFET的源极和漏极节点通过二极管连接到功率MOSFET的源极节点。二极管连接的MOSFET的漏极节点连接到半导体器件的栅极输入节点。二极管连接的MOSFET的源节点连接到功率MOSFET的栅极。功率MOSFET和二极管连接的MOSFET集成到半导体器件的衬底中，使得二极管连接的MOSFET源极和漏极节点通过pn结与功率MOSFET源节点电隔离。

2. 发明授权

US07589378B2 Power LDMOS transistor 有权
标题翻译：电源LDMOS晶体管
公开(公告)号：US07589378B2
公开(公告)日：2009-09-15
申请号：US11676613
申请日：2007-02-20
申请人： Christopher Boguslaw Kocon , Shuming Xu , Jacek Korec
发明人： Christopher Boguslaw Kocon , Shuming Xu , Jacek Korec
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4933 , H01L29/7802 , H01L29/7816 , H01L29/7823
摘要： A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.
摘要翻译：横向扩散的金属氧化物半导体晶体管器件包括具有在衬底上形成的半导体层的第一导电类型的衬底。在半导体层中形成第一导电类型的源极区域和漏极延伸区域。在半导体层中形成第二导电类型的体区。导电栅极形成在沟道区域上形成的栅极电介质层上。漏极接触将漏极延伸区域电连接到衬底并且与沟道区域横向间隔开。漏极接触包括形成在半导体层中的衬底和漏极延伸区域之间的高掺杂漏极接触区域，其中高掺杂漏极接触区域的最高部分与半导体层的上表面间隔开。源极触点将源极区域电连接到主体区域。

3. 发明申请

US20080054994A1 Dual-Gate Metal-Oxide-Semiconductor Device 失效
标题翻译：双栅极金属氧化物半导体器件
公开(公告)号：US20080054994A1
公开(公告)日：2008-03-06
申请号：US11927950
申请日：2007-10-30
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： G05F1/10 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7835 , H01L29/402 , H01L29/7831
摘要： An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A non-uniformly doped channel region of the first conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on the upper surface of the semiconductor layer. A first gate is formed on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region, and at least a second gate formed on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region. The second gate has a length which is substantially greater than a length of the first gate, the first and second gates being electrically isolated from one another.
摘要翻译： MOS器件包括在半导体层的上表面附近形成在第二导电类型的半导体层中的第一导电类型的第一和第二源极/漏极区域，第一和第二源极/漏极区域相对于彼此间隔开。第一导电类型的非均匀掺杂沟道区形成在靠近半导体层的上表面的半导体层中，并且至少部分地在第一和第二源/漏区之间。绝缘层形成在半导体层的上表面上。至少部分地在第一和第二源极/漏极区域之间并且在沟道区域的至少一部分上方形成第一栅极，并且至少在绝缘层上形成的至少一部分第二栅极并且在第一栅极和第二源极/漏极区域之间。第二栅极的长度远大于第一栅极的长度，第一栅极和第二栅极彼此电隔离。

4. 发明授权

US07297606B2 Metal-oxide-semiconductor device including a buried lightly-doped drain region 有权
标题翻译：金属氧化物半导体器件包括埋入的轻掺杂漏极区域
公开(公告)号：US07297606B2
公开(公告)日：2007-11-20
申请号：US11116903
申请日：2005-04-28
申请人： Muhammed Ayman Shibib , Shuming Xu
发明人： Muhammed Ayman Shibib , Shuming Xu
IPC分类号： H01L21/336
CPC分类号： H01L29/402 , H01L29/0615 , H01L29/0847 , H01L29/0873 , H01L29/4175 , H01L29/66659 , H01L29/7835
摘要： An MOS device includes a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions. The MOS device further includes a buried LDD region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being spaced laterally from the drain region, and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.
摘要翻译： MOS器件包括形成在半导体层中的第一导电类型的半导体层，第二导电类型的源极区和形成在半导体层中并与源极区隔开的第二导电类型的漏极区。栅极形成在半导体层的上表面附近，并且至少部分地在源区和漏区之间形成。 MOS器件还包括形成在栅极和漏极区域之间的半导体层中的第二导电类型的埋入LDD区域，所述掩埋LDD区域与漏极区域横向间隔开，并且形成第一导电类型的第二LDD区域在掩埋的LDD区域中并且靠近半导体层的上表面。第二LDD区域与栅极自对准并且与栅极横向隔开，使得栅极相对于第二LDD区域不重叠。

5. 发明授权

US07282765B2 Power LDMOS transistor 有权
标题翻译：电源LDMOS晶体管
公开(公告)号：US07282765B2
公开(公告)日：2007-10-16
申请号：US11180155
申请日：2005-07-13
申请人： Shuming Xu , Jacek Korec
发明人： Shuming Xu , Jacek Korec
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4933 , H01L29/7802 , H01L29/7811 , H01L29/7823
摘要： An LDMOS device comprises a substrate having a first conductivity type and a lightly doped epitaxial layer thereon having an upper surface. Source and drain regions of the first conductivity type are formed in the epitaxial layer along with a channel region of a second conductivity type formed therebetween. A conductive gate is formed over a gate dielectric layer. A drain contact electrically connects the drain region to the substrate, comprising a first trench formed from the upper surface of the epitaxial layer to the substrate and having a side wall along the epitaxial layer, a highly doped region of the first conductivity type formed along the side wall of the first trench, and a drain plug in the first trench adjacent the highly doped region. A source contact is provided and an insulating layer is formed between the conductive gate and the source contact.
摘要翻译： LDMOS器件包括具有第一导电类型的衬底和其上具有上表面的轻掺杂外延层。第一导电类型的源区和漏区与其间形成的第二导电类型的沟道区一起形成在外延层中。导电栅极形成在栅极电介质层上。漏极接触将漏极区域电连接到衬底，包括从外延层的上表面到衬底形成的第一沟槽，并且沿着外延层具有侧壁，沿着所述外延层形成的第一导电类型的高掺杂区域沿着所述第一沟槽的侧壁以及与所述高掺杂区域相邻的所述第一沟槽中的排水塞。提供源极触点，并且在导电栅极和源极触点之间形成绝缘层。

6. 发明申请

US20070034942A1 Power LDMOS transistor 有权
标题翻译：电源LDMOS晶体管
公开(公告)号：US20070034942A1
公开(公告)日：2007-02-15
申请号：US11202981
申请日：2005-08-12
申请人： Shuming Xu , Jacek Korec
发明人： Shuming Xu , Jacek Korec
IPC分类号： H01L31/00
CPC分类号： H01L29/7835 , H01L29/1083 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/4933
摘要： A LDMOS transistor comprises a trench formed through the epitaxial layer at least to the top surface of the substrate, the trench having a bottom surface and a sidewall contacting the source region and the portion of the channel region extending under the source region. A first insulating layer is formed over the upper surface and sidewall surfaces of the conductive gate. A continuous layer of conductive material forming a source contact and a gate shield electrode is formed along the bottom surface and the sidewall of the trench and over the first insulating layer to cover the top and sidewall surfaces of the conductive gate. A second insulating layer is formed over an active area of the transistor, including over the continuous layer of conductive material and filling the trench. A drain electrode can extend over the second insulating layer to substantially cover the active area.
摘要翻译： LDMOS晶体管包括至少通过外延层形成的沟槽，至少到衬底的顶表面，沟槽具有接触源极区域和在源极区域下延伸的沟道区域的部分的底表面和侧壁。在导电栅极的上表面和侧壁表面上形成第一绝缘层。形成源极接触和栅极屏蔽电极的连续导电材料层沿着沟槽的底表面和侧壁形成，并且在第一绝缘层上方覆盖导电栅极的顶表面和侧壁表面。在晶体管的有源区域上形成第二绝缘层，包括在连续的导电材料层上并填充沟槽。漏电极可以在第二绝缘层上延伸以基本覆盖有源区。

7. 发明申请

US20070013008A1 Power LDMOS transistor 有权
公开(公告)号：US20070013008A1
公开(公告)日：2007-01-18
申请号：US11180155
申请日：2005-07-13
申请人： Shuming Xu , Jacek Korec
发明人： Shuming Xu , Jacek Korec
IPC分类号： H01L21/337
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4933 , H01L29/7802 , H01L29/7811 , H01L29/7823
摘要： An LDMOS device comprises a substrate having a first conductivity type and a lightly doped epitaxial layer thereon having an upper surface. Source and drain regions of the first conductivity type are formed in the epitaxial layer along with a channel region of a second conductivity type formed therebetween. A conductive gate is formed over a gate dielectric layer. A drain contact electrically connects the drain region to the substrate, comprising a first trench formed from the upper surface of the epitaxial layer to the substrate and having a side wall along the epitaxial layer, a highly doped region of the first conductivity type formed along the side wall of the first trench, and a drain plug in the first trench adjacent the highly doped region. A source contact is provided and an insulating layer is formed between the conductive gate and the source contact.

8. 发明申请

US20060071270A1 Metal-oxide-semiconductor device having trenched diffusion region and method of forming same 审中-公开
标题翻译：具有沟槽扩散区域的金属氧化物半导体器件及其形成方法
公开(公告)号：US20060071270A1
公开(公告)日：2006-04-06
申请号：US10953018
申请日：2004-09-29
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L21/223 , H01L21/2253 , H01L21/266 , H01L29/0653 , H01L29/0657 , H01L29/0886 , H01L29/1037 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.
摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的靠近半导体层的上表面的第二导电类型的第一和第二源极/漏极区域。第一和第二源极/漏极区域相对于彼此间隔开。至少部分地在第一和第二源极/漏极区之间形成栅极，并与半导体层电隔离。第一和第二源极/漏极区域中的至少一个被配置为具有基本上大于半导体层和给定源极/漏极区域之间的结的宽度的有效宽度。

9. 发明申请

US20050285189A1 Graded conductive structure for use in a metal-oxide-semiconductor device 有权
标题翻译：用于金属氧化物半导体器件的分级导电结构
公开(公告)号：US20050285189A1
公开(公告)日：2005-12-29
申请号：US10878857
申请日：2004-06-28
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： H01L21/336 , H01L29/08 , H01L29/40 , H01L29/417 , H01L29/76 , H01L29/78
CPC分类号： H01L29/7816 , H01L29/0847 , H01L29/402 , H01L29/404 , H01L29/4175 , H01L29/41758 , H01L29/41775 , H01L29/66659 , H01L29/7802 , H01L29/7835
摘要： An MOS device comprises a semiconductor layer of a first conductivity type and source and drain regions of a second conductivity type formed in the semiconductor layer, the source and drain regions being spaced apart from one another. A drift region is formed in the semiconductor layer proximate an upper surface of the semiconductor layer and between the source and drain regions, and a insulating layer is formed on the semiconductor layer above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the source and drift regions. The MOS device further includes a conductive structure comprising a first end formed on the insulating layer and spaced apart from the gate, and a second end formed on the insulating layer and extending laterally toward the drain region above at least a portion of the drift region. The conductive structure is configured such that a thickness of the insulating layer under the second end of the conductive structure increases as the second end extends toward the drain region.
摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的第二导电类型的源区和漏区，源极和漏极彼此间隔开。在半导体层中，靠近半导体层的上表面并且在源极和漏极区之间形成漂移区，并且在漂移区的至少一部分上方的半导体层上形成绝缘层。栅极形成在绝缘层上并且至少部分地在源极和漂移区域之间。 MOS器件还包括导电结构，该导电结构包括形成在绝缘层上并与栅极隔开的第一端，以及形成在绝缘层上并在漂移区的至少一部分上方向漏极区横向延伸的第二端。导电结构被构造成使得当导电结构的第二端下方的绝缘层的厚度随着第二端向漏极区延伸而增加。

10. 发明授权

US08722503B2 Capacitors and methods of forming 有权
标题翻译：电容器和成型方法
公开(公告)号：US08722503B2
公开(公告)日：2014-05-13
申请号：US13184854
申请日：2011-07-18
申请人： Jacek Korec , Shuming Xu , Jun Wang , Boyi Yang
发明人： Jacek Korec , Shuming Xu , Jun Wang , Boyi Yang
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L29/66181
摘要： Capacitors and methods of forming semiconductor device capacitors are disclosed. Trenches are formed to define a capacitor bottom plate in a doped upper region of a semiconductor substrate, a dielectric layer is formed conformally over the substrate within the trenches, and a polysilicon layer is formed over the dielectric layer to define a capacitor top plate. A guard ring region of opposite conductivity and peripheral recessed areas may be added to avoid electric field crowding. A central substrate of lower doping concentration may be provided to provide a resistor in series below the capacitor bottom plate. A series resistor may also be provided in a resistivity region of the polysilicon layer laterally extending from the trenched area region. Contact for the capacitor bottom plate may be made through a contact layer formed on a bottom of the substrate. A top contact may be formed laterally spaced from the trenched area by patterning laterally extended portions of one or more of the dielectric, polysilicon and top metal contact layers.
摘要翻译：公开了形成半导体器件电容器的电容器和方法。形成沟槽以在半导体衬底的掺杂上部区域中限定电容器底板，电介质层在沟槽内的衬底上共形地形成，并且在电介质层上形成多晶硅层以限定电容器顶板。可以添加相反导电性和周边凹陷区域的保护环区域，以避免电场拥挤。可以提供较低掺杂浓度的中心衬底以在电容器底板下方串联提供串联的电阻器。也可以在从沟槽区域侧向延伸的多晶硅层的电阻率区域中提供串联电阻器。电容器底板的接触可以通过形成在基板的底部上的接触层制成。可以通过对电介质，多晶硅和顶部金属接触层中的一个或多个的横向延伸部分进行图案来形成顶部接触件与沟槽区域横向间隔开。

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