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41. 发明授权

US5926697A Method of forming a moisture guard ring for integrated circuit applications 失效
标题翻译：形成用于集成电路应用的防潮环的方法
公开(公告)号：US5926697A
公开(公告)日：1999-07-20
申请号：US947793
申请日：1997-10-09
申请人： Dun-Nian Yaung , Shou-Gwo Wuu , Jin-Yuan Lee , Hsien Wei Chin
发明人： Dun-Nian Yaung , Shou-Gwo Wuu , Jin-Yuan Lee , Hsien Wei Chin
IPC分类号： H01L21/02 , H01L21/761 , H01L23/525 , H01L21/76
CPC分类号： H01L28/87 , H01L21/761 , H01L23/5258 , H01L2924/0002
摘要： An improved and new structure and method for forming a guard ring in an integrated circuit having at least one level of polysilicon wiring has been developed. The guard ring is formed without necessitating additional manufacturing process steps and the guard ring is bonded to the semiconductor substrate, thereby providing a superior barrier to diffusion of moisture and contaminants from a window in the insulating layers to the semiconductor device regions.
摘要翻译：已经开发了用于在具有至少一个级别的多晶硅布线的集成电路中形成保护环的改进和新的结构和方法。保护环形成，而不需要额外的制造工艺步骤，并且保护环结合到半导体衬底，从而为水分和污染物从绝缘层中的窗口扩散到半导体器件区域提供了优越的屏障。

42. 发明授权

US08124495B2 Semiconductor device having enhanced photo sensitivity and method for manufacture thereof 有权
标题翻译：具有增强的光敏度的半导体器件及其制造方法
公开(公告)号：US08124495B2
公开(公告)日：2012-02-28
申请号：US11627883
申请日：2007-01-26
申请人： Tzu-Hsuan Hsu , Dun-Nian Yaung , Shou-Gwo Wuu , Ho-Ching Chien , Chien-Hsien Tseng , Jeng-Shyan Lin
发明人： Tzu-Hsuan Hsu , Dun-Nian Yaung , Shou-Gwo Wuu , Ho-Ching Chien , Chien-Hsien Tseng , Jeng-Shyan Lin
IPC分类号： H01L21/76
CPC分类号： H01L27/14689 , H01L27/1463
摘要： Provided are a semiconductor device and a method for its manufacture. In one example, the method includes forming an isolation structure having a first refraction index over a sensor embedded in a substrate. A first layer having a second refraction index that is different from the first refraction index is formed over the isolation structure. The first layer is removed from at least a portion of the isolation structure. A second layer having a third refraction index is formed over the isolation structure after the first layer is removed. The third refraction index is substantially similar to the first refraction index.
摘要翻译：提供半导体器件及其制造方法。在一个示例中，该方法包括在嵌入基板中的传感器上形成具有第一折射率的隔离结构。在隔离结构上形成具有与第一折射率不同的第二折射率的第一层。从隔离结构的至少一部分去除第一层。在去除第一层之后，在隔离结构上形成具有第三折射率的第二层。第三折射率基本上类似于第一折射率。

43. 发明授权

US08054371B2 Color filter for image sensor 有权
标题翻译：图像传感器滤色片
公开(公告)号：US08054371B2
公开(公告)日：2011-11-08
申请号：US11676388
申请日：2007-02-19
申请人： Ching-Chun Wang , Dun-Nian Yaung , Chien-Hsien Tseng , Shou-Gwo Wuu
发明人： Ching-Chun Wang , Dun-Nian Yaung , Chien-Hsien Tseng , Shou-Gwo Wuu
IPC分类号： H04N5/225 , H04N5/335 , G02B5/30 , H04L31/062
CPC分类号： G02B5/201 , G02B5/223
摘要： An image sensor device includes a semiconductor substrate having a front surface and a back surface, pixels formed on the front surface of the semiconductor substrate, and grid arrays aligned with one of the pixels. One of the grid arrays is configured to allow a wavelength of light to pass through to the corresponding one of the pixels. The grid arrays are disposed overlying the front or back surface of the semiconductor substrate.
摘要翻译：图像传感器装置包括具有前表面和后表面的半导体衬底，形成在半导体衬底的前表面上的像素和与像素之一对准的栅格阵列。网格阵列中的一个被配置为允许光的波长通过到相应的一个像素。栅格阵列设置在半导体衬底的前表面或后表面上。

44. 发明授权

US07588993B2 Alignment for backside illumination sensor 有权
标题翻译：背面照明传感器对准
公开(公告)号：US07588993B2
公开(公告)日：2009-09-15
申请号：US11951916
申请日：2007-12-06
申请人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
发明人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
IPC分类号： H01L21/76
CPC分类号： H01L23/544 , H01L21/71 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An apparatus and manufacturing method thereof, wherein an integrated circuit is located in a first region of a substrate having first and second opposing major surfaces, and wherein an alignment mark is located in a second region of the substrate and extends through the substrate between the first and second surfaces. The alignment mark may protrude from the first and/or second surfaces, and/or may comprise a plurality of substantially similar alignment marks. The second region may interpose the first region and a perimeter of the substrate. The second region may comprise a scribe region.
摘要翻译：一种装置及其制造方法，其中集成电路位于具有第一和第二相对主表面的基板的第一区域中，并且其中对准标记位于所述基板的第二区域中，并且延伸穿过所述基板在所述第一和第二表面。对准标记可以从第一和/或第二表面突出，和/或可以包括多个基本相似的对准标记。第二区域可以插入衬底的第一区域和周边。第二区域可以包括划线区域。

45. 发明授权

US07253458B2 CMOS image sensor 有权
标题翻译： CMOS图像传感器
公开(公告)号：US07253458B2
公开(公告)日：2007-08-07
申请号：US10980959
申请日：2004-11-04
申请人： Tzu-Hsuan Hsu , Dun-Nian Yaung , Wen-De Wang , Ho-Ching Chien , Shou-Gwo Wuu
发明人： Tzu-Hsuan Hsu , Dun-Nian Yaung , Wen-De Wang , Ho-Ching Chien , Shou-Gwo Wuu
IPC分类号： H01L27/148
CPC分类号： H01L27/14643 , H01L27/14621 , H01L27/14627 , H01L27/14636
摘要： A complementary metal oxide semiconductor field effect transistor (CMOS-FET) image sensor. An active photosensing pixel is formed on a substrate. At least one side of the pixel has a width equal to or less than approximately 3 μm. At least one dielectric layer is disposed on the substrate covering the pixel. A color filter is disposed on the least one dielectric layer. A microlens array is disposed on the color filter of the pixel, and the sum of the thickness of all dielectric layers and the color filter divided by the pixel width is equal to or less than approximately 1.87.
摘要翻译：互补金属氧化物半导体场效应晶体管（CMOS-FET）图像传感器。在基板上形成有源感光像素。像素的至少一侧具有等于或小于约3μm的宽度。在覆盖像素的基板上设置至少一个电介质层。滤色器设置在至少一个电介质层上。微透镜阵列设置在像素的滤色器上，所有电介质层和滤色器的厚度之和除以像素宽度等于或小于约1.87。

46. 发明申请

US20060186547A1 Light shield for CMOS imager 有权
公开(公告)号：US20060186547A1
公开(公告)日：2006-08-24
申请号：US11066432
申请日：2005-02-24
申请人： Wen-De Wang , Dun-Nian Yaung , Shou-Gwo Wuu , Chung-Yi Yu
发明人： Wen-De Wang , Dun-Nian Yaung , Shou-Gwo Wuu , Chung-Yi Yu
IPC分类号： H01L23/52
CPC分类号： H01L27/14654 , H01L27/14623 , H01L27/14636 , H01L2924/0002 , H01L2924/00
摘要： System and method for providing a light shield for a CMOS imager is provided. The light shield comprises a structure formed above a point between a photo-sensitive element and adjacent circuitry. The structure is formed of a light-blocking material, such as a metal, metal alloy, metal compound, or the like, formed in dielectric layers over the photo-sensitive elements.

47. 发明授权

US06982443B2 Hollow dielectric for image sensor 有权
公开(公告)号：US06982443B2
公开(公告)日：2006-01-03
申请号：US10799986
申请日：2004-03-12
申请人： Tzu-Hsuan Hsu , Shou-Gwo Wuu , Ho-Ching Chien , Dun-Nian Yaung
发明人： Tzu-Hsuan Hsu , Shou-Gwo Wuu , Ho-Ching Chien , Dun-Nian Yaung
IPC分类号： H01L27/148 , H01L29/768
CPC分类号： H01L27/14632 , H01L27/1462
摘要： A plurality of apertures is formed in at least one first insulating layer disposed over a sensor formed in a semiconductor substrate. A second insulating layer is disposed over the at least one first insulating layer and the plurality of apertures in the at least one first insulating layer. The apertures form hollow regions in the at least one first insulating layer over the sensor, allowing more light or energy to pass through the at least one first insulating layer to the sensor, and increasing the sensitivity of the sensor.

48. 发明授权

US06642076B1 Asymmetrical reset transistor with double-diffused source for CMOS image sensor 有权
标题翻译： CMOS图像传感器双扩散源非对称复位晶体管
公开(公告)号：US06642076B1
公开(公告)日：2003-11-04
申请号：US10278134
申请日：2002-10-22
申请人： Dun-Nian Yaung , Shou-Gwo Wuu , Ho-Ching Chien , Chien-Hsien Tseng
发明人： Dun-Nian Yaung , Shou-Gwo Wuu , Ho-Ching Chien , Chien-Hsien Tseng
IPC分类号： H01L2100
CPC分类号： H01L27/14689 , H01L27/0802 , H01L27/14609 , H01L27/1463
摘要： A new method to form CMOS image sensors in the manufacture of an integrated circuit device is achieved. The method comprises providing a semiconductor substrate. Sensor diodes are formed in the semiconductor substrate each comprising a first terminal and a second terminal. Gates are formed for transistors in the CMOS image sensors. The gates comprise a conductor layer overlying the semiconductor substrate with an insulating layer therebetween. The transistors include reset transistors. Ions are implanted into the semiconductor substrate to form source/drain regions for the transistors. The source regions of the reset transistors are formed in the first terminals of the sensor diodes. Ions are implanted into the reset transistor sources to form double diffused sources. The implanting is blocked from other source/drain regions.
摘要翻译：实现了在制造集成电路器件中形成CMOS图像传感器的新方法。该方法包括提供半导体衬底。传感器二极管形成在每个包括第一端子和第二端子的半导体衬底中。为CMOS图像传感器中的晶体管形成栅极。栅极包括覆盖半导体衬底的导体层，其间具有绝缘层。晶体管包括复位晶体管。将离子注入到半导体衬底中以形成用于晶体管的源极/漏极区域。复位晶体管的源极区域形成在传感器二极管的第一端子中。离子被植入到复位晶体管源中以形成双扩散源。植入物从其它源极/漏极区域被阻挡。

49. 发明授权

US06350662B1 Method to reduce defects in shallow trench isolations by post liner anneal 有权
标题翻译：通过后衬板退火来减少浅沟槽隔离缺陷的方法
公开(公告)号：US06350662B1
公开(公告)日：2002-02-26
申请号：US09357244
申请日：1999-07-19
申请人： Kong-Beng Thei , Kuei-Ying Lee , Dun-Nian Yaung , Shou-Gwo Wuu
发明人： Kong-Beng Thei , Kuei-Ying Lee , Dun-Nian Yaung , Shou-Gwo Wuu
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method to form shallow trench isolations with reduced substrate defects by using a nitrogen anneal is achieved. A silicon substrate is provided. The silicon substrate is etched where not protected by a photoresist mask to form shallow trenches where shallow trench isolations are planned. A liner oxide layer is grown on the interior surfaces of the shallow trenches. The silicon substrate and the liner oxide layer are annealed to reduce or eliminate defects, dislocations, interface traps, and stress in the silicon substrate. An isolation oxide layer is deposited overlying the liner oxide layer and completely filling the shallow trenches. The isolation oxide layer is etched down to the top surface of the silicon substrate and thereby forms the shallow trench isolations. The integrated circuit device is completed.
摘要翻译：实现了通过使用氮退火形成具有减少的衬底缺陷的浅沟槽隔离的方法。提供硅衬底。蚀刻硅衬底，其中未被光致抗蚀剂掩模保护以形成浅沟槽，其中规划浅沟槽隔离。在浅沟槽的内表面上生长衬里氧化物层。对硅衬底和衬里氧化物层进行退火以减少或消除硅衬底中的缺陷，位错，界面陷阱和应力。隔离氧化物层沉积在衬垫氧化物层上并且完全填充浅沟槽。隔离氧化物层被蚀刻到硅衬底的顶表面，从而形成浅沟槽隔离。集成电路装置完成。

50. 发明授权

US06232194B1 Silicon nitride capped poly resistor with SAC process 有权
标题翻译：具有SAC工艺的氮化硅封端聚电阻
公开(公告)号：US06232194B1
公开(公告)日：2001-05-15
申请号：US09434921
申请日：1999-11-05
申请人： Dun-Nian Yaung , Shou-Gwo Wuu
发明人： Dun-Nian Yaung , Shou-Gwo Wuu
IPC分类号： H01L2120
CPC分类号： H01L28/20 , H01L21/3185 , H01L27/11 , H01L27/1112
摘要： A new method of forming a polysilicon resistor having precisely controlled resistance by using a thin silicon nitride cap over the polysilicon resistor is described. A dielectric layer is provided on a semiconductor substrate. A polysilicon layer is deposited overlying the dielectric layer and patterned to form a polysilicon resistor. A silicon nitride capping layer having a thickness of not more than 100 Angstroms is deposited overlying the polysilicon resistor and dielectric layer. An interlevel dielectric layer is deposited overlying the silicon nitride capping layer. The substrate is annealed thereby densifying the silicon nitride capping layer. A self-aligned contact opening may be made through the interlevel dielectric layer, the silicon nitride capping layer, and the dielectric layer to underlying device structures. The capping silicon nitride layer is thin enough not to act as an etch stop in the self-aligned contact etching. The contact opening is filled with a conducting layer. A passivation layer is deposited overlying the conducting layer wherein the passivation layer contains hydrogen atoms and wherein the silicon nitride capping layer prevents the hydrogen atoms from penetrating the polysilicon resistor.
摘要翻译：描述了通过在多晶硅电阻器上使用薄的氮化硅盖来形成具有精确控制电阻的多晶硅电阻器的新方法。介电层设置在半导体衬底上。沉积覆盖在电介质层上并形成多晶硅电阻器的多晶硅层。覆盖多晶硅电阻器和电介质层上的厚度不大于100埃的氮化硅覆盖层。沉积覆盖氮化硅覆盖层的层间电介质层。将衬底退火，从而使氮化硅覆盖层致密化。可以通过层间介质层，氮化硅覆盖层和介电层到底层器件结构来制造自对准的接触开口。封盖氮化硅层足够薄，不能用作自对准接触蚀刻中的蚀刻停止。接触开口填充有导电层。钝化层沉积在导电层上，其中钝化层包含氢原子，并且其中氮化硅覆盖层防止氢原子穿透多晶硅电阻器。

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