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41. 发明授权

US08810281B2 Sense amplifiers including bias circuits 有权
标题翻译：感应放大器包括偏置电路
公开(公告)号：US08810281B2
公开(公告)日：2014-08-19
申请号：US13191263
申请日：2011-07-26
申请人： Seong-Hoon Lee
发明人： Seong-Hoon Lee
IPC分类号： G01R19/00
CPC分类号： H03F3/45071 , G11C7/062 , G11C7/065 , G11C7/12 , G11C2207/063 , H03F1/301 , H03F3/45179 , H03F2200/453 , H03F2200/462 , H03F2200/91 , H03F2203/45154 , H03F2203/45176
摘要： Sense amplifiers including bias circuits are described. Examples include bias circuits having an adjustable width transistor. A loop gain of the bias circuit may be determined in part by the adjustable width of the transistor. Examples of sense amplifiers including amplifier stages configured to bias an input/output node to a reference voltage.
摘要翻译：描述了包括偏置电路的感应放大器。示例包括具有可调宽度晶体管的偏置电路。偏置电路的环路增益可以部分地由晶体管的可调宽度确定。读出放大器的示例包括被配置为将输入/输出节点偏置到参考电压的放大器级。

42. 发明授权

US08743642B2 Data serializers, output buffers, memory devices and methods of serializing 有权
标题翻译：数据串行器，输出缓冲器，存储器件和序列化方法
公开(公告)号：US08743642B2
公开(公告)日：2014-06-03
申请号：US13491311
申请日：2012-06-07
申请人： Seong-Hoon Lee
发明人： Seong-Hoon Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1048 , G11C7/1057 , G11C7/1072 , G11C11/4093 , G11C2207/107 , H03M9/00
摘要： Data serializers, output buffers, memory devices and methods for serializing are provided, including a data serializer that may convert digits of parallel data to a stream of corresponding digits of serial data digits. One such data serializer may include a logic system receiving the parallel data digits and clock signals having phases that are equally phased apart from each other. Such a data serializer may use the clock signals to generate data sample signals having a value corresponding to the value of a respective one of the parallel data digits and a timing corresponding to a respective one of the clock signals. The data sample signals may be applied to a switching circuit that includes a plurality of switches, such as respective transistors, coupled to each other in parallel between an output node and a first voltage.
摘要翻译：提供了数据串行器，输出缓冲器，存储器件和用于串行化的方法，包括可将并行数据的数字转换为串行数据数字的对应数字流的数据串行器。一个这样的数据串行器可以包括接收并行数据位的逻辑系统和具有彼此相位分开的相位的时钟信号。这样的数据串行器可以使用时钟信号来产生具有对应于并行数据位中的相应一个的值的值的数据采样信号和对应于相应的一个时钟信号的定时。数据采样信号可以被施加到包括在输出节点和第一电压之间并联耦合的多个开关（诸如相应的晶体管）的开关电路。

43. 发明授权

US08552416B2 Quantum dot light emitting diode device and display device therewith 有权
标题翻译：量子点式发光二极管装置及其显示装置
公开(公告)号：US08552416B2
公开(公告)日：2013-10-08
申请号：US13115537
申请日：2011-05-25
申请人： Young-Mi Kim , Ho-Cheol Kang , Ho-Jin Kim , Chang-Hee Lee , Kook-Heon Char , Seong-Hoon Lee , Jeong-Hun Kwak , Wan-Ki Bae , Dong-Gu Lee , Jae-Hoon Lim
发明人： Young-Mi Kim , Ho-Cheol Kang , Ho-Jin Kim , Chang-Hee Lee , Kook-Heon Char , Seong-Hoon Lee , Jeong-Hun Kwak , Wan-Ki Bae , Dong-Gu Lee , Jae-Hoon Lim
IPC分类号： H01L29/06
CPC分类号： H01L51/502 , H01L27/3244 , H01L51/5004 , H01L51/5036
摘要： The present invention relates to a quantum dot light emitting diode device in which a hole transportation layer is formed after forming a quantum dot light emitting layer by a solution process by applying an inverted type quantum dot light emitting diode device for making free selection of a hole transportation layer material that enables easy injection of a hole to the quantum dot light emitting layer; and display device and method therewith.
摘要翻译：本发明涉及一种量子点式发光二极管装置，其中通过应用倒置型量子点发光二极管装置，通过溶液法形成量子点发光层，形成空穴传输层，用于自由选择孔能够容易地向量子点发光层注入孔的输送层材料; 和显示装置及其方法。

44. 发明授权

US08283946B2 Signaling systems, preamplifiers, memory devices and methods 有权
标题翻译：信号系统，前置放大器，存储器件和方法
公开(公告)号：US08283946B2
公开(公告)日：2012-10-09
申请号：US12760922
申请日：2010-04-15
申请人： Seong-Hoon Lee
发明人： Seong-Hoon Lee
IPC分类号： H03K19/0175
CPC分类号： H03F3/245 , H03K19/00315 , H04L25/0272
摘要： Signaling systems, preamplifiers, memory devices and methods are disclosed, such as a signaling system that includes a transmitter configured to receive a first digital signal. The transmitter provides a transmitted signal corresponding to the digital signal to a signal path. A receiver system coupled to the signal line includes a preamplifier coupled to receive the transmitted signal from the signal path. The preamplifier includes a common-gate amplifying transistor that is configured to provide an amplified signal. The receiver system also includes a receiver coupled to receive the amplified signal from the preamplifier. The receiver is configured to provide a second digital signal corresponding to the amplified signal received by the receiver. Such a signaling system may be used in a memory device or in any other electronic circuit.
摘要翻译：公开了信号系统，前置放大器，存储器件和方法，例如包括被配置为接收第一数字信号的发射器的信令系统。发射机将对应于数字信号的发射信号提供给信号路径。耦合到信号线的接收机系统包括前置放大器，其被耦合以从信号路径接收发送的信号。前置放大器包括配置成提供放大信号的共栅放大晶体管。接收机系统还包括接收器，用于从前置放大器接收放大的信号。接收器被配置为提供对应于由接收器接收的放大信号的第二数字信号。这样的信令系统可以用在存储器装置或任何其它电子电路中。

45. 发明申请

US20120210546A1 FASTENER AND DISASSEMBLING APPARATUS FOR THE SAME 审中-公开
标题翻译：紧固件和拆卸装置
公开(公告)号：US20120210546A1
公开(公告)日：2012-08-23
申请号：US13169145
申请日：2011-06-27
申请人： Hong-Min JANG , Seong-Hoon Lee
发明人： Hong-Min JANG , Seong-Hoon Lee
IPC分类号： F16B1/00 , B23P19/00
CPC分类号： A63H33/101 , F16B21/086 , Y10T24/45529 , Y10T29/53
摘要： The present invention relates to a fastener and a disassembling apparatus for the same. The fastener (10) of the present invention has a cylindrical hollow body (12) which configures a framework. A through hole (14) is penetrated through an inside of the hollow body (12) in a longitudinal direction thereof. A plurality of coupling legs (16) are formed by deformation slits (18) to extend toward one end portion of the hollow body (12). A coupling protrusion (20) is formed at an outer surface of the front end of the coupling leg (16), while a releasing portion (24) is formed at an inner side of the hollow body (12) which is opposite to the outer surface. A placing step (22) is formed in a stepwise manner at a location adjacent to the other end portion of the hollow body (12) which corresponds to an opposite side of the coupling protrusion (20). A separating protrusion (28) is formed at an end of the other end portion of the hollow body (12). A disassembling apparatus (30) has a release pin (34) protruding on one side of a frame (32), and a release coupling hole (36) is formed in the release pin (34) so that the releasing portion (24) may be inserted and guided in the release coupling hole (36). The release lever (38) is provided to extend to be spaced apart from the frame (32) at a predetermined interval, and a catching protrusion (40) caught by the separating protrusion (28) is formed at the front end of the release lever (38). According to the present invention, since the fastener (10) for coupling objects (50 and 50′) is configured as a single unit, the number of parts and the number of assembling processes may be reduced, and the fastener (10) may be handled more simply using the disassembling apparatus 30.
摘要翻译：本发明涉及一种紧固件及其拆卸装置。本发明的紧固件（10）具有构造框架的圆柱形中空体（12）。一个通孔（14）沿其纵向方向穿过中空体（12）的内部。多个联接腿（16）由变形狭缝（18）形成，以向中空体（12）的一个端部延伸。耦合突起（20）形成在联接腿（16）的前端的外表面处，而释放部分（24）形成在中空本体（12）的与外侧相反的内侧表面。在与中空体（12）的与联接突起（20）的相对侧相对应的另一端部的位置处，分阶段地形成放置台阶（22）。在中空体（12）的另一端部的端部形成有分离突起（28）。分解装置（30）具有在框架（32）的一侧上突出的释放销（34），并且在释放销（34）中形成有释放联结孔（36），使得释放部分（24）可以在释放联结孔（36）中插入和引导。释放杆（38）设置成以预定间隔与框架（32）间隔开延伸，并且在释放杆的前端形成有由分离突起（28）卡住的捕获突起（40）（38）。根据本发明，由于用于连接物体（50和50'）的紧固件（10）被构造为单个单元，所以可以减少部件的数量和组装过程的数量，并且紧固件（10）可以是使用拆卸装置30更简单地处理。

46. 发明授权

US08203900B2 Data serializers, output buffers, memory devices and methods of serializing 有权
标题翻译：数据串行器，输出缓冲器，存储器件和序列化方法
公开(公告)号：US08203900B2
公开(公告)日：2012-06-19
申请号：US12500207
申请日：2009-07-09
申请人： Seong-Hoon Lee
发明人： Seong-Hoon Lee
IPC分类号： G11C7/02
CPC分类号： G11C7/1051 , G11C7/1048 , G11C7/1057 , G11C7/1072 , G11C11/4093 , G11C2207/107 , H03M9/00
摘要： Data serializers, output buffers, memory devices and methods for serializing are provided, including a data serializer that may convert digits of parallel data to a stream of corresponding digits of serial data digits. One such data serializer may include a logic system receiving the parallel data digits and clock signals having phases that are equally phased apart from each other. Such a data serializer may use the clock signals to generate data sample signals having a value corresponding to the value of a respective one of the parallel data digits and a timing corresponding to a respective one of the clock signals. The data sample signals may be applied to a switching circuit that includes a plurality of switches, such as respective transistors, coupled to each other in parallel between an output node and a first voltage.
摘要翻译：提供了数据串行器，输出缓冲器，存储器件和用于串行化的方法，包括可将并行数据的数字转换为串行数据数字的对应数字流的数据串行器。一个这样的数据串行器可以包括接收并行数据位的逻辑系统和具有彼此相位分开的相位的时钟信号。这样的数据串行器可以使用时钟信号来产生具有对应于并行数据位中的相应一个的值的值的数据采样信号和对应于相应的一个时钟信号的定时。数据采样信号可以被施加到包括在输出节点和第一电压之间并联耦合的多个开关（诸如相应的晶体管）的开关电路。

47. 发明授权

US08008947B2 Balanced phase detector 有权
标题翻译：平衡相位检测器
公开(公告)号：US08008947B2
公开(公告)日：2011-08-30
申请号：US12939869
申请日：2010-11-04
申请人： Seong-Hoon Lee
发明人： Seong-Hoon Lee
IPC分类号： G01R25/00
CPC分类号： H03D13/004
摘要： Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of two clock signals leads the other. One such phase detector includes a balancer configured to prepare the phase detection circuit for a phase detection. The phase detection circuit of one or more embodiments includes a cross-coupled latch configured to receive the two clock signals and generate a first latch output and a second latch output in response to the two clock signals. The aforementioned balancer is configured to substantially equalize the voltage levels of the first and second latch outputs before the phase detection circuit detects a phase difference between the two clock signals. For example, the balancer might pre-charge the outputs of the phase detection circuit to substantially the same voltage level before phase detection.
摘要翻译：公开了诸如涉及数字相位检测器的方法和装置，该数字相位检测器包括被配置为检测两个时钟信号中的哪一个引导另一个的相位检测电路。一个这样的相位检测器包括配置成准备用于相位检测的相位检测电路的平衡器。一个或多个实施例的相位检测电路包括交叉耦合锁存器，其被配置为接收两个时钟信号，并响应于两个时钟信号产生第一锁存器输出和第二锁存器输出。上述平衡器被配置为在相位检测电路检测到两个时钟信号之间的相位差之前基本均衡第一和第二锁存器输出的电压电平。例如，平衡器可以在相位检测之前将相位检测电路的输出预充电至基本相同的电压电平。

48. 发明申请

US20100311304A1 FIGHTER ROBOT SYSTEM 失效
标题翻译： FIGHTER机器人系统
公开(公告)号：US20100311304A1
公开(公告)日：2010-12-09
申请号：US12795100
申请日：2010-06-07
申请人： Hong-Min JANG , Seong-Hoon Lee
发明人： Hong-Min JANG , Seong-Hoon Lee
IPC分类号： A63H13/06
CPC分类号： A63H13/06
摘要： A fighter robot system that supplies power to two fighter robots, which have a match against each other, through respective power lines and prevents the power lines from becoming entangled even when the robots are moving. The fighter robot system includes two fighter robots, a power supply providing power to the fighter robots, and a rotary member located above or below the fighter robots, the rotary member having a predetermined length and rotatable around a central axis formed at a predetermined portion. The power supply provides the power to the fighter robots through power lines. Each power line starts from the power supply, extends from the central axis to either end of the rotary member in the lengthwise direction, and is connected at that end to each fighter robot. The rotary member rotates around the central axis following the movement of the fighter robots.
摘要翻译：一种战斗机器人系统，通过各自的电源线向两个相互匹配的战斗机器人供电，即使在机器人移动时也能防止电力线缠结。战斗机器人系统包括两个战斗机器人，为战斗机器人提供动力的电源，以及位于战斗机器人上方或下方的旋转构件，旋转构件具有预定长度并可围绕形成在预定部分的中心轴线旋转。电源通过电源线为战斗机器人提供动力。每个电源线从电源开始，从长轴方向的中心轴线延伸到旋转部件的任一端，并且在该端部连接到每个战斗机器人。随着战斗机器人的移动，旋转构件围绕中心轴线旋转。

49. 发明授权

US07839179B2 Balanced phase detector 有权
标题翻译：平衡相位检测器
公开(公告)号：US07839179B2
公开(公告)日：2010-11-23
申请号：US11762557
申请日：2007-06-13
申请人： Seong-Hoon Lee
发明人： Seong-Hoon Lee
IPC分类号： G01R25/00
CPC分类号： H03D13/004
摘要： Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of two clock signals leads the other. One such phase detector includes a balancer configured to prepare the phase detection circuit for a phase detection. The phase detection circuit of one or more embodiments includes a cross-coupled latch configured to receive the two clock signals and generate a first latch output and a second latch output in response to the two clock signals. The aforementioned balancer is configured to substantially equalize the voltage levels of the first and second latch outputs before the phase detection circuit detects a phase difference between the two clock signals. For example, the balancer might pre-charge the outputs of the phase detection circuit to substantially the same voltage level before phase detection.
摘要翻译：公开了诸如涉及数字相位检测器的方法和装置，该数字相位检测器包括被配置为检测两个时钟信号中的哪一个引导另一个的相位检测电路。一个这样的相位检测器包括配置成准备用于相位检测的相位检测电路的平衡器。一个或多个实施例的相位检测电路包括交叉耦合锁存器，其配置为接收两个时钟信号，并响应于两个时钟信号产生第一锁存器输出和第二锁存器输出。上述平衡器被配置为在相位检测电路检测到两个时钟信号之间的相位差之前基本均衡第一和第二锁存器输出的电压电平。例如，平衡器可以在相位检测之前将相位检测电路的输出预充电至基本相同的电压电平。

50. 发明授权

US07274236B2 Variable delay line with multiple hierarchy 有权
标题翻译：具有多层次的可变延迟线
公开(公告)号：US07274236B2
公开(公告)日：2007-09-25
申请号：US11107587
申请日：2005-04-15
申请人： Seong-Hoon Lee
发明人： Seong-Hoon Lee
IPC分类号： H03L7/06
CPC分类号： H03H11/265 , H03K5/133 , H03K2005/00058 , H03K2005/00156
摘要： Disclosed herein are improved, simplified designs for a hierarchical delay line (HDL). The HDL is useful in providing precise phase control between an input clock signal and an output clock signal, and has particular utility as the variable delay in a delay-locked loop (DLL). In one embodiment, a coarse unit delay provides a delayed representation of an input clock. The original and delayed versions of the input clock are presented to a phase mixer block, which is controllable to weight its output to a phase between one of the two input clock signals. The output of the phase mixer block is then provided to a controllable variable delay line capable of adding further coarse delay into the processed signal. To assist in boundary switching, multiplexers are provided in the path between the original and delayed versions of the input clock and the phase mixer block, which provides the ability to boundary shift without having to reset the phase mixer.
摘要翻译：本文公开了改进的分层延迟线（HDL）的简化设计。 HDL可以在输入时钟信号和输出时钟信号之间提供精确的相位控制，并且具有延迟锁定环（DLL）中的可变延迟的特殊用途。在一个实施例中，粗略单位延迟提供输入时钟的延迟表示。输入时钟的原始和延迟版本被呈现给相位混频器模块，该相位混频器模块可控制以将其输出加权到两个输入时钟信号之一之间的相位。然后将相位混合器块的输出提供给能够将进一步的粗延迟加入到处理的信号中的可控可变延迟线。为了协助边界切换，多路复用器被提供在输入时钟的原始和延迟版本与相位混合器块之间的路径中，这提供了边界移位的能力，而不必复位相位混频器。

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