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    • 46. 发明申请
    • Tube fitting with separable tube gripping device
    • 管接头与可分离管夹持装置
    • US20070007766A1
    • 2007-01-11
    • US11522814
    • 2006-09-14
    • Mark BennettPeter Williams
    • Mark BennettPeter Williams
    • F16L47/00
    • F16L19/14F16L19/10
    • A tube fitting for a tube end has a female threaded member that cooperates with a male threaded member. The female member includes a tube gripping device in the form of a gripping ring or ferrule that is attached to the female member by a frangible web. Upon a partial pull-up the ferrule engages a camming surface on the male threaded member and breaks off or separates from the female threaded member to become a separate piece so that the fitting then functions as a single ferrule tube fitting. Additional features include a steep camming angle on the camming surface to cause the ferrule to grip the tube end with a bite-type action and to form a primary seal between the camming surface and a front end of the separated ferrule. The ferrule front end, and optionally the entire female threaded member including the initially integral tube gripping device, are hardened to be at least about 3.3 times harder than the material of the tube end.
    • 用于管端的管配件具有与阳螺纹构件配合的内螺纹构件。 阴构件包括通过易碎腹板附接到阴构件的夹紧环或套圈形式的管夹持装置。 在部分上拉时,套圈接合阳螺纹构件上的凸轮表面并且从内螺纹构件断开或分离成为单独的件,使得配件然后用作单个套圈管配件。 附加特征包括在凸轮表面上的陡峭的凸轮角度,以使套圈以咬入动作夹紧管端,并且在凸轮表面和分离的套圈的前端之间形成主密封。 套管前端以及可选地包括最初整体的管夹持装置的整个内螺纹构件被硬化至比管端材料的硬度至少约3.3倍。
    • 47. 发明申请
    • Micro-tile memory interfaces
    • 微瓦片存储器接口
    • US20070002668A1
    • 2007-01-04
    • US11174134
    • 2005-06-30
    • Peter WilliamsJames AkiyamaDouglas Gabel
    • Peter WilliamsJames AkiyamaDouglas Gabel
    • G11C8/00
    • G11C8/12G06F13/1684G11C5/04G11C11/4082
    • In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.
    • 在本发明的一个实施例中,提供一种存储器集成电路,包括:地址解码器,用于选择性地访问存储器阵列内的存储单元; 具有位存储电路的模式寄存器,用于存储使能位和至少一个子通道选择位; 和控制逻辑。 控制逻辑耦合到多个地址信号线,地址解码器和模式寄存器。 响应于使能位和至少一个子通道选择位,控制逻辑选择一个或多个地址信号线以捕获独立的地址信息,以支持对存储器阵列的独立子通道存储器访问。 控制逻辑将独立的地址信息耦合到地址解码器中。