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41. 发明授权

US6114234A Method of making a semiconductor with copper passivating film 有权
标题翻译：用铜钝化膜制造半导体的方法
公开(公告)号：US6114234A
公开(公告)日：2000-09-05
申请号：US338735
申请日：1999-06-23
申请人： Sailesh M. Merchant , Sudhanshu Misra , Pradip K. Roy
发明人： Sailesh M. Merchant , Sudhanshu Misra , Pradip K. Roy
IPC分类号： H01L21/321 , H01L21/768 , H01L21/4763 , H01L21/302 , H01L21/44 , H01L21/461
CPC分类号： H01L21/7684 , H01L21/3212
摘要： A method of making a semiconductor with a passivating film for copper interconnects includes the step of etching a first set of trench openings within a second oxide layer and then through an etch stop layer that has been deposited over a first oxide layer on a semiconductor substrate. At least a second set of openings are etched in the first oxide layer within the bounds defined by each of a first set of openings. A copper layer is deposited and a passivating film formed on top of the deposited copper layer by depositing one of either a chromate or chromite on the deposited copper layer and forming a respective copper chromate or copper chromite composition. The passivating film is chemically mechanically polished with a slurry containing a respective nitric acid when the passivating film is formed from a chromite and ammonium hydroxide when the passivating film is formed from a chromate.
摘要翻译：制造具有用于铜互连的钝化膜的半导体的方法包括在第二氧化物层内蚀刻第一组沟槽开口，然后通过沉积在半导体衬底上的第一氧化物层上的蚀刻停止层的步骤。在由第一组开口限定的界限内的第一氧化物层中蚀刻至少第二组开口。通过在沉积的铜层上沉积铬酸盐或铬铁矿中的一种并形成各自的铬酸铜或亚铬酸铜组合物，沉积铜层和形成在沉积的铜层的顶部上的钝化膜。当钝化膜由铬酸盐形成时，当钝化膜由铬铁矿和氢氧化铵形成时，钝化膜用含有各自硝酸的浆料进行化学机械抛光。

42. 发明授权

US5913146A Semiconductor device having aluminum contacts or vias and method of manufacture therefor 失效
公开(公告)号：US5913146A
公开(公告)日：1999-06-15
申请号：US820063
申请日：1997-03-18
申请人： Sailesh M. Merchant , Binh Nguyenphu
发明人： Sailesh M. Merchant , Binh Nguyenphu
IPC分类号： H01L21/768 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76882 , H01L21/7684 , H01L23/53223 , H01L2924/0002
摘要： A semiconductor device and a method of manufacture therefor. The semiconductor device includes: (1) a substrate having a recess therein, (2) an aluminum-alloy layer located over at least a portion of the substrate and filling at least a portion of the recess and (3) a protective metal layer at least partially diffused in the aluminum-alloy layer, the metal protective layer having a high affinity for oxygen and acting as a sacrificial target for oxygen during a reflow of the aluminum-alloy layer.

43. 发明申请

US20130155207A1 SYSTEM AND METHOD FOR AUTOMATICALLY CONTROLLING A VIDEO PRESENTATION 审中-公开
标题翻译：用于自动控制视频呈现的系统和方法
公开(公告)号：US20130155207A1
公开(公告)日：2013-06-20
申请号：US13327559
申请日：2011-12-15
申请人： Joseph M. Freund , Roger A. Fratti , Sailesh M. Merchant , Sujal D. Shah
发明人： Joseph M. Freund , Roger A. Fratti , Sailesh M. Merchant , Sujal D. Shah
IPC分类号： H04N13/04
CPC分类号： H04N13/398 , H04N13/332 , H04N13/356
摘要： A system for, and method of automatically controlling a video presentation and 3D glasses incorporating the system or the method. In one embodiment, the system is configured to sense whether a viewer is wearing glasses and transmit a signal to the video source if the viewer is not wearing the glasses. In another embodiment, the system is configured to sense whether the viewer is watching the video presentation and transmit a signal to the video source if the viewer is not watching the video presentation.
摘要翻译：用于自动控制视频呈现的系统和方法以及结合该系统或方法的3D眼镜。在一个实施例中，如果观看者没有佩戴眼镜，则系统被配置为感测观看者是否佩戴眼镜并且将信号发送到视频源。在另一个实施例中，如果观众没有观看视频呈现，则系统被配置为感测观看者是否正在观看视频呈现并且将信号发送到视频源。

44. 发明授权

US07327029B2 Integrated circuit device incorporating metallurigical bond to enhance thermal conduction to a heat sink 有权
标题翻译：集成电路器件结合了金属结合，以增强散热片的热传导
公开(公告)号：US07327029B2
公开(公告)日：2008-02-05
申请号：US11235920
申请日：2005-09-27
申请人： Vance D. Archer, III , Kouros Azimi , Daniel Patrick Chesire , Warren K Gladden , Seung H. Kang , Taeho Kook , Sailesh M. Merchant , Vivian Ryan
发明人： Vance D. Archer, III , Kouros Azimi , Daniel Patrick Chesire , Warren K Gladden , Seung H. Kang , Taeho Kook , Sailesh M. Merchant , Vivian Ryan
IPC分类号： H01L23/34
CPC分类号： H01L23/36 , H01L21/4871 , H01L25/165 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/15311 , H01L2924/16195 , H01L2924/00
摘要： An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.
摘要翻译：一种集成电路装置，其包括冶金结合以增强对散热器的热传导。在半导体器件中，集成电路管芯的表面冶金地结合到散热器的表面。在制造器件的示例性方法中，封装衬底的上表面包括内部区域和周边区域。集成电路管芯位于衬底表面上，并且集成电路管芯的第一表面被放置成与封装衬底接触。金属层形成在集成电路管芯的第二相对表面上。预成型件定位在金属层上，并且散热器位于预制件上。用预成型件形成接合层，将散热器冶金结合到集成电路管芯的第二表面。

45. 发明授权

US07115985B2 Reinforced bond pad for a semiconductor device 有权
公开(公告)号：US07115985B2
公开(公告)日：2006-10-03
申请号：US10955913
申请日：2004-09-30
申请人： Joze E. Antol , Philip William Seitzer , Daniel Patrick Chesire , Rafe Carl Mengel , Vance Dolvan Archer , Thomas B. Gans , Taeho Kook , Sailesh M. Merchant
发明人： Joze E. Antol , Philip William Seitzer , Daniel Patrick Chesire , Rafe Carl Mengel , Vance Dolvan Archer , Thomas B. Gans , Taeho Kook , Sailesh M. Merchant
IPC分类号： H01L23/12 , H01L23/053 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L23/3171 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/451 , H01L2224/48463 , H01L2224/49175 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2224/45099 , H01L2924/00015
摘要： Disclosed herein are novel support structures for pad reinforcement in conjunction with new bond pad designs for semiconductor devices. The new bond pad designs avoid the problems associated with probe testing by providing a probe region that is separate from a wire bond region. Separating the probe region 212 from the wire bond region 210 and forming the bond pad 211 over active circuitry has several advantages. By separating the probe region 212 from the wire bond region 210, the wire bond region 210 is not damaged by probe testing, allowing for more reliable wire bonds. Also, forming the bond pad 211 over active circuitry, including metal interconnect layers, allows the integrated circuit to be smaller.

46. 发明授权

US07061264B2 Test semiconductor device and method for determining Joule heating effects in such a device 有权
标题翻译：测试这种器件中的焦耳加热效应的半导体器件和方法
公开(公告)号：US07061264B2
公开(公告)日：2006-06-13
申请号：US10953292
申请日：2004-09-29
申请人： Seung H. Kang , Subramanian Karthikeyan , Sailesh M. Merchant
发明人： Seung H. Kang , Subramanian Karthikeyan , Sailesh M. Merchant
IPC分类号： G01R31/26
CPC分类号： G01R31/2877 , G01R31/2853 , G01R31/2856 , H01L22/32
摘要： Method and test structures for determining heating effects in a test semiconductor device (10) are provided. The test device may include a first conductive metal structure (151–156) for accepting a flow of electric current that causes a heating effect. The test device may further include a second conductive metal structure proximate (121–126) the first conductive structure for obtaining resistivity changes in response to the heating effect. The resistivity changes are indicative of temperature changes due to the heating effect.
摘要翻译：提供了用于确定测试半导体器件（10）中的加热效应的方法和测试结构。测试装置可以包括用于接受引起加热效应的电流的第一导电金属结构（15 SUB-15,6）。测试装置还可以包括靠近第一导电结构的第二导电金属结构，用于响应于加热效应而获得电阻率变化。电阻率变化表示由于加热效应引起的温度变化。

47. 发明授权

US06784478B2 Junction capacitor structure and fabrication method therefor in a dual damascene process 有权
标题翻译：板式电容器结构及其制造方法在双镶嵌工艺中
公开(公告)号：US06784478B2
公开(公告)日：2004-08-31
申请号：US10260693
申请日：2002-09-30
申请人： Sailesh M. Merchant , Yifeng W. Yan
发明人： Sailesh M. Merchant , Yifeng W. Yan
IPC分类号： H01L27108
CPC分类号： H01L28/60 , H01L21/76807 , H01L21/76895 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and fabrication process for a capacitor formed in conjunction with a dual damascene process. A bottom capacitor plate is electrically connected to an overlying first conductive via formed according to the dual damascene process. A top capacitor plate is connected to an overlying second conductive via. A dielectric material is disposed between the top and the bottom plates. The capacitor is formed by successively forming the bottom plate, the dielectric layer, and the top plate, patterning these layers as required after their formation. The first conductive via is formed over and electrically connected to the bottom plate and the second conductive via is formed over and connected to the top capacitor plate thereby providing for interconnection of the capacitor to other circuit elements by way of the dual damascene conductive runners connected to the conductive vias.
摘要翻译：一种与双镶嵌工艺结合形成的电容器的装置和制造方法。底部电容器电极电连接到根据双镶嵌工艺形成的上覆的第一导电通孔。顶部电容器板连接到上覆的第二导电通孔。介电材料设置在顶板和底板之间。电容器通过依次形成底板，电介质层和顶板形成，在形成之后根据需要对这些层进行图案化。第一导电通孔形成在底板上并电连接到底板，并且第二导电通孔形成在顶部电容器板上并连接到顶部电容器板，从而通过连接到第二导电通孔的双镶嵌导电流道提供电容器与其它电路元件的互连导电通孔。

48. 发明授权

US06703712B2 Microelectronic device layer deposited with multiple electrolytes 有权
标题翻译：微电子器件层沉积有多个电解质
公开(公告)号：US06703712B2
公开(公告)日：2004-03-09
申请号：US10008015
申请日：2001-11-13
申请人： Daniele Gilkes , Minseok Oh , Sailesh M. Merchant
发明人： Daniele Gilkes , Minseok Oh , Sailesh M. Merchant
IPC分类号： H01L2348
CPC分类号： H01L21/76877 , H01L21/2885
摘要： A microelectronic device (24) is formed by plating a layer of material (36) to fill a cavity (28) formed in a substrate (26). The layer of material has a plurality of regions (42, 44, 46) with respective chemical compositions formed by varying the chemical composition of the plating solution as the layer of material is being deposited. In this manner, expensive additives necessary to achieve desired properties within the cavity may be omitted from the region (46) of overfill that will be removed by a later planarization process.
摘要翻译：微电子器件（24）通过电镀一层材料（36）以填充形成在衬底（26）中的空腔（28）而形成。材料层具有多个区域（42,44,46），其具有通过随着材料层的沉积而改变镀液的化学组成而形成各自的化学组成。以这种方式，可以从将通过稍后的平坦化处理除去的过量填充区域（46）中省略在空腔内实现所需性质所需的昂贵的添加剂。

49. 发明授权

US06495875B2 Method of forming metal oxide metal capacitors using multi-step rapid material thermal process and a device formed thereby 有权
标题翻译：使用多步快速材料热处理形成金属氧化物金属电容器的方法和由此形成的器件
公开(公告)号：US06495875B2
公开(公告)日：2002-12-17
申请号：US09962641
申请日：2001-09-25
申请人： Siddhartha Bhowmik , Sailesh M. Merchant , Pradip K. Roy , Sidhartha Sen
发明人： Siddhartha Bhowmik , Sailesh M. Merchant , Pradip K. Roy , Sidhartha Sen
IPC分类号： H01L2976
CPC分类号： H01L28/40
摘要： The present invention provides a method of forming a metal oxide metal (MOM)capacitor on a substrate, such as a silicon substrate, of a semiconductor wafer in a rapid thermal process (RTP) machine. The MOM capacitor is fabricated by forming a metal layer on the semiconductor substrate. The metal layer is then subjected to a first rapid thermal process in a substantially inert but nitrogen-free atmosphere that consumes a portion of the metal layer to form a first metal electrode layer and a silicide layer between the first metal electrode and the semiconductor substrate. The semiconductor wafer is then subjected to a second rapid thermal process. During this process, the remaining portion of the metal layer is oxidized to form a metal oxide on the first metal electrode, which serves as the dielectric layer of the MOM capacitor. Following the formation of the dielectric layer, a second metal electrode layer is then conventionally formed on the metal oxide, which completes the formation of the MOM capacitor. Preferably, the first electrode layer and the metal oxide layer are formed in a single RTP machine.
摘要翻译：本发明提供了一种在快速热处理（RTP）机器中在半导体晶片的衬底（例如硅衬底）上形成金属氧化物金属（MOM）电容器的方法。通过在半导体衬底上形成金属层来制造MOM电容器。然后在基本惰性但无氮的气氛中对金属层进行第一快速热处理，其消耗金属层的一部分以在第一金属电极和半导体衬底之间形成第一金属电极层和硅化物层。然后对半导体晶片进行第二快速热处理。在该过程中，金属层的剩余部分被氧化，在作为MOM电容器的电介质层的第一金属电极上形成金属氧化物。在形成电介质层之后，通常在金属氧化物上形成第二金属电极层，从而完成MOM电容器的形成。优选地，第一电极层和金属氧化物层在单个RTP机器中形成。

50. 发明授权

US06340827B1 Diffusion barrier for use with high dielectric constant materials and electronic devices incorporating same 有权
标题翻译：用于高介电常数材料的扩散阻挡层和结合其的电子器件
公开(公告)号：US06340827B1
公开(公告)日：2002-01-22
申请号：US09478647
申请日：2000-01-06
申请人： Seungmoo Choi , Sailesh M. Merchant , Pradip K. Roy
发明人： Seungmoo Choi , Sailesh M. Merchant , Pradip K. Roy
IPC分类号： H01L3300
CPC分类号： H01L28/40 , H01L21/28568
摘要： A diffusion barrier for preventing the diffusion of oxygen from a high dielectric constant material to a titanium nitride layer. The diffusion barrier comprises one or more layers, wherein each of the one or more layers comprises a material selected from the group consisting of metal carbide, metal nitride, metal boride, metal carbo-nitride, and silicon carbide. The high dielectric constant material may be tantalum pentoxide or any perkovskite-type high dielectric constant material.
摘要翻译：用于防止氧从高介电常数材料扩散到氮化钛层的扩散屏障。扩散阻挡层包括一层或多层，其中一层或多层中的每层包括选自金属碳化物，金属氮化物，金属硼化物，金属碳氮化物和碳化硅的材料。高介电常数材料可以是五氧化二钽或任何一种钙钛矿型高介电常数材料。

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