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41. 发明授权

US5427965A Method of fabricating a complementary heterojunction FET 失效
标题翻译：制造互补异质结FET的方法
公开(公告)号：US5427965A
公开(公告)日：1995-06-27
申请号：US262292
申请日：1994-06-20
申请人： Saied N. Tehrani , X. T. Zhu , Herbert Goronkin , Jun Shen
发明人： Saied N. Tehrani , X. T. Zhu , Herbert Goronkin , Jun Shen
IPC分类号： H01L29/80 , H01L27/06 , H01L27/092 , H01L27/095 , H01L21/265 , H01L21/20
CPC分类号： H01L27/0605 , H01L27/092 , Y10S148/015 , Y10S148/072 , Y10S148/16
摘要： A heterojunction device including a first semiconductive layer on a substrate, a barrier layer on the first layer, a second semiconductive layer on the barrier layer and a multi-layer cap, on the second semiconductive layer. First and second gates positioned on layers of the cap to define first and second transistors, with the cap layers being selected and etched to pin the Fermi level in a first transistor conduction channel in the second semiconductive layer such that the number of carriers in the first conduction channel are substantially less than the number of carriers in surrounding portions of the second semiconductive layer and the Fermi level in a second transistor conduction channel in the first semiconductive layer such that the number of carriers in the second conduction channel are substantially less than the number of carriers in surrounding portions of the first semiconductive layer.
摘要翻译：一种异质结装置，在第二半导体层上包括衬底上的第一半导体层，第一层上的阻挡层，阻挡层上的第二半导体层和多层帽。位于盖的层上的第一和第二栅极限定第一和第二晶体管，其中盖层被选择和蚀刻以在第二半导体层中的第一晶体管导通通道中引导费米能级，使得第一和第二晶体管中的载流子数目传导通道基本上小于第一半导体层中的第二半导体层的周围部分中的载流子数量和第二晶体管传导通道中的费米能级数，使得第二导电通道中的载流子数目基本上小于数量在第一半导体层的周围部分的载体。

42. 发明授权

US5410160A Interband tunneling field effect transistor 失效
标题翻译：带间隧道场效应晶体管
公开(公告)号：US5410160A
公开(公告)日：1995-04-25
申请号：US894963
申请日：1992-06-08
申请人： Herbert Goronkin , Jun Shen , Saied N. Tehrani , X. Theodore Zhu
发明人： Herbert Goronkin , Jun Shen , Saied N. Tehrani , X. Theodore Zhu
IPC分类号： H01L29/80 , H01L29/739 , H01L29/772 , H01L29/161 , H01L29/205 , H01L29/225
CPC分类号： H01L29/772 , H01L29/739
摘要： A field effect semiconductor device having multiple vertically stacked channels (12, 14, 16) separated by barrier layers comprising wide bandgap material (18) is provided. The channels (12, 14, 16) are formed on a wide bandgap buffer layer (11) and each channel is coupled a P-type drain region (22b). Each channel is also coupled to an N-type source region (25b). With appropriate gate bias on a gate electrode (17), quantized energy levels in the channels (12, 14, 16) are aligned providing peak current flow by electrons tunneling from the conduction band of one or more N-channels (12, 16) to the valence band of the P-channel (14).
摘要翻译：提供了具有由包括宽带隙材料（18）的阻挡层分开的多个垂直堆叠通道（12,14,16）的场效应半导体器件。通道（12,14,16）形成在宽带隙缓冲层（11）上，每个通道耦合有P型漏极区域（22b）。每个通道也耦合到N型源极区域（25b）。在栅电极（17）上具有适当的栅极偏置，通道（12,14,16）中的量化能级对齐，从一个或多个N沟道（12,16）的导带隧穿的电子提供峰值电流，到P沟道（14）的价带。

43. 发明授权

US5298441A Method of making high transconductance heterostructure field effect transistor 失效
标题翻译：制造高跨导异质结场场效应晶体管的方法
公开(公告)号：US5298441A
公开(公告)日：1994-03-29
申请号：US709741
申请日：1991-06-03
申请人： Herbert Goronkin , Jun Shen , Saied N. Tehrani , X. Theodore Zhu
发明人： Herbert Goronkin , Jun Shen , Saied N. Tehrani , X. Theodore Zhu
IPC分类号： H01L29/772 , H01L21/265
CPC分类号： H01L29/7725 , Y10S148/097
摘要： A high transconductance HFET (21) utilizes nonalloy semiconductor materials (26) to form a strained channel layer (26) that has a deep quantum well (38). The materials utilized for layers adjacent to the channel layer (26) apply strain to the channel layer (26) and create an excess of high mobility carriers in the channel layer (26). The materials also form a deep quantum well (38) that confines the high mobility carriers to the channel (26). The high mobility carriers and the high confinement provide an HFET (21) that has high transconductance, high frequency response, and sharp pinch-off characteristics.
摘要翻译：高跨导HFET（21）利用非合金半导体材料（26）形成具有深量子阱（38）的应变通道层（26）。用于与沟道层（26）相邻的层的材料对沟道层（26）施加应变，并在沟道层（26）中产生过量的高迁移率载流子。这些材料还形成将高迁移率载流子限制到通道（26）的深量子阱（38）。高迁移率载流子和高限制性提供了具有高跨导，高频响应和清晰夹断特性的HFET（21）。

44. 发明授权

US06812040B2 Method of fabricating a self-aligned via contact for a magnetic memory element 失效
标题翻译：制造用于磁存储元件的自对准通孔接点的方法
公开(公告)号：US06812040B2
公开(公告)日：2004-11-02
申请号：US10095816
申请日：2002-03-12
申请人： Kelly Kyler , Saied N. Tehrani , John J. D'urso , Gregory W. Grynkewich , Mark A. Durlam , Brian Butcher
发明人： Kelly Kyler , Saied N. Tehrani , John J. D'urso , Gregory W. Grynkewich , Mark A. Durlam , Brian Butcher
IPC分类号： H01L2100
CPC分类号： H01L43/12 , B82Y10/00
摘要： A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a conductive layer positioned on the substrate, forming a magnetoresistive random access memory device positioned on conductive layer, forming a metal cap on the magnetoresistive random access memory device, and electroless plating a bump metal layer on the metal cap. The bump metal layer acts as a self-aligned via for a bit line subsequently formed thereon.
摘要翻译：一种制造磁阻随机存取存储器件的方法，包括以下步骤：提供衬底，形成位于衬底上的导电层，形成位于导电层上的磁阻随机存取存储器件，在磁阻随机存取存储器件上形成金属帽并且在金属盖上化学镀覆凸块金属层。凸块金属层用作随后在其上形成的位线的自对准通孔。

45. 发明授权

US5943574A Method of fabricating 3D multilayer semiconductor circuits 失效
标题翻译：制造3D多层半导体电路的方法
公开(公告)号：US5943574A
公开(公告)日：1999-08-24
申请号：US27915
申请日：1998-02-23
申请人： Saied N. Tehrani , Kumar Shiralagi , Herbert Goronkin
发明人： Saied N. Tehrani , Kumar Shiralagi , Herbert Goronkin
IPC分类号： H01L21/336 , H01L21/768 , H01L27/06 , H01L27/092 , H01L29/786
CPC分类号： H01L29/6675 , H01L21/76838 , H01L27/0688 , H01L27/0922 , H01L29/78642
摘要： A method of fabricating 3D semiconductor circuits including providing a conductive layer with doped polysilicon thereon patterned and annealed to form first single grain polysilicon terminals of semiconductor devices. Insulated gate contacts are spaced vertically from the terminals so as to define vertical vias and polysilicon is deposited in the vias to form conduction channels. An upper portion of the polysilicon in the vias is doped to form second terminals for the semiconductor devices, and the polysilicon is annealed to convert it to single grain polysilicon. A second electrically conductive layer is deposited and patterned on the second terminal to define second terminal contacts of the semiconductor devices.
摘要翻译：一种制造3D半导体电路的方法，包括向其上形成有导电层的掺杂多晶硅进行图案化和退火，以形成半导体器件的第一单晶多晶硅端子。绝缘栅极触点与端子垂直间隔开，以便限定垂直通孔，并且多孔沉积在通孔中以形成传导通道。通孔中的多晶硅的上部被掺杂以形成用于半导体器件的第二端子，并且将多晶硅退火以将其转换成单晶粒多晶硅。在第二端子上沉积和图案化第二导电层以限定半导体器件的第二端子触点。

46. 发明授权

US5831295A Current confinement via defect generator and hetero-interface interaction 失效
标题翻译：通过缺陷发生器和异质界面相互作用的电流限制
公开(公告)号：US5831295A
公开(公告)日：1998-11-03
申请号：US566388
申请日：1995-12-01
申请人： Jenn-Hwa Huang , Saied N. Tehrani
发明人： Jenn-Hwa Huang , Saied N. Tehrani
IPC分类号： H01L23/62 , H01L31/0328 , H01L23/48 , H01L31/0336
CPC分类号： H01L23/62 , H01L2924/0002
摘要： A semiconductor device including a plurality of layers of material defining a diffusion barrier. A defect generator positioned on the plurality of layers in overlying relationship to the diffusion barrier so as to produce a collection of defects at the diffusion barrier that operates as a current restriction. In a typical example, an ohmic contact is positioned around the mesa of a ridge VCSEL, which ohmic contact generates defects that accumulate at a hetero-interface near the active area and confine the current flow to a lasing volume of the VCSEL.
摘要翻译：一种包括限定扩散阻挡层的多层材料的半导体器件。一种缺陷发生器，其以与扩散阻挡层重叠的关系位于多个层上，以便在作为电流限制的扩散阻挡层产生缺陷的集合。在典型的示例中，欧姆接触定位在脊VCSEL的台面周围，该欧姆接触产生在有源区附近的异质界面处积累的缺陷，并将电流限制到VCSEL的激光体积。

47. 发明授权

US5768181A Magnetic device having multi-layer with insulating and conductive layers 失效
标题翻译：具有多层绝缘导电层的磁性器件
公开(公告)号：US5768181A
公开(公告)日：1998-06-16
申请号：US834968
申请日：1997-04-07
申请人： Theodore Zhu , Saied N. Tehrani
发明人： Theodore Zhu , Saied N. Tehrani
IPC分类号： G11C11/15 , G11C11/56 , G11C7/00
CPC分类号： G11C11/15 , G11C11/5607 , G11C2211/5615
摘要： A magnetic device (40) having multi-layer (41-45) with insulating layer (45) and conductive layer (42). The conductive layer (42) is positioned between a first magnetic layer (41) and a third magnetic layer (44). The insulating layer (45) is positioned between a second magnetic layer (43) and the third magnetic layer (44), and which forms a tunnel junction between the second and third layers. Magnetic vectors in the first magnetic layer (41) magnetically couple with ones in the second magnetic layer (43) so that the magnetic coupling loop formed around the third magnetic layer (44) allows magnetic vectors in the third magnetic layer (44) to be switchable in a low magnetic field. Consequently, total power consumption of the magnetic device (60) decreases.
摘要翻译：具有绝缘层（45）和导电层（42）的具有多层（41-45）的磁性装置（40）。导电层（42）位于第一磁性层（41）和第三磁性层（44）之间。绝缘层（45）位于第二磁性层（43）和第三磁性层（44）之间，并且在第二层和第三层之间形成隧道结。第一磁性层（41）中的磁矢量与第二磁性层（43）中的磁性磁耦合，使得围绕第三磁性层（44）形成的磁耦合环允许第三磁性层（44）中的磁矢量为可在低磁场中切换。因此，磁性装置（60）的总功耗降低。

48. 发明授权

US5748519A Method of selecting a memory cell in a magnetic random access memory device 失效
标题翻译：选择磁性随机存取存储器件中的存储单元的方法
公开(公告)号：US5748519A
公开(公告)日：1998-05-05
申请号：US766637
申请日：1996-12-13
申请人： Saied N. Tehrani , Herbert Goronkin
发明人： Saied N. Tehrani , Herbert Goronkin
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L21/78
CPC分类号： G11C11/15
摘要： Improved methods for selecting memory cells in magnetic random access memory (MRAM) are provided. Whenever a state in a memory cell is sensed, a MRAM requires to adjust an output of comparator to a zero voltage (auto-zeroing step) before the content of memory cell is detected. This invention sequentially accesses memory cells 29-30 once sense line 25 is selected and auto-zeroed. Accordingly, a higher speed operation is attained because the invention does not require an auto-zeroing step every sensing a memory cell.
摘要翻译：提供了用于选择磁随机存取存储器（MRAM）中的存储单元的改进方法。每当检测到存储单元中的状态时，MRAM需要在检测到存储器单元的内容之前将比较器的输出调整为零电压（自动调零步骤）。一旦感测线25被选择并自动归零，本发明顺序地访问存储器单元29-30。因此，由于本发明不需要每次感测存储单元的自动归零步骤，所以实现了更高的速度操作。

49. 发明授权

US5659179A Ultra-small semiconductor devices having patterned edge planar surfaces 失效
标题翻译：具有图案化边缘平坦表面的超小型半导体器件
公开(公告)号：US5659179A
公开(公告)日：1997-08-19
申请号：US399809
申请日：1995-03-07
申请人： Herbert Goronkin , Saied N. Tehrani , Martin Walther , Raymond Tsui
发明人： Herbert Goronkin , Saied N. Tehrani , Martin Walther , Raymond Tsui
IPC分类号： H01L29/06 , H01L21/329 , H01L27/06 , H01L29/88
CPC分类号： H01L29/66219 , H01L27/0605 , H01L29/882
摘要： Ultra-small semiconductor devices and a method of fabrication including patterning the planar surface of a substrate to form a pattern edge (e.g. a mesa) and consecutively forming a plurality of layers of semiconductor material in overlying relationship to the pattern edge so that a discontinuity is produced in the layers and a first layer on one side of the pattern edge is aligned with and in electrical contact with a different layer on the other side of the pattern edge.
摘要翻译：超小型半导体器件和制造方法包括图案化衬底的平坦表面以形成图案边缘（例如台面）并且以与图案边缘重叠的关系连续地形成多个半导体材料层，使得不连续性为在图案边缘的一侧上产生的层和第一层与图案边缘的另一侧上的不同层对准并与之接触。

50. 发明授权

US5326985A Bipolar doped semiconductor structure and method for making 失效
标题翻译：双极掺杂半导体结构及其制造方法
公开(公告)号：US5326985A
公开(公告)日：1994-07-05
申请号：US951994
申请日：1992-09-28
申请人： Herbert Goronkin , Jun Shen , Saied N. Tehrani
发明人： Herbert Goronkin , Jun Shen , Saied N. Tehrani
IPC分类号： H01L29/778 , H01L29/161 , H01L29/205
CPC分类号： H01L29/7783
摘要： A semiconductor structure that provides both N-type and P-type doping from a single dopant source is provided. A first doping region (13) comprising a first material composition includes holes and electrons in a doping energy level (E.sub.D)- A first undoped spacer region (12) comprising the first material composition covers the doping region (13). An undoped channel (11,14) comprising a second material composition covers the first spacer region (12) and a second undoped spacer region (12) comprising the first material composition covers the undoped channel (11,14). The first material composition has a wider bandgap than the second material composition and the doping energy level (E.sub.D) is selected to provide electrons to the undoped channel (11,14) when the second material composition has a conduction band minimum less than the doping energy level (E.sub.D) and to provide holes to the first undoped channel (11,14) when the second material composition has a valence band maximum greater than the doping energy level (E.sub.D).
摘要翻译：提供了从单个掺杂剂源提供N型和P型掺杂的半导体结构。包括第一材料组合物的第一掺杂区域（13）包括掺杂能级（ED）的空穴和电子 - 包含第一材料组合物的第一未掺杂间隔区域（12）覆盖掺杂区域（13）。包括第二材料组合物的未掺杂通道（11,14）覆盖第一间隔区域（12），并且包括第一材料组合物的第二未掺杂间隔区域（12）覆盖未掺杂沟道（11,14）。第一材料组合物具有比第二材料组成更宽的带隙，并且当第二材料组合物具有小于掺杂能量的导带最小值时，选择掺杂能级（ED）以向未掺杂沟道（11,14）提供电子（ED），并且当第二材料组合物具有大于掺杂能级（ED）的价带最大值时，向第一未掺杂通道（11,14）提供孔。

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