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    • 45. 发明申请
    • Self-aligned cell integration scheme
    • 自对准单元集成方案
    • US20060281256A1
    • 2006-12-14
    • US11312849
    • 2005-12-20
    • Richard CarterHemanshu BhattShiqun GuPeter BurkeJames ElmerSey-Shing SunByung-Sung KwakVerne Hornback
    • Richard CarterHemanshu BhattShiqun GuPeter BurkeJames ElmerSey-Shing SunByung-Sung KwakVerne Hornback
    • H01L21/336
    • H01L51/0018B82Y10/00H01L27/283H01L51/0048H01L51/0545Y10S977/742
    • A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.
    • 一种形成自对准逻辑单元的方法。 在底部电极上形成纳米管层。 在纳米管层上形成夹层。 夹层覆盖纳米管层,从而保护纳米管层。 在钳位层上形成电介质层。 蚀刻介电层。 钳位层提供蚀刻停止并保护纳米管层。 用各向同性蚀刻剂蚀刻钳夹层,蚀刻介质层下方的夹层,产生电介质层的重叠,并引起钳位层和电介质层之间的自对准。 在纳米管层上形成间隔层。 除了围绕电介质层的边缘的环形部分之外,蚀刻间隔层。 除了夹持层,电介质层和间隔层中的至少一个的部分以外,蚀刻纳米管层,从而导致夹紧层之间的自对准,与电介质层的重叠,间隔层, 和纳米管层。