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41. 发明授权

US06576943B1 Semiconductor device for reducing leak currents and controlling a threshold voltage and using a thin channel structure 失效
标题翻译：用于减少泄漏电流并控制阈值电压并使用薄沟道结构的半导体器件
公开(公告)号：US06576943B1
公开(公告)日：2003-06-10
申请号：US09512827
申请日：2000-02-25
申请人： Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
发明人： Tomoyuki Ishii , Kazuo Yano , Toshiyuki Mine
IPC分类号： H01L27108
CPC分类号： G11C16/0433 , H01L27/105 , H01L27/108 , H01L27/10873 , H01L27/12 , H01L27/1203 , H01L29/78642
摘要： A very thin semiconductor film is used for channels of semiconductor memory elements such that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. The amount of electrical charge accumulated in each charge accumulating region is used to change the conductance between a source region and a drain region of each read transistor structure. This conductance change is utilized for data storage. The thickness of the channel of the write transistor structure is preferably no more than 5 nm. According to one embodiment, the channel of the write transistor is formed by a semiconductor film deposited on a surface intersecting a principal plane of the substrate.
摘要翻译：非常薄的半导体膜用于半导体存储元件的通道，使得漏电流通过膜厚度方向的量子力学容纳效应而降低。使用在每个电荷累积区域中累积的电荷量来改变每个读取的晶体管结构的源极区域和漏极区域之间的电导。该电导变化用于数据存储。写入晶体管结构的沟道的厚度优选不大于5nm。根据一个实施例，写入晶体管的沟道由沉积在与衬底的主平面相交的表面上的半导体膜形成。

42. 发明授权

US06211531B1 Controllable conduction device 失效
标题翻译：可控导通装置
公开(公告)号：US06211531B1
公开(公告)日：2001-04-03
申请号：US09492171
申请日：2000-01-27
申请人： Kazuo Nakazato , Kiyoo Itoh , Hiroshi Mizuta , Toshikazu Shimada , Hideo Sunami , Tatsuya Teshima , Toshiyuki Mine , Ken Yamaguchi
发明人： Kazuo Nakazato , Kiyoo Itoh , Hiroshi Mizuta , Toshikazu Shimada , Hideo Sunami , Tatsuya Teshima , Toshiyuki Mine , Ken Yamaguchi
IPC分类号： H01L2906
CPC分类号： H01L27/10858 , B82Y10/00 , G11C11/16 , H01L21/28273 , H01L27/10808 , H01L27/1082 , H01L27/10873 , H01L27/10876 , H01L27/11 , H01L29/154 , H01L29/42324 , H01L29/66825 , H01L29/772 , H01L29/78609 , H01L29/78618 , H01L29/78642 , H01L29/78687 , H01L29/7881 , H01L29/882
摘要： A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.
摘要翻译：晶体管形式的可控导电器件包括源极和漏极区域5，其间延伸用于电荷载流子的导电路径P，用于控制沿导电路径的电荷载流子的栅极4和提供多个导通路径中的隧道结结构，结果当晶体管处于其截止状态时，漏电流被多重隧道结构造阻塞。描述了垂直和横向晶体管配置，以及使用晶体管的互补对和随机存取存储器单元。描述了改进的栅极结构，其也适用于结合隧道势垒配置以在存储器节点上存储电荷的存储器件。

43. 发明授权

US4907046A Semiconductor device with multilayer silicon oxide silicon nitride dielectric 失效
标题翻译：具有多层氧化硅氮化硅电介质的半导体器件
公开(公告)号：US4907046A
公开(公告)日：1990-03-06
申请号：US168490
申请日：1988-03-15
申请人： Yuzuru Ohji , Osamu Kasahara , Yoshitaka Tadaki , Hiroko Kaneko , Toshiyuki Mine , Kunihiro Yagi
发明人： Yuzuru Ohji , Osamu Kasahara , Yoshitaka Tadaki , Hiroko Kaneko , Toshiyuki Mine , Kunihiro Yagi
IPC分类号： H01L27/04 , F02B3/06 , H01L21/318 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/51 , H01L29/92 , H01L29/78 , H01L27/02 , H01L29/34
CPC分类号： H01L28/40 , H01L27/10808 , F02B3/06 , H01L29/51
摘要： A solid state device includes a transistor (A) and a capacitor (B). The capacitor is defined by a lower polycrystalline silicon layer or electrode (20), multiple dielectric layers (22), and an upper polycrystalline silicon layer or electrode (30). The dielectric layers are formed by vapor depositing a 3.6-18.6 nm thick layer of silicon nitride on the lower polycrystalline layer. Thicker silicon nitride layers increase the failure rate and decrease the capacitance (FIG. 8). More specifically, the silicon nitride layer is deposited on a thin, about 1 nm, oxidized film or surface (24) of the polycrystalline silicon layer. The silicon nitride layer is oxidized forming a silicon dioxide layer (28) until the silicon nitride layer is only about 3 nm thick. This forms on oxide layer that is 1-8.4 nm thick. If the silicon nitride layer is reduced below 3 nm, the polycrystalline silicon tends to oxidize rapidly reducing capacitance and increasing failure (FIG. 8).
摘要翻译：固态器件包括晶体管（A）和电容器（B）。电容器由下多晶硅层或电极（20），多个电介质层（22）和上多晶硅层或电极（30）限定。电介质层通过在下多晶层上气相沉积3.6-18.6nm厚的氮化硅层形成。较厚的氮化硅层增加故障率并降低电容（图8）。更具体地，氮化硅层沉积在多晶硅层的薄的约1nm的氧化膜或表面（24）上。氧化氮化硅层形成二氧化硅层（28），直到氮化硅层仅为约3nm厚。这在氧化层上形成，厚度为1-8.4nm。如果氮化硅层减小到3nm以下，则多晶硅容易迅速氧化，降低电容并增加故障（图8）。

44. 发明申请

US20150179744A1 MOS FIELD EFFECT TRANSISTOR 有权
标题翻译： MOS场效应晶体管
公开(公告)号：US20150179744A1
公开(公告)日：2015-06-25
申请号：US14413435
申请日：2012-07-09
申请人： Toshiyuki Mine , Yasuhiro Shimamoto , Hirotaka Hamamura
发明人： Toshiyuki Mine , Yasuhiro Shimamoto , Hirotaka Hamamura
IPC分类号： H01L29/16 , H01L29/51 , H01L29/423 , H01L29/78 , H01L29/10
CPC分类号： H01L29/1608 , H01L29/0657 , H01L29/1079 , H01L29/12 , H01L29/4236 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/66068 , H01L29/78 , H01L29/7802 , H01L29/7813 , H01L29/7926
摘要： The present invention is to cause high channel mobility and a high threshold voltage to coexist in a SiC-MOSFET power device which uses a SiC substrate. The SiC MOSFET which is provided with a layered insulation film having electric charge trap characteristics on a gate insulation film has an irregular threshold voltage in a channel length direction of the SiC MOSFET, and in particular, has a shorter area having a maximum threshold voltage in the channel length direction compared to an area having other threshold voltages.
摘要翻译：本发明是在使用SiC衬底的SiC-MOSFET功率器件中使高通道迁移率和高阈值电压共存。在栅极绝缘膜上具有电荷陷阱特性的分层绝缘膜的SiC MOSFET在SiC MOSFET的沟道长度方向上具有不规则的阈值电压，特别是具有最小阈值电压的较短区域通道长度方向与具有其它阈值电压的区域相比较。

45. 发明申请

US20150044840A1 METHOD FOR PRODUCING SILICON CARBIDE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：生产碳化硅半导体器件的方法
公开(公告)号：US20150044840A1
公开(公告)日：2015-02-12
申请号：US14381597
申请日：2012-03-30
申请人： Keisuke Kobayashi , Toshiyuki Mine , Hirotaka Hamamura
发明人： Keisuke Kobayashi , Toshiyuki Mine , Hirotaka Hamamura
IPC分类号： H01L29/66 , H01L21/02 , H01L21/265 , H01L29/16
CPC分类号： H01L29/66477 , H01L21/02057 , H01L21/0223 , H01L21/02236 , H01L21/02252 , H01L21/046 , H01L21/049 , H01L21/26513 , H01L21/30604 , H01L29/1608 , H01L29/66053 , H01L29/66068 , H01L29/78 , H01L29/7827
摘要： In order to provide a method for producing a SiC-MOSFET capable of increasing Vth without deteriorating channel mobility, before forming a gate insulation film, (a) silicon carbide substrate is oxidized by a low temperature oxidation method represented by plasma oxidation to form a silicon oxide film. Next, (b) the silicon oxide film is removed. After repeating the processes (a) and (b) once or more, (c) the gate insulation film is formed.
摘要翻译：为了提供能够增加Vth而不劣化沟道迁移率的SiC-MOSFET的制造方法，在形成栅极绝缘膜之前，（a）碳化硅衬底被等离子体氧化所代表的低温氧化法氧化，形成硅氧化膜。接下来，（b）去除氧化硅膜。重复（a）和（b）工序一次以上后，（c）形成栅极绝缘膜。

46. 发明授权

US08790948B2 Method for manufacturing a solar cell 有权
标题翻译：制造太阳能电池的方法
公开(公告)号：US08790948B2
公开(公告)日：2014-07-29
申请号：US13303227
申请日：2011-11-23
申请人： Keiji Watanabe , Toshiyuki Mine , Akio Shima , Tomoko Sekiguchi , Ryuta Tsuchiya
发明人： Keiji Watanabe , Toshiyuki Mine , Akio Shima , Tomoko Sekiguchi , Ryuta Tsuchiya
IPC分类号： H01L21/00
CPC分类号： H01L31/02168 , B82Y20/00 , H01L31/0352 , H01L31/035236 , H01L31/055 , H01L31/075 , H01L31/1872 , Y02E10/52 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： In the existent method for manufacturing a solar cell, manufacture of a solar cell having a quantum well having a crystalline well layer and capable of controlling the thickness of the well layer was difficult. A quantum well having an amorphous well layer, comprising a barrier layer and an amorphous well layer is formed and then the quantum well having the amorphous well layer is annealed thereby crystallizing the amorphous well layer to form a quantum well having a crystalline well layer. By applying energy density applied to the amorphous well layer at an energy density of 1.26 J/mm2 or more and 28.8 J/mm2 or less, the crystalline well layer can be formed and the lamination structure of the quantum well can be maintained simultaneously.
摘要翻译：在制造太阳能电池的现有方法中，难以制造具有具有结晶阱层并能够控制阱层的厚度的量子阱的太阳能电池。形成具有非晶阱层的量子阱，其包含阻挡层和非晶阱层，然后对具有非晶阱层的量子阱退火，从而使非晶阱层结晶，形成具有结晶阱层的量子阱。通过以1.26J / mm 2以上且28.8J / mm 2以下的能量密度施加到非晶质阱层的能量密度，可以形成结晶阱层，同时可以维持量子阱的层叠结构。

47. 发明授权

US08409949B2 Non-volatile semiconductor memory device and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08409949B2
公开(公告)日：2013-04-02
申请号：US12822157
申请日：2010-06-23
申请人： Tsuyoshi Arigane , Digh Hisamoto , Yasuhiro Shimamoto , Toshiyuki Mine
发明人： Tsuyoshi Arigane , Digh Hisamoto , Yasuhiro Shimamoto , Toshiyuki Mine
IPC分类号： H01L21/336
CPC分类号： H01L29/42328 , G11C16/3418 , H01L27/11521 , H01L27/1203 , H01L29/7883
摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).
摘要翻译：提供了高度集成且高度可靠的非易失性半导体存储器件。多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散层（n +型半导体区）也与阱（p型半导体区）电连接。

48. 发明授权

US08089067B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08089067B2
公开(公告)日：2012-01-03
申请号：US12318452
申请日：2008-12-30
申请人： Shinichi Saito , Hiroyuki Uchiyama , Toshiyuki Mine
发明人： Shinichi Saito , Hiroyuki Uchiyama , Toshiyuki Mine
IPC分类号： H01L33/00
CPC分类号： H01L27/156 , H01L33/16 , H01L33/34
摘要： A self emission silicon emission display is provided at a low price, which contains silicon and oxygen which exist in abundance on the earth as the main component and which can be easily formed by conventional silicon process. A light emission element includes a first electrode for injecting electrons, a second electrode for injecting holes, and a light emission part electrically connected to the first electrode and the second electrode, where the light emission part includes amorphous or polycrystalline silicon consisting of a single layer or plural layers and where the dimension of the silicon in at least one direction is controlled to be several nanometers.
摘要翻译：以低价格提供自发射硅发射显示器，其包含以地球上丰富地存在的硅和氧作为主要成分，并且可以通过常规硅工艺容易地形成。发光元件包括用于注入电子的第一电极，用于注入空穴的第二电极和与第一电极和第二电极电连接的发光部分，其中发光部分包括由单层组成的非晶或多晶硅或多个层，并且其中至少一个方向上的硅的尺寸被控制为几纳米。

49. 发明授权

US07772053B2 Method for fabrication of semiconductor device 失效
标题翻译：半导体器件制造方法
公开(公告)号：US07772053B2
公开(公告)日：2010-08-10
申请号：US11956858
申请日：2007-12-14
申请人： Norifumi Kameshiro , Toshiyuki Mine , Tomoyuki Ishii , Toshiaki Sano
发明人： Norifumi Kameshiro , Toshiyuki Mine , Tomoyuki Ishii , Toshiaki Sano
IPC分类号： H01L21/00
CPC分类号： H01L29/66757 , H01L29/66613 , H01L29/66772
摘要： After forming a source-drain material film on an insulator layer, an opening portion reaching the insulator layer is formed in the source-drain material film. Then, a channel having desired thickness and a gate insulator are sequentially formed on the insulator layer and the source-drain material film in the opening portion. Thereafter, a gate material film embedding the opening portion is formed on the gate insulator. Subsequently, a cap film is formed on the gate material film, thereby forming the gate made of the gate material film. Then, a mask layer is formed on the source-drain material film. Next, the source-drain material film not protected by the mask layer is removed while protecting the gate by the cap film, thereby leaving the source-drain material film on both sides of the gate. The source-drain material film on one side becomes the source and that on the other side becomes the drain.
摘要翻译：在绝缘体层上形成源极 - 漏极材料膜之后，在源极 - 漏极材料膜中形成到达绝缘体层的开口部分。然后，在开口部分的绝缘体层和源极 - 漏极材料膜上依次形成具有期望厚度的沟道和栅极绝缘体。此后，在栅极绝缘体上形成嵌入开口部的栅极材料膜。随后，在栅极材料膜上形成盖膜，从而形成由栅极材料膜制成的栅极。然后，在源极 - 漏极材料膜上形成掩模层。接下来，除去未被掩模层保护的源极 - 漏极材料膜，同时通过盖膜保护栅极，从而在栅极的两侧留下源极 - 漏极材料膜。一侧的源极 - 漏极材料膜成为源极，而另一侧的源极 - 漏极材料膜变成漏极。

50. 发明申请

US20100182828A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20100182828A1
公开(公告)日：2010-07-22
申请号：US12688886
申请日：2010-01-17
申请人： Akio SHIMA , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
发明人： Akio SHIMA , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
IPC分类号： G11C11/00 , H01L47/00 , G11C8/00
CPC分类号： H01L27/2481 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
摘要翻译：提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以构成三维存储器单元格阵列。存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

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