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41. 发明授权

US06922105B2 Operational amplifier 失效
标题翻译：运算放大器
公开(公告)号：US06922105B2
公开(公告)日：2005-07-26
申请号：US10632849
申请日：2003-08-04
申请人： Hiroshi Imai , Mitsuru Aoki , Hiroyuki Ban
发明人： Hiroshi Imai , Mitsuru Aoki , Hiroyuki Ban
IPC分类号： H03F1/52 , H03F3/30 , H03F3/45 , H03F3/26
CPC分类号： H03F3/3071 , H03F3/45183 , H03F2203/30036 , H03F2203/30051 , H03F2203/45324 , H03F2203/45352 , H03F2203/45632 , H03F2203/45708
摘要： In an operational amplifier, a differential amplifying circuit is configured to amplify an input voltage inputted from the input terminal. An outputting transistor is connected to the output terminal. A driving transistor is connected to the differential amplifying circuit and the outputting transistor. The driving transistor turns on according to a control signal supplied from the differential amplifying circuit to the driving circuit. The driving transistor is also configured to drive the outputting transistor according to the control signal. A control signal reducing circuit, when a voltage is applied on the driving transistor through the outputting transistor, is configured to reduce the control signal within a range that the driving transistor is kept to on state. The voltage applied on the driving transistor exceeds a predetermined threshold voltage.
摘要翻译：在运算放大器中，差分放大电路被配置为放大从输入端输入的输入电压。输出晶体管连接到输出端子。驱动晶体管连接到差分放大电路和输出晶体管。驱动晶体管根据从差分放大电路向驱动电路提供的控制信号导通。驱动晶体管也被配置为根据控制信号来驱动输出晶体管。当通过输出晶体管对驱动晶体管施加电压时，控制信号降低电路被配置为在驱动晶体管保持导通状态的范围内减少控制信号。施加在驱动晶体管上的电压超过预定阈值电压。

42. 发明授权

US06646319B2 Semiconductor device having isolating region for suppressing electrical noise 失效
公开(公告)号：US06646319B2
公开(公告)日：2003-11-11
申请号：US10175306
申请日：2002-06-20
申请人： Hirokazu Itakura , Hiroyuki Ban
发明人： Hirokazu Itakura , Hiroyuki Ban
IPC分类号： H01L2900
CPC分类号： H01L21/765 , H01L21/76264 , H01L21/76286 , H01L21/76291
摘要： A semiconductor device includes an output power device, which generates an electrical noise, and an on-chip circuit, to which the noise is transmitted. The output power device is surrounded by two isolating regions. The area between the two isolating regions is electrically connected to a field ground area by a first wiring line. The field ground area is electrically connected to a point of contact, which has ground potential. The area between the outer isolating region of the two isolating regions and another isolating region around the on-chip circuit is also electrically connected to the field ground area by a second wiring line. The first and second wiring lines are separated from each other. The electrical noise is transmitted to the field ground area and released to the point of contact. Therefore, the noise is attenuated and the transmission of the noise to the on-chip circuit is suppressed.

43. 发明授权

US6104094A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US6104094A
公开(公告)日：2000-08-15
申请号：US42728
申请日：1998-03-17
申请人： Hiroyuki Ban , Fukuo Ishikawa
发明人： Hiroyuki Ban , Fukuo Ishikawa
IPC分类号： H01L21/762 , H01L21/60 , H01L21/822 , H01L23/485 , H01L27/04 , H01L27/12 , H01L23/48
CPC分类号： H01L24/05 , H01L24/48 , H01L27/1203 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05073 , H01L2224/05124 , H01L2224/05624 , H01L2224/48463 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/12032 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105
摘要： A pad for input/output signals is formed on a first conductive type insulated island region interposing an insulating film therebetween. The insulated island region is electrically insulated and isolated from other semiconductor regions in a semiconductor substrate. A fixed potential is provided to the insulated island region through an n.sup.+ -type layer and an electrode. As a result, it is possible to prevent noise superimposed on the input/output signals from interfering in the operation of the other semiconductor regions, and to prevent noise produced in the other semiconductor regions from being superimposed on the input/output signals.
摘要翻译：用于输入/输出信号的焊盘形成在其间插入有绝缘膜的第一导电型绝缘岛区域上。绝缘岛区域与半导体衬底中的其它半导体区域电绝缘和隔离。通过n +型层和电极将绝缘岛区域提供固定电位。结果，可以防止叠加在输入/输出信号上的噪声干扰其他半导体区域的操作，并且防止在其它半导体区域中产生的噪声叠加在输入/输出信号上。

44. 发明授权

US5994744A Analog switching circuit 失效
标题翻译：模拟开关电路
公开(公告)号：US5994744A
公开(公告)日：1999-11-30
申请号：US898752
申请日：1997-07-23
申请人： Tetsuya Katayama , Takeshi Miki , Junji Hayakawa , Hiroyuki Ban
发明人： Tetsuya Katayama , Takeshi Miki , Junji Hayakawa , Hiroyuki Ban
IPC分类号： H01L27/02 , H03K17/082 , H01L29/72
CPC分类号： H03K17/0822 , H01L27/0251 , H01L27/0266 , H03K2217/0018
摘要： An analog switching circuit comprises an insulated-gate field-effect transistor (Q20) having two n-type input-side and outpu-side semiconductor regions (201, 202) and a p-type semiconductor substrate region 203, for controlling conductiveness between an input terminal (IN) and an output terminal (OUT) based on a gate potential. A surge pulse detecting circuit (1020), responsive to an electric potential (Vi) of the input terminal (IN), produces a detection signal of a surge pulse equivalent to a forward bias of a PN junction formed between the semiconductor substrate region (203) and the input-side semiconductor region (201). A substrate potential setting circuit (1010) varies an electric potential of the semiconductor substrate region (203) in response to the electric potential (Vi) of the input terminal (IN) when aby detection signal is produced. Furthermore, a gate potential control circuit (1030) varies the gate potential of the insulated-gate field-effect transistor (Q20) in the same direction as the electric potential of the semiconductor substrate region (203) when the detection signal is produced.
摘要翻译：模拟开关电路包括具有两个n型输入侧和外侧半导体区域（201,202）和p型半导体衬底区域203的绝缘栅场效应晶体管（Q20），用于控制导电性输入端子（IN）和输出端子（OUT）。响应于输入端子（IN）的电位（Vi）的浪涌脉冲检测电路（1020）产生与在半导体衬底区域（203）之间形成的PN结的正向偏压相当的浪涌脉冲的检测信号）和输入侧半导体区域（201）。基板电位设定电路（1010）响应于当产生aby检测信号时的输入端子（IN）的电位（Vi），改变半导体衬底区域（203）的电位。此外，当产生检测信号时，栅极电位控制电路（1030）在与半导体衬底区域（203）的电位相同的方向上改变绝缘栅极场效应晶体管（Q20）的栅极电位。

45. 发明授权

US5889722A Hybrid integrated circuit device and method of fabricating the same 失效
标题翻译：混合集成电路装置及其制造方法
公开(公告)号：US5889722A
公开(公告)日：1999-03-30
申请号：US917131
申请日：1997-08-25
申请人： Koji Numazaki , Takahisa Koyasu , Hiroyuki Ban
发明人： Koji Numazaki , Takahisa Koyasu , Hiroyuki Ban
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/10 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C5/14 , G11C16/102
摘要： An IC which integrates an EPROM is disposed on a circuit board. Also, a pad for supplying a writing voltage to the EPROM and a voltage supplying circuit, for supplying a power voltage to power terminals of the IC, which includes a first transistor and a second transistor, are disposed on the circuit board. When the pad is supplied with a high voltage for writing the data in the EPROM, the first transistor is on, the second transistor is off, and the voltage is supplied to the EPROM as the writing voltage. When data are read from the EPROM after the circuit board is packaged, because the pad is not supplied with any voltage, the first transistor is off, the second transistor is on, and a reading voltage is supplied to the EPROM via the outer terminal.
摘要翻译：将EPROM集成的IC设置在电路板上。此外，在电路板上设置用于向EPROM提供写入电压的焊盘和用于向包括第一晶体管和第二晶体管的IC的电源端子提供电源电压的电压供给电路。当提供用于将数据写入EPROM的高电压时，第一晶体管导通，第二晶体管截止，并将电压作为写入电压提供给EPROM。在电路板封装后从EPROM读取数据时，由于焊盘未被提供任何电压，所以第一晶体管截止，第二晶体管导通，并且读取电压通过外部端子提供给EPROM。

46. 发明授权

US08102047B2 Load driving device 有权
标题翻译：负载驱动装置
公开(公告)号：US08102047B2
公开(公告)日：2012-01-24
申请号：US12801187
申请日：2010-05-27
申请人： Satoshi Shiraki , Akira Yamada , Hiroyuki Ban
发明人： Satoshi Shiraki , Akira Yamada , Hiroyuki Ban
IPC分类号： H01L23/34 , H01L23/10
CPC分类号： H05K7/1432 , H01L24/73 , H01L2224/32145 , H01L2224/32245 , H01L2224/33181 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/73215 , H01L2224/73265 , H01L2924/01046 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H02M7/003 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A load driving device includes: an output power device for driving a load; a driving IC for controlling the output power device, wherein the driving IC is electrically coupled with the output power device through a wire or a connection member; and a first electrode substrate. The output power device and the driving IC are mounted on the first electrode substrate. In this case, the output power device is controlled with high speed, and a mounting area of the output power device and the driving IC is reduced.
摘要翻译：负载驱动装置包括：用于驱动负载的输出功率装置; 用于控制输出功率器件的驱动IC，其中驱动IC通过导线或连接构件与输出功率器件电耦合; 和第一电极基板。输出功率器件和驱动IC安装在第一电极基板上。在这种情况下，输出功率器件被高速控制，并且输出功率器件和驱动IC的安装面积减小。

47. 发明申请

US20100178213A1 REACTOR AND REACTING METHOD 有权
标题翻译：反应器和反应方法
公开(公告)号：US20100178213A1
公开(公告)日：2010-07-15
申请号：US12482903
申请日：2009-06-11
申请人： Hiroyuki Ban , Koji Noishiki , Kazuto Okada , Seiichi Yamamoto
发明人： Hiroyuki Ban , Koji Noishiki , Kazuto Okada , Seiichi Yamamoto
IPC分类号： B01J14/00
CPC分类号： B01J4/001 , B01F5/0471 , B01F13/0059 , B01J19/249 , B01J2219/2453 , B01J2219/2458 , B01J2219/247 , B01J2219/2485 , B01J2219/2486 , B01J2219/2487 , B01J2219/2488 , B01J2219/249
摘要： It is aimed to improve reaction efficiency by increasing a contact area of first and second reactants per unit volume without reducing dimensions of an inlet path for the first reactant and an inlet path for the second reactant in a layer-thickness direction.In a reactor, a channel includes a first inlet path having the first reactant introduced thereinto, a second inlet path arranged while being separated from the first inlet path and having the second reactant introduced thereinto, a junction channel for causing the first reactant flowing via the first inlet path and the second reactant flowing via the second inlet path to join in the form of the laminar flows separated from each other, and a reaction channel connected with a downstream side of the junction channel for permitting the laminar flow of the first reactant and that of the second reactant held in contact with each other and reacting the two reactants at a contact interface thereof. A dimension of the reaction channel in the layer-thickness direction perpendicular to the contact interface is set to be smaller than the sum of a dimension of the first inlet path in the layer-thickness direction and a dimension of the second inlet path in the layer-thickness direction.
摘要翻译：旨在通过增加每单位体积的第一和第二反应物的接触面积而不减少第一反应物的入口路径的尺寸和层厚度方向上的第二反应物的入口路径来提高反应效率。在反应器中，通道包括具有引入其中的第一反应物的第一入口路径，第二入口通道，其与第一入口路径分离并且具有引入第二入口路径的第二入口通道，用于使第一反应物经由第一入口路径和第二反应物经由第二入口路径流动以彼此分离的层流的形式连接;以及反应通道，其与接合通道的下游侧连接，以允许第一反应物的层流，以及第二反应物彼此接触并在其接触界面处使两种反应物反应。垂直于接触界面的层厚度方向上的反应通道的尺寸被设定为小于层厚度方向上的第一入口路径的尺寸和层中的第二入口路径的尺寸之和厚度方向。

48. 发明授权

US07755187B2 Load driving device 有权
公开(公告)号：US07755187B2
公开(公告)日：2010-07-13
申请号：US11806467
申请日：2007-05-31
申请人： Satoshi Shiraki , Akira Yamada , Hiroyuki Ban
发明人： Satoshi Shiraki , Akira Yamada , Hiroyuki Ban
IPC分类号： H01L23/34 , H01L23/495
CPC分类号： H05K7/1432 , H01L24/73 , H01L2224/32145 , H01L2224/32245 , H01L2224/33181 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/73215 , H01L2224/73265 , H01L2924/01046 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H02M7/003 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A load driving device includes: an output power device for driving a load; a driving IC for controlling the output power device, wherein the driving IC is electrically coupled with the output power device through a wire or a connection member; and a first electrode substrate. The output power device and the driving IC are mounted on the first electrode substrate. In this case, the output power device is controlled with high speed, and a mounting area of the output power device and the driving IC is reduced.

49. 发明授权

US07554314B2 Current mirror circuit for reducing chip size 有权
标题翻译：电流镜电路，减少芯片尺寸
公开(公告)号：US07554314B2
公开(公告)日：2009-06-30
申请号：US11589878
申请日：2006-10-31
申请人： Satoshi Sobue , Hiroyuki Ban , Shigenori Mori
发明人： Satoshi Sobue , Hiroyuki Ban , Shigenori Mori
IPC分类号： G05F3/16
CPC分类号： G05F3/265 , G05F3/267
摘要： A current mirror circuit includes transistors having bases coupled together and emitters connected to a voltage line. The current mirror circuit further includes a zener diode having an anode connected to the bases and a cathode connected to the voltage line. When a base potential of the transistors decreases, a reverse current of the zener diode increases. Therefore, the zener diode has a resistance and acts as a resistor to clamp the base potential of the transistors. A layout area of the zener diode is much smaller than that of the resistor having a resistance equal to that of the zener diode. The current mirror circuit achieves reduced chip size by using the zener diode instead of the resistor.
摘要翻译：电流镜电路包括具有耦合在一起的基极和连接到电压线的发射极的晶体管。电流镜电路还包括具有连接到基极的阳极和连接到电压线的阴极的齐纳二极管。当晶体管的基极电位降低时，齐纳二极管的反向电流增加。因此，齐纳二极管具有电阻并且用作钳位晶体管的基极电位的电阻器。齐纳二极管的布局面积远小于具有等于齐纳二极管电阻的电阻器的布局面积。电流镜电路通过使用齐纳二极管而不是电阻实现了减小的芯片尺寸。

50. 发明授权

US07542255B2 Input protection circuit 有权
标题翻译：输入保护电路
公开(公告)号：US07542255B2
公开(公告)日：2009-06-02
申请号：US11715421
申请日：2007-03-08
申请人： Shinichiro Nakata , Hiroyuki Ban , Satoshi Ichikawa
发明人： Shinichiro Nakata , Hiroyuki Ban , Satoshi Ichikawa
IPC分类号： H02H3/22
CPC分类号： H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： An input protection circuit comprises a reverse flow preventing diode, a series circuit of a diode and a Zener diode, and a current path forming resistor or diode. The reverse flow preventing diode is connected between an input terminal and an internal circuit. The series circuit is connected between the input terminal and a ground. The current path forming resistor or diode is connected between a first common connection point of the reverse flow preventing diode and the internal circuit and a second common connection point of the series circuit, and sets a potential at the first common connection point to be less than a potential at the input terminal when the surge voltage is applied to the input terminal.
摘要翻译：输入保护电路包括反向阻流二极管，二极管和齐纳二极管的串联电路以及电流路径形成电阻器或二极管。反向防流二极管连接在输入端和内部电路之间。串联电路连接在输入端和地之间。电流通路形成电阻器或二极管连接在反向防流二极管的第一公共连接点和内部电路之间，并且串联电路的第二公共连接点连接，并将第一公共连接点处的电位设置为小于当浪涌电压施加到输入端时在输入端子处的电位。

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