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41. 发明授权

US6154047A Bus configuration and input/output buffer 有权
公开(公告)号：US6154047A
公开(公告)日：2000-11-28
申请号：US339853
申请日：1999-06-25
申请人： Masao Taguchi
发明人： Masao Taguchi
IPC分类号： G11C11/409 , G06F3/00 , G06F12/00 , G06F13/16 , G06F13/40 , G11C7/10 , G11C11/401 , G11C11/407 , H03K19/00 , H03K19/0175 , H03K19/0185 , H03K19/0948
CPC分类号： G11C7/1057 , G06F13/4077 , G06F13/4086 , G11C7/1051 , H03K19/0016 , H03K19/017545 , H03K19/018585 , G11C2207/2227 , Y02B60/1228 , Y02B60/1235
摘要： A system for signal transmission has at least one bus for the signal transmission and a reflection-prevention resistance provided on a stub connected to the bus for preventing reflection of signals at an intersection between the bus and the stub. The system includes termination resistances, and a switch unit for coupling the bus to termination voltage via the termination resistances in a first mode and for disconnecting the bus from the termination voltage in a second mode.

42. 发明授权

US06045976A Optical exposure method 失效
公开(公告)号：US06045976A
公开(公告)日：2000-04-04
申请号：US734790
申请日：1996-10-25
申请人： Tamae Haruki , Kenji Nakagawa , Masao Taguchi , Hiroyuki Tanaka , Satoru Asai , Isamu Hanyu
发明人： Tamae Haruki , Kenji Nakagawa , Masao Taguchi , Hiroyuki Tanaka , Satoru Asai , Isamu Hanyu
IPC分类号： G03F7/20 , G03F7/207 , G03C5/00 , G03F9/00
CPC分类号： G03F7/70566 , G03F7/201 , G03F7/70091 , G03F7/701 , G03F7/70125 , G03F7/70241 , G03F7/70283 , G03F7/70583
摘要： An optical exposure method in photolithography applied for precise processing when semiconductor devices are produced. A pattern on a photomask is projected and exposed on a register on a base plate with an exposure device including a deformation illumination system, a photomask and a projection lens. The deformation illumination system is composed of a light source, a diaphragm and a condenser lens, and the diaphragm is provided with a linear through-hole. The optical exposure method uses a ray of linear light for illumination or two rays of linear light for illumination that are parallel with the pattern. The two rays of linear light are symmetrical with respect to an optical axis. These rays are parallel with the pattern in a position separate from the optical axis of the exposure device when the photomask pattern is a line and space pattern.

43. 发明授权

US5949252A Bus configuration and input/output buffer 失效
公开(公告)号：US5949252A
公开(公告)日：1999-09-07
申请号：US754760
申请日：1996-11-21
申请人： Masao Taguchi
发明人： Masao Taguchi
IPC分类号： G11C11/409 , G06F3/00 , G06F12/00 , G06F13/16 , G06F13/40 , G11C7/10 , G11C11/401 , G11C11/407 , H03K19/00 , H03K19/0175 , H03K19/0185 , H03K19/0948
CPC分类号： G11C7/1057 , G06F13/4077 , G06F13/4086 , G11C7/1051 , H03K19/0016 , H03K19/017545 , H03K19/018585 , G11C2207/2227 , Y02B60/1228 , Y02B60/1235
摘要： A system for signal transmission has at least one bus for the signal transmission and a reflection-prevention resistance provided on a stub connected to the bus for preventing reflection of signals at an intersection between the bus and the stub. The system includes termination resistances, and a switch unit for coupling the bus to termination voltage via the termination resistances in a first mode and for disconnecting the bus from the termination voltage in a second mode.

44. 发明授权

US5896320A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5896320A
公开(公告)日：1999-04-20
申请号：US439906
申请日：1995-05-12
申请人： Masao Taguchi
发明人： Masao Taguchi
IPC分类号： G11C11/409 , G11C5/14 , G11C11/407 , G11C11/4074 , G11C11/4091 , G11C11/4094 , G11C11/40
CPC分类号： G11C5/14 , G11C11/4074 , G11C11/4091 , G11C11/4094 , G11C5/147
摘要： A semiconductor memory device comprises a bit line, a memory cell connected to the bit line, a sense amplifier, a power source for providing a first voltage to the sense amplifier as an operational power source voltage, a MOS transistor connected between the sense amplifier and the bit line and a stabilized power source for providing to a gate electrode of the MOS transistor a second voltage lower than the first voltage, so that a restore voltage of the memory cell is determined by the source voltage of the MOS transistor.
摘要翻译：半导体存储器件包括位线，连接到位线的存储单元，读出放大器，用于向读出放大器提供第一电压作为工作电源电压的电源，连接在读出放大器与位线和稳定的电源，用于向MOS晶体管的栅电极提供低于第一电压的第二电压，从而由MOS晶体管的源极电压确定存储单元的恢复电压。

45. 发明授权

US5838188A Reference voltage generation circuit 失效
标题翻译：参考电压发生电路
公开(公告)号：US5838188A
公开(公告)日：1998-11-17
申请号：US794773
申请日：1997-02-03
申请人： Masao Taguchi
发明人： Masao Taguchi
IPC分类号： G05F3/24 , G05F3/26 , G11C5/14 , G11C11/407 , H03F1/02 , H03G3/20 , H03K19/00 , G05F1/10
CPC分类号： G05F3/262 , G11C5/147
摘要： A reference voltage generation circuit includes: a load unit having one end thereof connected to a higher voltage power supply line; an enhancement type n-channel MIS transistor having a drain thereof connected to the other end of the load unit, and a source thereof connected to a lower voltage power supply line; and a source follower circuit using a MIS transistor as a driving element, the source follower circuit having an input end thereof connected to the drain of the n-channel MIS transistor and having an output end thereof connected to a gate of the n-channel MIS transistor. A reference voltage is obtained at the drain of the n-channel MIS transistor. By the constitution, it is possible to obtain a stable reference voltage, and to incorporate the reference voltage generation circuit into an integrated circuit produced by integrating MIS transistors, without introducing an increase in production processes. It is also possible to reduce a consumed current of the reference voltage generation circuit.
摘要翻译：参考电压产生电路包括：负载单元，其一端连接到较高电压电源线; 增强型n沟道MIS晶体管，其漏极连接到负载单元的另一端，其源极连接到较低电压电源线; 以及使用MIS晶体管作为驱动元件的源极跟随器电路，源极跟随器电路的输入端连接到n沟道MIS晶体管的漏极，并且其输出端连接到n沟道MIS的栅极晶体管。在n沟道MIS晶体管的漏极处获得参考电压。通过该结构，可以获得稳定的参考电压，并且将参考电压产生电路并入到通过集成MIS晶体管而生成的集成电路中，而不引入生产过程的增加。也可以减小参考电压产生电路的消耗电流。

46. 发明授权

US5757226A Reference voltage generating circuit having step-down circuit outputting a voltage equal to a reference voltage 失效
标题翻译：具有降压电路的参考电压产生电路，其输出等于参考电压的电压
公开(公告)号：US5757226A
公开(公告)日：1998-05-26
申请号：US722934
申请日：1996-09-30
申请人： Toyonobu Yamada , Tetsuya Endo , Takaaki Suzuki , Hirohiko Mochizuki , Masao Taguchi
发明人： Toyonobu Yamada , Tetsuya Endo , Takaaki Suzuki , Hirohiko Mochizuki , Masao Taguchi
IPC分类号： G05F1/46 , H01L20060101 , H01L27/105 , G05F1/10
CPC分类号： G05F1/465
摘要： A semiconductor integrated circuit device includes a reference voltage generating circuit outputting a reference voltage from a step-up voltage, a step-up circuit stepping up the reference voltage within a range lower than an external power supply voltage and thus outputting the above step-up voltage, a step-down circuit stepping down the external power supply voltage and thus outputting a step-down voltage equal to the reference voltage, and an internal circuit receiving, as a power supply voltage thereof, the step-down voltage.
摘要翻译：一种半导体集成电路器件，包括从升压电压输出参考电压的基准电压产生电路，在比外部电源电压低的范围内升压参考电压的升压电路，从而输出上述升压电压，降压电路降低外部电源电压，从而输出等于参考电压的降压电压，内部电路作为其电源电压接收降压电压。

47. 发明授权

US5624791A Pattern forming method using mask 失效
标题翻译：使用掩模的图案形成方法
公开(公告)号：US5624791A
公开(公告)日：1997-04-29
申请号：US463930
申请日：1995-06-05
申请人： Toshiaki Kawabata , Kenji Nakagawa , Seiichiro Yamaguchi , Masao Taguchi , Kazuhiko Sumi , Yuichiro Yanagishita
发明人： Toshiaki Kawabata , Kenji Nakagawa , Seiichiro Yamaguchi , Masao Taguchi , Kazuhiko Sumi , Yuichiro Yanagishita
IPC分类号： G03F1/00 , G03F1/34 , G03F1/68 , G03F1/80 , H01L21/027 , H01L21/30 , G03C5/00
CPC分类号： G03F1/29 , G03F1/30 , G03F1/34 , G03F1/28
摘要： A mask includes a transparent layer which is transparent with respect to a light which is used for an exposure, and a mask pattern layer which is formed on the transparent layer. At least a portion of the mask patterns layer is made up solely of a phase shift layer for transmitting the light, so that a phase shift occurs between a phase of the light transmitted through the phase shift layer and a phase of the light transmitted through a portion of the mask having no phase shift layer.
摘要翻译：掩模包括相对于用于曝光的光是透明的透明层，以及形成在透明层上的掩模图案层。掩模图案层的至少一部分仅由用于透射光的相移层构成，从而在通过相移层传输的光的相位与通过相移层传输的光的相位之间发生相移没有相移层的掩模部分。

48. 发明授权

US5339273A Semiconductor memory device having a testing function and method of testing the same 失效
标题翻译：具有测试功能的半导体存储器件及其测试方法
公开(公告)号：US5339273A
公开(公告)日：1994-08-16
申请号：US806406
申请日：1991-12-13
申请人： Masao Taguchi
发明人： Masao Taguchi
IPC分类号： G11C29/00 , G11C5/06 , G11C7/18 , G11C11/401 , G11C11/409 , G11C29/02 , G11C29/12 , G11C29/50 , G11C7/00
CPC分类号： G11C29/026 , G11C29/02 , G11C29/50 , G11C29/50012 , G11C5/063 , G11C7/18 , G11C11/401
摘要： A semiconductor memory device is provided with a plurality of bit lines, a plurality of word lines, a memory cell array including a plurality of memory cells each coupled to one bit line and one word line, and a varying part for varying a capacitance of at least a selected one of the bit lines in response to a predetermined signal which indicates a test mode in which an operation of the semiconductor memory device is tested.
摘要翻译：半导体存储器件具有多个位线，多个字线，包括多个存储单元的存储单元阵列，每个存储单元分别耦合到一个位线和一个字线，以及变化部分，用于改变在响应于指示测试半导体存储器件的操作的测试模式的预定信号，至少选择一个位线。

49. 发明授权

US5021357A Method of making a dram cell with stacked capacitor 失效
标题翻译：制造具有堆叠电容器的电容器的方法
公开(公告)号：US5021357A
公开(公告)日：1991-06-04
申请号：US561424
申请日：1990-08-01
申请人： Masao Taguchi , Taiji Ema
发明人： Masao Taguchi , Taiji Ema
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L29/92
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/40 , H01L28/87
摘要： A dynamic random access memory device includes a storage capacitor having a plurality of stacked conductive films which form a storage electrode. A gap is formed between elevationally adjacent conductive films so as to surround the storage electrode. A gap is also formed between an insulating film which covers a gate electrode for insulation and a lowermost film of the storage electrode. Connection between the adjacent films may be established so that an uppermost film elevationally extends so as to make contact with a drain region. Also, connection can be established so that an upper film is mounted directly on an lower film. An end portion of the film may be thicker than the other portion thereof. The stacked film structure may be produced by alternatively forming a film made of a material different from the insulating film covering the gate electrode, and a conductive film.

50. 发明授权

US4803535A Dynamic random access memory trench capacitor 失效
标题翻译：动态随机存取存储器沟槽电容器
公开(公告)号：US4803535A
公开(公告)日：1989-02-07
申请号：US020983
申请日：1987-03-02
申请人： Masao Taguchi
发明人： Masao Taguchi
IPC分类号： G11C11/34 , H01L21/8242 , H01L27/108 , H01L29/92 , H01L29/78 , H01L27/02 , H01L49/02
CPC分类号： H01L28/40 , H01L27/10829 , H01L27/10861
摘要： A dynamic random access memory having a trench capacitor includes: a semiconductor substrate; a trench formed in a semiconductor substrate; an insulating layer formed on an inner surface of the trench and having a bottom opening; a first conductive layer formed at the bottom opening position and on the insulating layer and the first conductive layer is ohmically connected to the semiconductor substrate at the bottom opening. The device includes further a dielectric layer formed on the first conductive layer; a second conductive layer formed on the dielectric layer so as to fill the trench, the first conductive layer, the dielectric layer, and the second conductive layer constituting a charge storage capacitor; and a MIS transistor formed in the semiconductor substrate, wherein the second conductive layer is ohmically connected to a source or drain region of the MIS transistor.
摘要翻译：具有沟槽电容器的动态随机存取存储器包括：半导体衬底; 形成在半导体衬底中的沟槽; 绝缘层，形成在所述沟槽的内表面上并具有底部开口; 在底部开口位置和绝缘层上形成的第一导电层和第一导电层在底部开口处欧姆连接到半导体衬底。该器件还包括形成在第一导电层上的电介质层; 形成在电介质层上以便填充沟槽的第二导电层，构成电荷存储电容器的第一导电层，电介质层和第二导电层; 以及形成在所述半导体衬底中的MIS晶体管，其中所述第二导电层欧姆连接到所述MIS晶体管的源极或漏极区域。

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