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1. 发明授权

US5757226A Reference voltage generating circuit having step-down circuit outputting a voltage equal to a reference voltage 失效
标题翻译：具有降压电路的参考电压产生电路，其输出等于参考电压的电压
公开(公告)号：US5757226A
公开(公告)日：1998-05-26
申请号：US722934
申请日：1996-09-30
申请人： Toyonobu Yamada , Tetsuya Endo , Takaaki Suzuki , Hirohiko Mochizuki , Masao Taguchi
发明人： Toyonobu Yamada , Tetsuya Endo , Takaaki Suzuki , Hirohiko Mochizuki , Masao Taguchi
IPC分类号： G05F1/46 , H01L20060101 , H01L27/105 , G05F1/10
CPC分类号： G05F1/465
摘要： A semiconductor integrated circuit device includes a reference voltage generating circuit outputting a reference voltage from a step-up voltage, a step-up circuit stepping up the reference voltage within a range lower than an external power supply voltage and thus outputting the above step-up voltage, a step-down circuit stepping down the external power supply voltage and thus outputting a step-down voltage equal to the reference voltage, and an internal circuit receiving, as a power supply voltage thereof, the step-down voltage.
摘要翻译：一种半导体集成电路器件，包括从升压电压输出参考电压的基准电压产生电路，在比外部电源电压低的范围内升压参考电压的升压电路，从而输出上述升压电压，降压电路降低外部电源电压，从而输出等于参考电压的降压电压，内部电路作为其电源电压接收降压电压。

2. 发明授权

US5634367A Press forming device 失效
标题翻译：压制成型装置
公开(公告)号：US5634367A
公开(公告)日：1997-06-03
申请号：US395928
申请日：1995-02-28
申请人： Toyonobu Yamada , Tadasi Morisima , Nobutake Aikura
发明人： Toyonobu Yamada , Tadasi Morisima , Nobutake Aikura
IPC分类号： B21D22/02 , B21D15/02 , B21D37/02 , B21D51/12 , H02K15/14 , B21D51/16
CPC分类号： B30B7/04 , B21D15/02
摘要： A press forming device for forming a plurality of inwardly directed projections on a circumferential wall of a tubular article to be formed. The press forming device includes a lower die holder adapted to be mounted on a lower base of a press machine, and a die fixed on the lower die holder. The die has a plurality of inside forming parts on a circumferential surface of the die, each for forming one of the projections, respectively. The press forming device further includes a plurality of punches mounted on the lower die holder around an outer circumference of the die, each being arranged to be capable of being moved towards or away from the die, and each having an outside forming part in a position facing one of the inside forming parts for forming one of the projections, respectively. The press forming device also includes an upper die holder adapted to be mounted on an upper raising and lowering base of the press machine and a plurality of pressing members of wedge shape mounted on the upper die holder. Each of the pressing members is mounted at a position above one of the punches for moving one of the punches in a direction towards the die with lowering the raising and lowering base, to thereby press the tubular article between one of the inside forming parts of the die and one of the outside forming parts of the punches, respectively.
摘要翻译：一种压制成形装置，用于在要形成的管状物品的周壁上形成多个向内的突起。压制成形装置包括适于安装在压力机的下基座上的下模夹持器和固定在下模夹持器上的模具。模具在模具的圆周表面上具有多个内部形成部分，每个用于分别形成一个突出部。冲压成形装置还包括多个冲头，其围绕模具的外周安装在下模托架上，每个冲头能够朝向或远离模具移动，并且每个具有外部形成部件位于模具的外周面对其中一个内部形成部分，分别形成一个突起。冲压成形装置还包括适于安装在压力机的上升下降基座上的上模夹持器和安装在上模夹座上的多个楔形加压构件。每个按压构件安装在一个冲头上方的位置上，用于使一个冲头沿着朝向模具的方向移动，同时降低升高和降低底座，从而将管状物品压在其中一个内部形成部分之间模具和冲头的外部形成部件之一。

3. 发明授权

US5499213A Semiconductor memory device having self-refresh function 失效
标题翻译：具有自刷新功能的半导体存储器件
公开(公告)号：US5499213A
公开(公告)日：1996-03-12
申请号：US83443
申请日：1993-06-29
申请人： Makoto Niimi , Shigemasa Ito , Toyonobu Yamada , Yoshihiro Takemae , Yoshiharu Kato
发明人： Makoto Niimi , Shigemasa Ito , Toyonobu Yamada , Yoshihiro Takemae , Yoshiharu Kato
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A semiconductor memory device has an oscillator unit for generating refresh pulses, a refresh address detection unit for detecting refreshed addresses and outputting a predetermined signal upon the completion of the refreshing of all addresses, and an output control unit for continuing a self-refresh mode to refresh all addresses according to the signal from the refresh address detection unit, before releasing the self-refresh mode in response to an external signal. Therefore, the refresh operation is continued until all cells are refreshed, thereby data stored in the semiconductor memory device is not lost and is correctly refreshed.
摘要翻译：半导体存储器件具有用于产生刷新脉冲的振荡器单元，刷新地址检测单元，用于检测刷新的地址并在完成所有地址的刷新时输出预定信号;以及输出控制单元，用于继续自刷新模式在响应于外部信号释放自刷新模式之前，根据刷新地址检测单元的信号刷新所有地址。因此，继续刷新操作直到所有单元被刷新，从而存储在半导体存储器件中的数据不会丢失并被正确地刷新。

4. 发明授权

US6063640A Semiconductor wafer testing method with probe pin contact 失效
标题翻译：半导体晶圆测试方法与探针接触
公开(公告)号：US6063640A
公开(公告)日：2000-05-16
申请号：US30349
申请日：1998-02-25
申请人： Masataka Mizukoshi , Hidehiko Akasaki , Masao Nakano , Yasuhiro Fujii , Shinnosuke Kamata , Makoto Yanagisawa , Yasurou Matsuzaki , Toyonobu Yamada , Masami Matsuoka , Hiroyoshi Tomita
发明人： Masataka Mizukoshi , Hidehiko Akasaki , Masao Nakano , Yasuhiro Fujii , Shinnosuke Kamata , Makoto Yanagisawa , Yasurou Matsuzaki , Toyonobu Yamada , Masami Matsuoka , Hiroyoshi Tomita
IPC分类号： H01L23/58 , G01R31/26 , H01L21/66
CPC分类号： H01L22/32 , H01L22/22 , H01L2224/05554 , Y10S438/977
摘要： A semiconductor wafer testing method includes a pre-test step for forming a temporary test film on a surface of a semiconductor wafer, a test step for testing the semiconductor wafer by applying a probe to the temporary test film and a post-test step for exfoliating the temporary test film from the surface of the semiconductor wafer. The temporary test film includes test electrode groups each provided with a plurality of regularly arranged test electrodes, and wiring patterns for electrically connecting the test electrodes with corresponding ones of semiconductor unit electrodes in respective semiconductor units on the semiconductor wafer. Probe pins of said probe are arranged so as to be aligned with corresponding ones of the test electrodes of the respective test electrode groups.
摘要翻译：半导体晶片测试方法包括：在半导体晶片的表面上形成临时测试膜的预测试步骤，通过向临时测试膜施加探针来测试半导体晶片的测试步骤和用于去角质的后测试步骤来自半导体晶片表面的临时测试膜。临时测试膜包括各自设置有多个规则排列的测试电极的测试电极组和用于将测试电极与半导体晶片上的各个半导体单元中的相应半导体单元电极电连接的布线图案。所述探针的探头针布置成与各个测试电极组的相应测试电极对齐。

5. 发明授权

US5986377A Stator for dynamoelectric machine 失效
标题翻译：电动机定子
公开(公告)号：US5986377A
公开(公告)日：1999-11-16
申请号：US57794
申请日：1998-04-09
申请人： Toyonobu Yamada , Tsutomu Kawamura , Naoki Mizutani , Toshikazu Sato , Kingo Miyaoka , Motoyasu Mochizuki
发明人： Toyonobu Yamada , Tsutomu Kawamura , Naoki Mizutani , Toshikazu Sato , Kingo Miyaoka , Motoyasu Mochizuki
IPC分类号： H02K1/14 , H02K3/18 , H02K3/52 , H02K15/02 , H02K15/04 , H02K15/06 , H02K1/00
CPC分类号： H02K15/066 , H02K1/148 , H02K15/022 , H02K15/0457 , H02K15/06 , H02K3/18 , H02K3/522 , H02K2201/06 , H02K2203/12
摘要： A stator for a dynamoelectric machine includes an annular stator core composed of a developed core formed by stacking a number of steel sheets, each steel sheet including a plurality of unit cores each of which includes a unit yoke and a magnetic pole tooth and which are sequentially connected together by connecting portions integral with the respective unit yokes, and a stator coil wound on the magnetic pole teeth. Each unit yoke has a circumferential end overlapping, in a direction of stacking of the steel sheets, a circumferential end of the unit yoke adjacent to said each unit yoke.
摘要翻译：一种用于电动机的定子包括由堆叠多个钢板形成的展开芯构成的环形定子铁芯，每个钢板包括多个单元芯，每个单元芯包括单元磁轭和磁极齿，并且依次通过与各单元轭一体化的连接部分连接在一起，以及缠绕在磁极齿上的定子线圈。每个单元轭具有在钢板堆叠方向上与圆柱体相邻的单元轭的圆周端重叠的圆周端。

6. 发明授权

US5942831A Laminated core 失效
标题翻译：层压芯
公开(公告)号：US5942831A
公开(公告)日：1999-08-24
申请号：US754147
申请日：1996-11-22
申请人： Toyonobu Yamada , Shoji Fujimori
发明人： Toyonobu Yamada , Shoji Fujimori
IPC分类号： H02K1/18 , H02K15/02 , H02K15/00
CPC分类号： H02K15/024 , Y10T29/49009
摘要： A laminated core for dynamoelectric machines and so on is formed of thin sheet core pieces each blanked into a predetermined configuration and stacked one upon another and are successively welded at a plurality of weld zones of an edge of each core piece by continuous or spot irradiation of laser beams so that the core pieces are combined together. The core piece constituting one of two end faces of the core has first notches formed in one half of the weld zones of the core piece. The core piece constituting the other end face of the core has second notches formed in one half of the weld zones of the core piece constituting the other end face of the core. The first notches are shifted from the second notches by 90 degrees.
摘要翻译：用于电动机等的层叠铁芯由薄片芯片形成，每个芯片芯片被冲裁成预定的构造并且彼此层叠，并且通过连续或点状照射连续地焊接在每个芯片的边缘的多个焊接区域激光束，使得芯片组合在一起。构成芯的两个端面之一的芯片在芯片的焊接区域的一半中形成有第一切口。构成芯的另一端面的芯片在构成芯的另一端面的芯片的焊接区域的一半中形成有第二凹口。第一个凹口从第二个凹口偏移了90度。

7. 发明授权

US5610863A Memory device having a booster circuit and a booster circuit control method 失效
标题翻译：具有升压电路和升压电路控制方法的存储装置
公开(公告)号：US5610863A
公开(公告)日：1997-03-11
申请号：US655915
申请日：1996-05-31
申请人： Toyonobu Yamada
发明人： Toyonobu Yamada
IPC分类号： G11C11/407 , G11C8/08 , G11C7/00
CPC分类号： G11C8/08
摘要： This invention relates to a memory device internally employing an active period control signal for controlling an active period and an inactive period for internal operation. The memory device comprises a plurality of word lines and bit lines; memory cells provided at intersections thereof; a booster circuit, having an output terminal, for outputting to the output terminal a higher voltage than a power source voltage; and word drivers, connected to each of the word lines, for connecting the output terminal of the booster circuit to a corresponding word line in response to a word selection signals provided during the active period. The memory device also comprises a boosting control signal generation circuit supplying the booster circuit with a boosting control signal to continue a boosting operation of the booster circuit longer than the active period in response to the active period control signal. The output of the booster circuit can recover appropriate voltage level after the termination of the active period so that the error read operation can be avoided.
摘要翻译：本发明涉及一种存储器件，其内部采用有源周期控制信号来控制有效周期和用于内部操作的无效周期。存储器件包括多个字线和位线; 在其交点处提供的记忆单元; 升压电路，具有输出端子，用于向输出端子输出比电源电压更高的电压; 和字驱动器，其连接到每个字线，用于响应于在该活动期间期间提供的字选择信号将升压电路的输出端连接到对应的字线。该存储装置还包括升压控制信号产生电路，该升压控制信号产生电路向升压电路提供升压控制信号，以响应于有效周期控制信号而持续升压电路的升压操作比活动周期长。升压电路的输出可以在有效周期结束后恢复适当的电压电平，从而避免错误读取操作。

8. 发明授权

US5349290A Method for testing semiconductor integrated circuit device, voltage drop power supply circuit suitable for the method, and semiconductor integrated circuit device having the voltage drop circuit 失效
标题翻译：用于测试半导体集成电路器件的方法，适合该方法的电压降电源电路以及具有电压降电路的半导体集成电路器件
公开(公告)号：US5349290A
公开(公告)日：1994-09-20
申请号：US52620
申请日：1993-04-27
申请人： Toyonobu Yamada
发明人： Toyonobu Yamada
IPC分类号： G01R31/40 , G01R31/28
CPC分类号： G01R31/40
摘要： In a voltage drop power supply circuit for a semiconductor integrated circuit device, a first unit generates a constant internal power supply voltage from an external power supply voltage in accordance with a first characteristic line defining a relationship between the external power supply voltage and the internal power supply voltage, and applies the constant internal power supply voltage to internal circuits of the semiconductor integrated circuit device. A second unit generates a burn-in voltage from the external power supply voltage having a level higher than that used in the normal operation in accordance with a second characteristic line defining a relationship between the external power supply voltage and the internal power supply line, and applies the burn-in voltage to the internal circuits when a burn-in test is carried out for the semiconductor integrated circuit device. The second characteristic line crosses the first characteristic line at an intermediate point between lower and upper limit voltages defined by the first characteristic line. The burn-in voltage is greater than the internal power supply voltage used in the normal operation.
摘要翻译：在用于半导体集成电路器件的电压降电源电路中，第一单元根据限定外部电源电压和内部功率之间的关系的第一特性线从外部电源电压产生恒定的内部电源电压电源电压，并将恒定的内部电源电压施加到半导体集成电路器件的内部电路。第二单元根据限定外部电源电压和内部电源线之间的关系的第二特性线，从具有比正常操作中使用的电平高的外部电源电压产生老化电压，以及当对半导体集成电路器件进行老化测试时，对内部电路施加老化电压。第二特征线在由第一特性线限定的下限和上限电压之间的中间点处穿过第一特征线。老化电压大于正常工作时使用的内部电源电压。

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