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41. 发明授权

US07157647B2 Circuitized substrate with filled isolation border, method of making same, electrical assembly utilizing same, and information handling system utilizing same 失效
标题翻译：具有填充隔离边界的电路化基板，其制造方法，利用其组合的电气组件以及利用其的信息处理系统
公开(公告)号：US07157647B2
公开(公告)日：2007-01-02
申请号：US10882170
申请日：2004-07-02
申请人： John M. Lauffer , James M. Larnerd , Voya R. Markovich
发明人： John M. Lauffer , James M. Larnerd , Voya R. Markovich
IPC分类号： H05K1/11
CPC分类号： H05K3/44 , H05K1/056 , H05K3/0047 , H05K3/0052 , H05K3/429 , H05K3/4641 , H05K2203/0323 , H05K2203/1476 , Y10T29/49124 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155
摘要： A circuitized substrate which includes a plurality of contiguous open segments along a side edge portion of the at least one electrically conductive layer thereof, these open segments isolated by a barrier of dielectric material which substantially fills the open segments, e.g., during a lamination process which bonds two dielectric layers of the substrate to the conductive layer. A method of making the substrate, an electrical assembly utilizing the substrate, a multilayered circuitized assembly also utilizing the substrate and an information handling system, e.g., a mainframe computer, are also provided.
摘要翻译：电路化衬底，其包括沿其至少一个导电层的侧边缘部分的多个邻接的开放段，这些开放段通过电介质材料的屏障隔离，所述阻挡层基本上填充开放段，例如在层压过程期间将基板的两个电介质层粘合到导电层。还提供了制造衬底的方法，利用衬底的电组件，还利用衬底的多层电路化组件和诸如主机的信息处理系统。

42. 发明授权

US06750405B1 Two signal one power plane circuit board 有权
标题翻译：两个信号一个电源平面电路板
公开(公告)号：US06750405B1
公开(公告)日：2004-06-15
申请号：US09690485
申请日：2000-10-17
申请人： Kenneth Fallon , Miguel A. Jimarez , Ross W. Keesler , John M. Lauffer , Roy H. Magnuson , Voya R. Markovich , Irv Memis , Jim P. Paoletti , Marybeth Perrino , John A. Welsh , William E. Wilson
发明人： Kenneth Fallon , Miguel A. Jimarez , Ross W. Keesler , John M. Lauffer , Roy H. Magnuson , Voya R. Markovich , Irv Memis , Jim P. Paoletti , Marybeth Perrino , John A. Welsh , William E. Wilson
IPC分类号： H01R1204
CPC分类号： H05K3/445 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L2924/0002 , H05K1/056 , H05K1/113 , H05K3/0023 , H05K3/0052 , H05K3/0094 , H05K3/06 , H05K3/108 , H05K3/426 , H05K3/429 , H05K3/44 , H05K3/4623 , H05K3/4641 , H05K2201/0919 , H05K2201/09536 , H05K2201/09554 , H05K2201/096 , H05K2201/10734 , H05K2203/0323 , H05K2203/0574 , H05K2203/0733 , H05K2203/1394 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers. Thereafter, the surfaces of the photoimageable material, vias and through holes are metalized by copper plating. This is preferably done by protecting the remainder of the circuitry with photoresist and utilizing photolithographic techniques. The photoresist is thereafter removed, leaving a circuit board or card having metalization on both sides, vias extending from both sides to the copper layer in the center, plated through holes connecting the two outer circuitized copper layers.
摘要翻译：形成印刷电路板或电路卡的方法设置有用作夹在一对可光成像的电介质层之间的电力平面的金属层。光刻图形金属填充的通孔和光成像的电镀通孔位于光图案化材料中，信号电路位于每个介电材料的表面上，并连接到通孔和电镀通孔。边界可以在板或卡周围，包括从电介质层之一的边缘终止的金属层。铜箔上设有间隙孔。可光成像的可固化介电材料的第一和第二层设置在作为可光成像的材料的铜的相对侧上。图案在可光成象材料的第一层和第二层上显影，以通过通孔显露金属层。在铜中的间隙孔处，通孔被开发成在两个电介质层中图案化孔。此后，可光成像材料，通孔和通孔的表面通过镀铜进行金属化。这优选通过用光致抗蚀剂和利用光刻技术保护电路的其余部分来实现。然后去除光致抗蚀剂，留下在两侧具有金属化的电路板或卡，其中心的两侧延伸到铜层，通孔连接两个外部电路化的铜层。

43. 发明授权

US06407341B1 Conductive substructures of a multilayered laminate 有权
标题翻译：多层层压板的导电子结构
公开(公告)号：US06407341B1
公开(公告)日：2002-06-18
申请号：US09557802
申请日：2000-04-25
申请人： Donald O. Anstrom , Bruce J. Chamberlin , James W. Fuller, Jr. , John M. Lauffer , Voya R. Markovich , Douglas O. Powell , Joseph P. Resavy , James R. Stack
发明人： Donald O. Anstrom , Bruce J. Chamberlin , James W. Fuller, Jr. , John M. Lauffer , Voya R. Markovich , Douglas O. Powell , Joseph P. Resavy , James R. Stack
IPC分类号： H05K114
CPC分类号： H01L23/50 , H01L23/5383 , H01L23/5385 , H01L2224/16 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/3025 , H05K3/429 , H05K3/4602 , H05K3/4623 , H05K3/4641 , H05K2201/09309 , H05K2201/09536 , Y10T29/49124 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165 , H01L2224/0401
摘要： Conductive substructures of a multilayered laminate and associated methods of fabrication. The conductive substructures include a 0S1P substructure, a 0S3P substructure, and a 2S1P substructure, in accordance with the notation nSmP, wherein n and m are non-negative integers, wherein S stands for “signal plane,” and wherein P stands for “power plane.” A signal plane is characterized by its inclusion of a layer comprising conductive circuitry. A power plane is characterized by its inclusion of a continuously conductive layer. Thus, a 0S1P substructure includes 0 signal planes and 1 power plane (n=0, m=1). A 0S3P substructure includes 0 signal planes and 3 power plane (n=0, m=3) with a dielectric layer between each pair of power planes. A 2S1P substructure includes 2 signal planes and 1 power plane (n=2, m=1) with a dielectric layer between the power plane and each signal plane. A multilayered laminate includes a stacked substructure configuration having any combination of 0S1P, 0S3P, and 2S1P substructures with dielectric material insulatively separating the substructures from one another.
摘要翻译：多层层压板的导电子结构和相关的制造方法。根据符号nSmP，导电子结构包括0S1P子结构，0S3P子结构和2S1P子结构，其中n和m是非负整数，其中S代表“信号面”，其中P代表“功率飞机“。信号平面的特征在于其包括包括导电电路的层。功率平面的特征在于其包括连续导电层。因此，0S1P子结构包括0个信号平面和1个功率平面（n = 0，m = 1）。 0S3P子结构包括0个信号平面和3个电源平面（n = 0，m = 3），每对电源层之间具有介电层。 2S1P子结构包括2个信号面和1个功率平面（n = 2，m = 1），电源层与每个信号平面之间具有介电层。多层层压板包括具有0S1P，0S3P和2S1P子结构的任何组合的堆叠的子结构配置，其中介电材料将子结构彼此绝缘地分离。

44. 发明授权

US06388204B1 Composite laminate circuit structure and methods of interconnecting the same 失效
公开(公告)号：US06388204B1
公开(公告)日：2002-05-14
申请号：US09651010
申请日：2000-08-29
申请人： John M. Lauffer , Voya R. Markovich , Thomas R. Miller , Konstantinos I. Papathomas , William E. Wilson
发明人： John M. Lauffer , Voya R. Markovich , Thomas R. Miller , Konstantinos I. Papathomas , William E. Wilson
IPC分类号： H01R909
CPC分类号： H05K3/462 , H01R4/26 , H05K3/0023 , H05K3/4069 , H05K3/4623 , H05K3/4641 , H05K2201/0347 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , H05K2203/0307 , Y10S428/901 , Y10T156/1089 , Y10T428/24917
摘要： A laminate circuit structure assembly is provided that comprises at least two modularized circuitized plane subassemblies; a joining layer located between each of the subassemblies and wherein the subassemblies and joining layer are bonded together with a cured dielectric from a bondable, curable dielectric. The subassemblies and joining layer are electrically interconnected with bondable electrically conductive material. The joining layer comprises dielectric layers disposed about an internal electrically conductive layer. The electrically conductive layer has a via and the dielectric layers each have a via of smaller diameter than the vias in the electrically conductive layer and are aligned with the vias in the electrically conductive layer. The vias are filled with electrically bondable electrically conductive material for providing electrical contact between the subassemblies.

45. 发明授权

US06201194B1 Multi-voltage plane, multi-signal plane circuit card with photoimageable dielectric 有权
标题翻译：多电平面，多信号平面电路卡，带有可光成像电介质
公开(公告)号：US06201194B1
公开(公告)日：2001-03-13
申请号：US09203978
申请日：1998-12-02
申请人： John M. Lauffer , Roy H. Magnuson , Voya R. Markovich , John A. Welsh
发明人： John M. Lauffer , Roy H. Magnuson , Voya R. Markovich , John A. Welsh
IPC分类号： H01R909
CPC分类号： H05K3/429 , H01R12/523 , H05K3/0023 , H05K3/4602 , H05K3/4608 , H05K3/4641 , H05K2201/0355 , H05K2201/09309 , H05K2201/09536 , H05K2201/096 , H05K2203/0554 , Y10T29/49165
摘要： A technique for forming an organic chip carrier or circuit board, having two voltage planes and at least two signal planes is provided which includes bonding a first layer of photolithographic dielectric material to a first metal layer and exposing the first layer of dielectric material to a pattern of radiation to provide at least one opening through the first layer of the dielectric material. A second metal layer is bonded to the first layer of photoimageable material on the opposite side from the first metal layer. Holes are etched in the first and second metal layers which correspond to and are larger than each of the patterns on said openings in the first layer of dielectric material. The exposed pattern on the first layer of dielectric material is then developed, with the openings in the first and second metal layers being larger than the corresponding developed opening in the first dielectric material. Second and third layers of photoimageable dielectric material are applied on the first and second metal layers, respectively and are photopatterned and developed to provide openings in each of the second and third layers of dielectric material some of which correspond to each of the holes in the first layer of dielectric material and the holes in the first and second metal layers, some of which terminate at the underlying metal layer. The exposed surfaces of both the second and third dielectric material, are circuitized and the holes plated or filled with metal.
摘要翻译：提供了一种用于形成具有两个电压平面和至少两个信号面的有机芯片载体或电路板的技术，其包括将第一层光刻电介质材料结合到第一金属层并将第一介电材料层暴露于图案的辐射以提供通过电介质材料的第一层的至少一个开口。第二金属层在与第一金属层相对的一侧上结合到可光成像材料的第一层。在第一和第二金属层中蚀刻孔，其对应于并且大于第一介电材料层中的所述开口上的每个图案。然后显影第一层介电材料上的暴露图案，其中第一和第二金属层中的开口大于第一介电材料中对应的显影开口。将第二和第三层可光成像介电材料分别施加在第一和第二金属层上，并对其进行光刻图案化和显影以在第二和第三层介电材料中的每一个中提供开口，其中的第一和第三层对应于第一和第二金属层中的每个孔介电材料层和第一和第二金属层中的孔，其中一些终止于下面的金属层。第二和第三介电材料的暴露表面被电路化，并且孔被镀金或填充金属。

46. 发明授权

US08247703B2 Method of making circuitized substrate with resistor including material with metal component and electrical assembly and information handling system utilizing said circuitized substrate 失效
标题翻译：制造具有电阻器的电路化基板的方法，包括具有金属部件的材料和利用所述电路化基板的电气组件和信息处理系统
公开(公告)号：US08247703B2
公开(公告)日：2012-08-21
申请号：US12938759
申请日：2010-11-03
申请人： Rabindra N. Das , John M. Lauffer , Voya R. Markovich
发明人： Rabindra N. Das , John M. Lauffer , Voya R. Markovich
IPC分类号： H05K1/16
CPC分类号： H05K1/167 , H01G4/206 , H01L2224/16 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/0102 , H01L2924/01025 , H01L2924/01046 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/15311 , H01L2924/16195 , H01L2924/3011 , H05K1/095 , H05K1/162 , H05K3/0023 , H05K2201/0187 , H05K2201/0209 , H05K2201/0215 , H05K2201/0257 , H05K2203/1453 , Y10T29/49082 , Y10T29/49087 , Y10T29/49089 , Y10T29/49091 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165 , H01L2224/0401
摘要： A method of making a circuitized substrate including a resistor comprised of material which includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) utilizing such a circuitized substrate are also provided.
摘要翻译：一种制造电路化基板的方法，包括由包括聚合物树脂的材料和包括至少一种金属组分和至少一种陶瓷组分的混合物的纳米粉末的量组成的电阻器。陶瓷部件可以是铁电陶瓷和/或高表面积陶瓷和/或透明氧化物和/或掺杂亚锰酸盐。或者，材料将包括聚合物树脂和纳米粉末，其中纳米粉末包含至少一种金属涂覆的陶瓷和/或至少一种氧化物涂覆的金属组分。还提供了使用这种电路化基板的电气组件（基板和至少一个电气部件）以及信息处理系统（例如，个人计算机）。

47. 发明授权

US07803688B2 Capacitive substrate and method of making same 失效
标题翻译：电容衬底及其制作方法
公开(公告)号：US07803688B2
公开(公告)日：2010-09-28
申请号：US12380616
申请日：2009-03-02
申请人： Rabindra N. Das , Frank D. Egitto , John M. Lauffer , How T. Lin , Voya R. Markovich
发明人： Rabindra N. Das , Frank D. Egitto , John M. Lauffer , How T. Lin , Voya R. Markovich
IPC分类号： H01L21/20
CPC分类号： H05K1/162 , H01L27/12 , H01L28/40 , H05K1/0306 , H05K3/125 , H05K3/4667 , H05K2201/0187 , H05K2201/09509 , H05K2203/013
摘要： A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.
摘要翻译：电容性基板及其制造方法，其中使用第一和第二玻璃层。第一导体形成在第一玻璃层上，并且电容电介质材料位于导体上方。然后将第二导体定位在电容电介质上，并且第二玻璃层位于第二导体上。形成导电通孔以分别耦合到第一和第二导体，使得当电容基板工作时，导体和电容电介质材料形成电容器。

48. 发明申请

US20090241332A1 Circuitized substrate and method of making same 审中-公开
标题翻译：电路基板及其制作方法
公开(公告)号：US20090241332A1
公开(公告)日：2009-10-01
申请号：US12078206
申请日：2008-03-28
申请人： John M. Lauffer , Roy H. Magnuson , Voya R. Markovich , James P. Paoletti , Kostas I. Papathomas , Rajinder S. Rai
发明人： John M. Lauffer , Roy H. Magnuson , Voya R. Markovich , James P. Paoletti , Kostas I. Papathomas , Rajinder S. Rai
IPC分类号： H05K3/00
CPC分类号： H05K3/462 , H05K3/0032 , H05K3/4069 , H05K3/4623 , H05K2201/09318 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2203/061 , Y10T29/49124
摘要： A circuitized substrate and method of making same in which a first plurality of holes are formed within two bonded dielectric layers and then made conductive, e.g., plated. The substrate also includes third and fourth dielectric layers bonded to the first and second with a plurality of continuous electrically conductive thru holes extending through all four dielectric layers. Conductive paste is positioned within the thru holes for providing electrical connections between desired conductive layers of the substrate and outer layers as well. A circuitized substrate assembly and method of making same are also provided.
摘要翻译：电路化基板及其制造方法，其中第一多个孔形成在两个接合的介电层内，然后导电，例如电镀。衬底还包括通过延伸穿过所有四个电介质层的多个连续导电通孔与第一和第二电极结合的第三和第四电介质层。导电浆料位于通孔内，用于在基板和外层的期望的导电层之间提供电连接。还提供了电路化基板组件及其制造方法。

49. 发明申请

US20090206051A1 Capacitive substrate and method of making same 失效
标题翻译：电容衬底及其制作方法
公开(公告)号：US20090206051A1
公开(公告)日：2009-08-20
申请号：US12380616
申请日：2009-03-02
申请人： Rabindra N. Das , Frank D. Egitto , John M. Lauffer , How T. Lin , Voya R. Markovich
发明人： Rabindra N. Das , Frank D. Egitto , John M. Lauffer , How T. Lin , Voya R. Markovich
IPC分类号： H01G13/00 , B05D5/12 , C23C14/34 , C23C14/30 , B05D3/00
CPC分类号： H05K1/162 , H01L27/12 , H01L28/40 , H05K1/0306 , H05K3/125 , H05K3/4667 , H05K2201/0187 , H05K2201/09509 , H05K2203/013
摘要： A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.
摘要翻译：电容性基板及其制造方法，其中使用第一和第二玻璃层。第一导体形成在第一玻璃层上，并且电容电介质材料位于导体上方。然后将第二导体定位在电容电介质上，并且第二玻璃层位于第二导体上。形成导电通孔以分别耦合到第一和第二导体，使得当电容基板工作时，导体和电容电介质材料形成电容器。

50. 发明授权

US07442879B2 Circuitized substrate with solder-coated microparticle paste connections, multilayered substrate assembly, electrical assembly and information handling system utilizing same and method of making said substrate 有权
标题翻译：具有焊料涂覆的微粒糊料连接的电路化衬底，多层衬底组件，利用其的电气组件和信息处理系统以及制造所述衬底的方法
公开(公告)号：US07442879B2
公开(公告)日：2008-10-28
申请号：US11244180
申请日：2005-10-06
申请人： Rabindra N. Das , John M. Lauffer , Roy H. Magnuson , Voya R. Markovich
发明人： Rabindra N. Das , John M. Lauffer , Roy H. Magnuson , Voya R. Markovich
IPC分类号： H01R12/04 , H05K1/11
CPC分类号： H05K3/4069 , H05K3/429 , H05K3/4614 , H05K2201/015 , H05K2201/0245 , H05K2201/09536 , H05K2201/096 , H05K2201/10378 , H05K2203/1152
摘要： A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a binder component and at least one metallic component including microparticles. In another embodiment, the paste includes the binder and a plurality of nano-wires. Selected ones of the microparticles or nano-wires include a layer of solder thereon. A method of making such a substrate is also provided, as are an electrical assembly and information handling system adapter for having such a substrate as part thereof.
摘要翻译：一种电路化基板，包括用于提供电连接的导电浆料。在一个实施方案中，糊状物包含粘合剂组分和至少一种包含微粒的金属组分。在另一个实施方案中，糊状物包括粘合剂和多根纳米线。所选择的微粒或纳米线包括其上的焊料层。还提供了制造这种基板的方法，以及用于将这种基板作为其一部分的电组件和信息处理系统适配器。

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