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41. 发明授权

US08193575B2 Flash memory structure with enhanced capacitive coupling coefficient ratio (CCCR) and method for fabrication thereof 失效
标题翻译：具有增强的电容耦合系数比（CCCR）的闪存结构及其制造方法
公开(公告)号：US08193575B2
公开(公告)日：2012-06-05
申请号：US12027496
申请日：2008-02-07
申请人： Louis C. Hsu , Xu Ouyang , Ping-Chuan Wang , Zhijian J. Yang
发明人： Louis C. Hsu , Xu Ouyang , Ping-Chuan Wang , Zhijian J. Yang
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/7881
摘要： A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.
摘要翻译：具有增强的电容耦合系数比（CCCR）的闪速存储器结构可以以自对准方式制造，同时使用半导体衬底，该半导体衬底具有相对于围绕有源区域的隔离区域在孔内凹入的有源区域。闪速存储器结构包括不在隔离区上方升起的浮栅，并且优选地由具有U形的单层组成。 U形有助于增强电容耦合系数比。

42. 发明授权

US08189419B2 Apparatus for nonvolatile multi-programmable electronic fuse system 有权
标题翻译：非易失性多可编程电子保险丝系统的装置
公开(公告)号：US08189419B2
公开(公告)日：2012-05-29
申请号：US12498175
申请日：2009-07-06
申请人： Howard H. Chen , John A. Fifield , Louis C. Hsu
发明人： Howard H. Chen , John A. Fifield , Louis C. Hsu
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C17/16
摘要： Electronic fuse (e-fuse) systems with multiple reprogrammability are provided. In one aspect, a reprogrammable e-fuse system is provided that includes a first e-fuse string; a second e-fuse string; a selector connected to both the first e-fuse string and the second e-fuse string configured to alternately select an e-fuse from the first e-fuse string or the second e-fuse string to be programmed; and a comparator connected to both the first e-fuse string and the second e-fuse string configured to compare a voltage across the first e-fuse string to a voltage across the second e-fuse string to determine a programming state of the e-fuse system.
摘要翻译：提供具有多重重新编程能力的电子保险丝（e-fuse）系统。在一个方面，提供了一种可再编程电子熔丝系统，其包括第一电熔丝串; 第二个电熔丝串; 连接到第一电熔丝串和第二电熔丝串的选择器，被配置为交替地从要编程的第一电熔丝串或第二电熔丝串中选择电熔丝; 以及连接到第一电熔丝串和第二电熔丝串两者的比较器，被配置为将第一电熔丝串两端的电压与第二电熔丝串的电压进行比较，以确定电子熔丝串的编程状态，保险丝系统

43. 发明授权

US08169077B2 Dielectric interconnect structures and methods for forming the same 有权
标题翻译：介电互连结构及其形成方法
公开(公告)号：US08169077B2
公开(公告)日：2012-05-01
申请号：US12185759
申请日：2008-08-04
申请人： Chih-Chao Yang , Louis C. Hsu , Rajiv V. Joshi
发明人： Chih-Chao Yang , Louis C. Hsu , Rajiv V. Joshi
IPC分类号： H01L23/52
CPC分类号： H01L21/76834 , H01L21/76814 , H01L21/76826 , H01L21/76843 , H01L21/76844 , H01L21/76846
摘要： Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.
摘要翻译：提供介电互连结构及其形成方法。具体地说，本发明提供一种具有贵金属层（例如，Ru，Ir，Rh，Pt，RuTa以及Ru，Ir，Rh，Pt和RuTa的合金）的电介质互连结构，其直接形成在改性电介质上表面。在典型的实施方案中，通过用气态离子等离子体（例如Ar，He，Ne，Xe，N 2，H 2，NH 3和N 2 H 2）处理互连结构的暴露介电层来产生修饰的电介质表面。在本发明中，贵金属层可以直接形成在只保留在暴露的介电层中形成的任何沟槽或通孔的垂直表面上的任选的胶层上。此外，贵金属层可以沿着通孔和内部金属层之间的界面设置也可以不设置。

44. 发明申请

US20110075504A1 Dual Beta Ratio SRAM 有权
标题翻译：双倍比率SRAM
公开(公告)号：US20110075504A1
公开(公告)日：2011-03-31
申请号：US12566862
申请日：2009-09-25
申请人： Yuen H. Chan , Louis C. Hsu , Xu Ouyang , Robert C. Wong
发明人： Yuen H. Chan , Louis C. Hsu , Xu Ouyang , Robert C. Wong
IPC分类号： G11C8/16 , G11C11/00
CPC分类号： G11C8/16 , G11C11/412
摘要： A static random access memory (SRAM) cell includes a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio. A static random access memory (SRAM) array includes a plurality of SRAM cells, an SRAM cell including a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio.
摘要翻译：静态随机存取存储器（SRAM）单元包括第一读取端口，第一读取端口具有第一β比率; 和写入端口，所述写入端口具有基本上低于所述第一β比率的第二β比率。静态随机存取存储器（SRAM）阵列包括多个SRAM单元，包括第一读取端口的SRAM单元，第一读取端口具有第一β比率; 和写入端口，所述写入端口具有基本上低于所述第一β比率的第二β比率。

45. 发明授权

US07906428B2 Modified via bottom structure for reliability enhancement 有权
标题翻译：通过底部结构改进可靠性增强
公开(公告)号：US07906428B2
公开(公告)日：2011-03-15
申请号：US12121216
申请日：2008-05-15
申请人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis C. Hsu , Conal Eugene Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis C. Hsu , Conal Eugene Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76847 , H01L21/76865 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.
摘要翻译：本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

46. 发明授权

US07777306B2 Defect-free hybrid orientation technology for semiconductor devices 失效
标题翻译：半导体器件的无缺陷混合取向技术
公开(公告)号：US07777306B2
公开(公告)日：2010-08-17
申请号：US11682403
申请日：2007-03-06
申请人： Louis C. Hsu , Rajiv V. Joshi , Xu Ouyang
发明人： Louis C. Hsu , Rajiv V. Joshi , Xu Ouyang
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L29/78 , H01L29/785 , Y10T428/12528
摘要： A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.
摘要翻译：半导体器件包括具有两个晶体取向的半导体材料。半导体材料形成该器件的有效区域。在两个晶体取向上形成器件沟道，其包括形成在半导体材料的第一晶体取向表面中的第一区域和形成在半导体材料的第二晶体取向表面中的第二区域，其中第一晶体取向表面形成与第二晶体取向表面和器件通道的角度至少覆盖角度的交点。

47. 发明授权

US07772649B2 SOI field effect transistor with a back gate for modulating a floating body 失效
标题翻译：具有用于调制浮体的背栅的SOI场效应晶体管
公开(公告)号：US07772649B2
公开(公告)日：2010-08-10
申请号：US12036325
申请日：2008-02-25
申请人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , Carl Radens , William Tonti
发明人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , Carl Radens , William Tonti
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66772 , H01L29/78612 , H01L29/78648
摘要： A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.
摘要翻译：将掩模层施加在顶部半导体层上并且被图案化以在开口中暴露浅沟槽隔离结构以及要在其中形成第一源极/漏极区域和主体的顶部半导体区域的一部分。将离子注入到开口区域内的埋入绝缘体层的一部分中以形成损坏的埋层绝缘体区域。去除浅沟槽隔离结构，并且损坏的埋层绝缘体区域被选择性地蚀刻到未损坏的埋入绝缘体部分以形成空腔。在顶部半导体区域的侧壁和暴露的底表面上形成介电层，并且形成填充空腔的背栅。形成接触以向后栅极提供电偏压，使得主体和第一源极/漏极区域的电势被电调制。

48. 发明授权

US07692308B2 Microelectronic circuit structure with layered low dielectric constant regions 失效
标题翻译：微电子电路结构具有层状低介电常数区域
公开(公告)号：US07692308B2
公开(公告)日：2010-04-06
申请号：US12256735
申请日：2008-10-23
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Louis C. Hsu , Wai-Kin Li
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Louis C. Hsu , Wai-Kin Li
IPC分类号： H01L29/40
CPC分类号： H01L21/7682 , H01L21/76808 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least two generally parallel conductor structures. Also included are a plurality of substantially vertically extending relatively low-k volumes sealed within the substantially horizontal layers and the substantially horizontally extending volumes between the at least two generally parallel conductor structures. The substantially vertically extending relatively low-k volumes and the substantially horizontally extending relatively low-k volumes reduce parasitic capacitance between the at least two generally parallel conductor structures as compared to an otherwise comparable microelectronic circuit not including the relatively low-k volumes.
摘要翻译：电路结构包括至少两个大致平行的导体结构，以及多个基本上水平的层介质材料层，散布着基本上水平延伸的相对较低的介电常数（低k）体积。基本水平的层和基本上水平延伸的体积通常介于至少两个大致平行的导体结构之间。还包括在基本水平的层内密封的多个基本上垂直延伸的相对低k的体积，以及在至少两个大致平行的导体结构之间的基本水平延伸的体积。与不包括相对低k体积的其他可比较的微电子电路相比，基本垂直延伸的相对低k体积和基本水平延伸的相对低k体积减小了至少两个大致平行的导体结构之间的寄生电容。

49. 发明申请

US20090305472A1 DEFECT-FREE HYBRID ORIENTATION TECHNOLOGY FOR SEMICONDUCTOR DEVICES 失效
标题翻译：用于半导体器件的无缺陷混合方向技术
公开(公告)号：US20090305472A1
公开(公告)日：2009-12-10
申请号：US12543630
申请日：2009-08-19
申请人： Louis C. Hsu , Rajiv V. Joshi , Xu Ouyang
发明人： Louis C. Hsu , Rajiv V. Joshi , Xu Ouyang
IPC分类号： H01L21/762
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L29/78 , H01L29/785 , Y10T428/12528
摘要： A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.
摘要翻译：半导体器件包括具有两个晶体取向的半导体材料。半导体材料形成该器件的有效区域。在两个晶体取向上形成器件沟道，其包括形成在半导体材料的第一晶体取向表面中的第一区域和形成在半导体材料的第二晶体取向表面中的第二区域，其中第一晶体取向表面形成与第二晶体取向表面和器件通道的角度至少覆盖角度的交点。

50. 发明申请

US20090200598A1 FLASH MEMORY STRUCTURE WITH ENHANCED CAPACITIVE COUPLING COEFFICIENT RATIO (CCCR) AND METHOD FOR FABRICATION THEREOF 失效
标题翻译：具有增强电容耦合系数（CCCR）的闪存存储器结构及其制造方法
公开(公告)号：US20090200598A1
公开(公告)日：2009-08-13
申请号：US12027496
申请日：2008-02-07
申请人： Louis C. Hsu , Xu Ouyang , Ping-Chuan Wang , Zhijian J. Yang
发明人： Louis C. Hsu , Xu Ouyang , Ping-Chuan Wang , Zhijian J. Yang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/7881
摘要： A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.
摘要翻译：具有增强的电容耦合系数比（CCCR）的闪速存储器结构可以以自对准方式制造，同时使用半导体衬底，该半导体衬底具有相对于围绕有源区域的隔离区域在孔内凹入的有源区域。闪速存储器结构包括不在隔离区上方升起的浮栅，并且优选地由具有U形的单层组成。 U形有助于增强电容耦合系数比。

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