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41. 发明专利

JPH0481337B2 失效
公开(公告)号：JPH0481337B2
公开(公告)日：1992-12-22
申请号：JP16484082
申请日：1982-09-24
申请人： HITACHI LTD
发明人： ANZAI NORIO , YASUOKA HIDEKI
IPC分类号： H01L27/06 , H01L21/205 , H01L21/225 , H01L21/74 , H01L21/76 , H01L21/761 , H01L21/8249

42. 发明专利

JPH025424A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH025424A
公开(公告)日：1990-01-10
申请号：JP15471188
申请日：1988-06-24
申请人： HITACHI LTD
发明人： KATO TOKIO , ANZAI NORIO
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60
摘要： PURPOSE:To enhance the current density of a resin-sealed semiconductor device having satisfactory bondability with gold wirings and excellent corrosion resistance by composing a 2-layer structure of a wiring layer part connected with gold wirings in such a manner that its lower layer is composed of Al containing 3% of Cu and 1.5% of Si and its upper layer is composed of Al containing 2% of Cu and 1% of Si. CONSTITUTION:A resin-sealed semiconductor device is formed in such a manner that an interconnection layer part 7 connected with gold wirings 8 is formed in a 2-layer structure in which its lower layer 10 is composed of Al containing 3% of Cu and 1.5% of Si. Its upper layer 11 is composed of Al containing 2% of Cu and 1% of Si, and the layer 10 is covered with Al 14 containing low Cu content with satisfactory corrosion resistance. Thus, even if a package 2 is formed of resin, its corrosion resistance is improved, satisfactory bondability with the gold wirings can be obtained, and the current density of the layer 7 can be raised.

43. 发明专利

JPS6035576A MANUFACTURE OF MOS SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6035576A
公开(公告)日：1985-02-23
申请号：JP8177584
申请日：1984-04-25
申请人： HITACHI LTD
发明人： ANZAI NORIO , FUKUDA MINORU
IPC分类号： H01L29/78 , H01L21/265 , H01L29/788
摘要： PURPOSE:To form the EP-ROM excellent in charge holding and high in integration degree by a method wherein the leakage current between double-layer poly Si's is reduced while shallowing the source and drain diffused layers. CONSTITUTION:Part of a poly Si layer and a gate oxide film are removed by etching by photo resist treatment. Thereby, the source-drain regions 1s and 1d of an Si substrate 1 expose, and at the same time a poly Si gate 4G is formed. Next, the second phosphorus treatment of phosphorus diffusion is performed to the poly Si gate and the source and drain regions of the Si substrate. Then, the second gate oxide film 7 is formed on the surface of the gate by the second gate oxidation. The diffusion depths of the source and drain further advance by the heat treatment at this time. The second poly Si layer 8 is formed by deposition. Besides, this layer 8 is selectively etched, and then the second gate oxide film on the source and drain regions is removed by etching. A PSG9 is deposited over the entire surface, and contact parts are exposed by contact photoetching.

44. 发明专利

JPS59139665A Semiconductor device and manufacture thereof 失效
标题翻译：半导体器件及其制造
公开(公告)号：JPS59139665A
公开(公告)日：1984-08-10
申请号：JP1271583
申请日：1983-01-31
申请人： Hitachi Ltd
发明人： ANZAI NORIO , MURAMATSU AKIRA , YASUOKA HIDEKI , IKEDA TAKAHIDE
IPC分类号： H01L29/78 , H01L21/768 , H01L21/8249 , H01L27/06 , H01L27/08
摘要： PURPOSE:To form low phiB in an SBD electrode, which is the second electrode, and to prevent the deterioration at the shallow p-n junction on the first electrode by a method wherein pure Al which is the second electrode material and the Al-Si mixture which is the material of semiconductor are deposited on the whole surface, and the first electrode is formed by performing a heat treatment. CONSTITUTION:The electrode part only of the insulating film 4 on the main surface of the n type semiconductor substrate 1 whereon a p type base layer 2 and an n type emitter layer 3 are formed is removed, pure Al is vapor-deposited, and a pure Al film 6 is formed. After the surface on the n type emitter layer 3 has been exposed by removing the other pure Al film leaving an SBD element part only, the SBD electrode 6 is obtained by performing a heat treatment and a contact alloying. An Al-Si film 8 containing 5% in atomic weight of Si is formed. The Al-Si film on the SBD electrode 6 is removed and the entire electrode pattern is formed, and lastly, a contact alloying is performed by conducting a heat treatment and the first electrode 8 consisting of Al-Si is obtained.
摘要翻译：目的：在作为第二电极的SBD电极中形成低phiB，并且通过其中作为第二电极材料的纯Al和Al-Si混合物的方法来防止第一电极上的浅pn结处的劣化，半导体的材料沉积在整个表面上，并且通过进行热处理形成第一电极。构成：除去形成p型基极层2和n型发射极层3的n型半导体衬底1的主表面上的绝缘膜4的电极部分，蒸镀纯Al，纯化形成Al膜6。在n型发射极层3的表面通过除去仅剩下SBD元件部分的其他纯Al膜而露出后，通过进行热处理和接触合金化来获得SBD电极6。形成含有原子量为Si的5％的Al-Si膜8。除去SBD电极6上的Al-Si膜，形成整个电极图案，最后通过热处理进行接触合金化，得到由Al-Si构成的第一电极8。

45. 发明专利

JPS59103379A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS59103379A
公开(公告)日：1984-06-14
申请号：JP17293983
申请日：1983-09-21
申请人： Hitachi Ltd
发明人： ANZAI NORIO
IPC分类号： H01L29/78
CPC分类号： H01L29/78
摘要： PURPOSE:To give difference in the impurity density of a diffusion layer and a gate electrode by a method wherein a P type poly Si is provided on an N type Si substrate through the intermediary of a thin oxide film, and after an impurity introduction blocking film has been formed on the surface thereof, a mask is formed by performing a patterning, and impurities are introduced thereon. CONSTITUTION:A poly Si film 4, wherein a small quantity of B is added, is covered on the field oxide film 2 and a gate oxide film 3 located on an N type Si substrate 1. An SiO2 film 5 is formed on the whole surface, a gate-electrode pattern is formed, a high density of B is diffused from the film 4, and a P type source S, a drain D and a wiring layer 6 are formed. According to this constitution, a low resistance wiring layer and a high density source and drain can be obtained, and a sufficiently low resistance poly Si gate electrode can also be obtained, the channel dope from the gate is reduced as much as possible, thereby enabling to obtain the semiconductor device of high efficiency and reliability having little variation in threshold voltage.
摘要翻译：目的：为了通过其中在N型Si衬底上通过薄氧化膜提供P型多晶硅，并且在杂质引入阻挡膜之后的方法来使扩散层和栅电极的杂质浓度差异在其表面上形成，通过进行图案化形成掩模，并且在其上引入杂质。构成：在场氧化膜2和位于N型Si衬底1上的栅极氧化膜3上覆盖添加有少量B的多晶硅膜4.在整个表面上形成SiO 2膜5 形成栅极电极图案，B的高密度从膜4扩散，形成P +型源极S，漏极D和布线层6。根据该结构，能够获得低电阻布线层和高密度的源极和漏极，并且还可以获得足够低电阻的多晶硅栅电极，尽可能地减小栅极的沟道掺杂，从而使得以获得阈值电压几乎没有变化的高效率和可靠性的半导体器件。

46. 发明专利

JPS5979564A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS5979564A
公开(公告)日：1984-05-08
申请号：JP18901582
申请日：1982-10-29
申请人： Hitachi Ltd
发明人： MURAMATSU AKIRA , YASUOKA HIDEKI , ANZAI NORIO
IPC分类号： H01L29/78 , H01L21/8249 , H01L27/06
CPC分类号： H01L21/8249
摘要： PURPOSE:To form elements in a small size, and moreover to prevent a semiconductor integrated circuit device from a reduction of terminal voltage when a bi-polar transistor and a C-MOS FET are to be made to coexist in an n type epitaxial layer on a p type substrate buried with n type layers by a method wherein formation of the buried layer directly under a p-well is avoided. CONSTITUTION:An n type epitaxial layer 2 on a p type Si substrate 1 buried with n type layers 3a, 3b is isolated by a p type layer 4, and a p well 5 is formed avoiding the layer 3a. Field oxide films 8 are formed selectively, and an n type collector lead out layer 9 and a p type base 10 are provided by diffusion in order in the n type layer 2 on the layer 3b at first, and poly-Si gates 12 are formed on the n type layer 2 on the layer 3a in succession interposing gate oxide films 11 between them. After then, p type layers 13, n type layers 16 and an n type emitter 17 are provided applying properly SiO2 masks 14, 15 to complete a C-MOS FET and a bi-polar transistor. According to this construction, even when the epitaxial layer 2 is formed thin, the reduction of withstand voltage according to arising to the p-well 5 from the buried layer 3a can be avoided, and the device can be formed in a fine size.
摘要翻译：目的：为了形成小尺寸的元件，此外，为了防止当双极晶体管和C-MOS FET在n型外延层中共存时，半导体集成电路器件不会降低端电压通过其中避免直接在p阱下面形成掩埋层的方法，以n + +型掩埋的p型衬底。构成：用n +型层3a，3b埋置的p型Si衬底1上的n型外延层2被ap型层4隔离，形成阱阱5，避免了层3a。首先形成场氧化膜8，并且首先通过在层3b上的n +型层2中依次扩散而提供n +型集电极引出层9和p型基极10， Si层12在层3a上的n +型层2上依次形成在其间插入栅极氧化膜11。之后，设置p + +型层13，n +型层16和n +型发射极17，适当地施加SiO 2掩模14,15以完成C-MOS FET和双极晶体管。根据这种结构，即使外延层2形成得较薄，也可以避免由掩埋层3a对p阱5产生的耐受电压的降低，能够形成微细的尺寸。

47. 发明专利

JPS5852878A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5852878A
公开(公告)日：1983-03-29
申请号：JP15061681
申请日：1981-09-25
申请人： HITACHI LTD
发明人： ANZAI NORIO , SAKAMOTO ISAO
IPC分类号： H01L21/337 , H01L29/80 , H01L29/808
摘要： PURPOSE:To improve reliability as the junction type field-effect transistor J-FET used for an operational amplifier, etc. by decreasing the scattering of effective channel length to approximately 0 because the mutual positions of a source and an N layer functioning as an upper gate are determined through self-alignment using an Si3N4 film regarding the manufacture of the J-FET. CONSTITUTION:An impurity B is deposited and diffused selectively in high concentration to the surface of an Si substrate of a section, from which SiO2 is removed through etching while using the Si3N4 film 5 and an HLD film 6 as masks, and P regions 7a, 7b functioning as the source and a drain are shaped. When the HLD film 6 is removed and B ions are implanted in P 3a, B is introduced selectively to the P layer 3a while the Si3N4 film 5 is used as a mask, and a P layer 8 having slightly high concentration is formed. The Si3N4 film 5 is removed through etching, and the ions of P or As are implanted in a section serving as the upper gate through a gate oxide film, and an N layer 9 is shaped. The offset gate P layer 8 does not function as an N type, and the N layer 9 serving as the upper gate is formed in a self-alignment manner.

48. 发明专利

JPS56152258A BIPOLAR TRANSISTOR AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING MIS TYPE FET 失效
公开(公告)号：JPS56152258A
公开(公告)日：1981-11-25
申请号：JP5414880
申请日：1980-04-25
申请人： HITACHI LTD
发明人： MATSUDA TOSHIHIRO , HIRASHIMA TOSHINORI , ANZAI NORIO
IPC分类号： H01L29/78 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/73
摘要： PURPOSE:To contrive the integration of a high dielectric strength transistor by providing a p well region becoming a base in an n type epitaxial layer formed by occupying a part of the layer by an n buried layer on a p type substrate wherein an n emitter is provided in the p well region to compose an n-p-n transistor and a CMIS is composed in the remaining part of the n type epitaxial layer on the substrate. CONSTITUTION:An n type epitaxialy layer 12 is formed on a p type Si substrate by occupying a part of the layer 12 by an n buried layer 13 and a p type isolation layer 14 connecting to the p type substrate is formed at a part of the surface of the n type epitaxial layer and p type wells 15, 16 extending to the upper part of the buried layer 13 and that of the substrate respectively are formed at the remaining part of the layer 12 to form an n-p-n transistor consisting the p type well 15 as a base on the surface of the semiconductor layer 12a on the n buried layer. And a p-channel MOSFET is formed on the surface of an n type semiconductor layer 12b locating at the upper part of the substrate having no buried layer and an n-channel MOSFET is formed on the surface of the n type well 16. In this way, a bipolar transistor providing a high dielectric strength n-p-n transistor and a semiconductor integrating circuit having an MLSFET can be obtained.

49. 发明专利

JPS60103662A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS60103662A
公开(公告)日：1985-06-07
申请号：JP21094083
申请日：1983-11-11
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： IKEDA HIROSHI , YAMADA MITSUHIRO , YASUOKA HIDEKI , MURAMATSU AKIRA , ANZAI NORIO
IPC分类号： H01L27/06 , H01L21/8222 , H01L21/8238 , H01L21/8249 , H01L27/07 , H01L27/092
摘要： PURPOSE:To reduce the forward voltage drop and prevent the deterioration of the withstand voltage of a shallow p-n junction by a method wherein a metallic material is deposited over the entire surface, and an electrode material made of the mixture of another metallic material with a semiconductor substrate material is deposited over the entire surface, which are then heat-treated after removal of the unnecessary part of this electrode material. CONSTITUTION:A material, produced by removal of only the electrode parts from an insulation film (SiO2 film) 4 on the main surface of an n type semiconductor substrate 11 with a p type base layer 2 and an n type emitter layer 3 formed, is prepared. An evaporated or sputtered Pt film 8 is formed over the entire surface in the state that an electrode part A is covered with a masking material 7 with only the other SBD electrode part B left. A Pt-Si layer 9 is formed by alloying the Pt film with Si the semiconductor material of the substrate by sintering. Al and Si films 10 are formed by evaporating Al containing Si at 5% of atomic weight and Si over the entire surface, and the whole electrode (wiring) pattern is formed by removing unnecessary Al and Si films. Finally, contact alloying is performed by heat treatment.

50. 发明专利

JPS605541A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS605541A
公开(公告)日：1985-01-12
申请号：JP10658384
申请日：1984-05-28
申请人： HITACHI LTD
发明人： OKABE TAKAHIRO , NAKAMURA TOORU , WATABE TOMOYUKI , KANEKO KENJI , NAGATA MINORU , AZUMA TAKASHI , HORIE NOBORU , MURAMATSU AKIRA , ANZAI NORIO , NISHIMURA TAKANORI
IPC分类号： H01L27/082 , H01L21/761 , H01L21/764 , H01L21/8226 , H01L21/76 , H01L27/06
摘要： PURPOSE:To obtain high density and high performance semiconductor integrated circuit by cutting off and separating an epitaxial layer for forming elements by means such as etching, and forming elements on the isolated layers. CONSTITUTION:n type layers 2, 200 are selectively formed on a p type substrate 1, and an epitaxial layer 3 is laminated thereon. Then, a phosphorus glass layer 4 formed at a low temperature is formed on the surface, and a window of an isolated part 6 is opened by a photoresist 5. With the photoresist 5 as a mask a phosphorus glass layer 4 is etched, and with the layer as a mask the layer 3 is etched. The entire element isolated at the epitaxial layer by separation 8 is covered with an oxide 9, an epitaxial layer 11 is exposed only on an integrated implantation logic circuit by the known photoetching method, and n type diffusion is performed by ion implanting or diffusing method. Then, an insulating film 12 is covered on the overall surface by the known technique, p type layers 14, 13, 14 and n type layers 16, 17, 18 are formed by ion implanting and diffusing method, a window of the contact is opened, and the electrodes 19, 20, 21, 22, 23, 24, 25 are formed. In this manner, a normal n-p-n transistor 10 is formed on the left half part and an integrated implanted logic circuit 101 is simultaneously formed on the right half part.

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