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1. 发明授权

US3906620A Method of producing multi-layer structure 失效
标题翻译：生产多层结构的方法
公开(公告)号：US3906620A
公开(公告)日：1975-09-23
申请号：US41044573
申请日：1973-10-29
申请人： HITACHI LTD
发明人： ANZAI NORIO , TOMOZAWA AKIHIRO , TSUNEMATSU MASAYASU , MATSUI YASUSHI
IPC分类号： H01L29/78 , H01L21/00 , H01L21/306 , H01L21/32 , H01L21/3205 , H01L21/336 , H01L23/52 , H01L29/00 , B01J17/00
CPC分类号： H01L21/32 , H01L21/00 , H01L29/00 , H01L2924/0002 , Y10S148/106 , Y10S148/141 , H01L2924/00
摘要： A method of producing metal-insulator-semiconductor structures, wherein an insulating layer is etched using a conductor layer formed on a selected area of the insulating layer as a mask, and a peripheral edge projection of the conductor layer caused by side etching of the side portion of the insulating layer during the etching step is completely converted into an insulator, whereby the destruction of the gate of the structure is prevented.
摘要翻译：一种制造金属绝缘体半导体结构的方法，其中使用形成在绝缘层的选定区域上的导体层作为掩模蚀刻绝缘层，以及由侧面的侧蚀引起的导体层的周边边缘突起在蚀刻步骤期间绝缘层的一部分被完全转变为绝缘体，由此防止了结构的栅极的破坏。

2. 发明专利

GB2128024B METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 未知
公开(公告)号：GB2128024B
公开(公告)日：1986-01-02
申请号：GB8324163
申请日：1983-09-09
申请人： HITACHI LTD
发明人： ANZAI NORIO , YASUOKA HIDEKI
IPC分类号： H01L27/06 , H01L21/205 , H01L21/225 , H01L21/74 , H01L21/76 , H01L21/761 , H01L21/8249 , H01L21/70
摘要： The present invention relates to a method of manufacturing a semiconductor integrated circuit device, especially a Bi-MOS IC. It comprises: 1. introducing an impurity of a first conductivity type into a plurality of parts of one major surface of a substrate containing a first conductivity type impurity, to form a plurality of impurity-doped regions which have an impurity density higher than that of said substrate; 2. forming an epitaxial semiconductor layer containing an impurity of a second conductivity type on the one major surface of said substrate; 3. introducing a first conductivity type impurity simultaneously into those parts of a major surface of said epitaxial semiconductor layer which overlie said plurality of impurity doped regions; and 4. introducing the first conductivity type impurity of said plurality of impurity-doped regions into said epitaxial semiconductor layer by drive-in diffusion, and subjecting to drive-in diffusion the first conductivity type impurity introduced in the major surface of said epitaxial semiconductor layer, to connect diffused layers formed by the respective diffusions and to form an isolation region and a semiconductor region for forming a MOS FET. MOS FETs can be formed in the semiconductor regions and bipolar transistors in a part of the epitaxial semiconductor layer.

3. 发明专利

GB2128024A METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 未知
公开(公告)号：GB2128024A
公开(公告)日：1984-04-18
申请号：GB8324163
申请日：1983-09-09
申请人： HITACHI LTD
发明人： ANZAI NORIO , YASUOKA HIDEKI
IPC分类号： H01L27/06 , H01L21/205 , H01L21/225 , H01L21/74 , H01L21/76 , H01L21/761 , H01L21/8249 , H01L21/70
摘要： The present invention relates to a method of manufacturing a semiconductor integrated circuit device, especially a Bi-MOS IC. It comprises: 1. introducing an impurity of a first conductivity type into a plurality of parts of one major surface of a substrate containing a first conductivity type impurity, to form a plurality of impurity-doped regions which have an impurity density higher than that of said substrate; 2. forming an epitaxial semiconductor layer containing an impurity of a second conductivity type on the one major surface of said substrate; 3. introducing a first conductivity type impurity simultaneously into those parts of a major surface of said epitaxial semiconductor layer which overlie said plurality of impurity doped regions; and 4. introducing the first conductivity type impurity of said plurality of impurity-doped regions into said epitaxial semiconductor layer by drive-in diffusion, and subjecting to drive-in diffusion the first conductivity type impurity introduced in the major surface of said epitaxial semiconductor layer, to connect diffused layers formed by the respective diffusions and to form an isolation region and a semiconductor region for forming a MOS FET. MOS FETs can be formed in the semiconductor regions and bipolar transistors in a part of the epitaxial semiconductor layer.

4. 发明专利

DE3329224A1 未知
公开(公告)号：DE3329224A1
公开(公告)日：1984-03-15
申请号：DE3329224
申请日：1983-08-12
申请人： HITACHI LTD
发明人： YASUOKA HIDEKI , TANIZAKI YASUNOBU , MURAMATSU AKIRA , ANZAI NORIO
IPC分类号： H01L29/78 , H01L21/76 , H01L21/8249 , H01L27/00 , H01L27/06 , H01L27/092 , H01L27/10 , H01L21/72
摘要： The present invention relates to a Bi-CMOS.IC, characterized by comprising a semiconductor substrate of a first conductivity type, and a semiconductor layer of a second conductivity type which is epitaxially grown on one major surface of said semiconductor substrate and which is electrically isolated into a plurality of semiconductor island regions by a thick surface oxide film formed by local oxidation and a semiconductor diffused layer of the first conductivity type formed between said oxide film and said substrate; a bipolar type semiconductor element being formed in one of said island regions, while CMOS type semiconductor elements are formed in the other island regions; the thick surface oxide film formed by the local oxidation being included between a base region and a collector contact region within said one island region formed with said bipolar type semiconductor element, while gate electrodes made of a semiconductor are disposed over said other island regions formed with said CMOS type semiconductor elements.

5. 发明专利

FR2533751B1 未知
公开(公告)号：FR2533751B1
公开(公告)日：1988-11-10
申请号：FR8309953
申请日：1983-06-16
申请人： HITACHI LTD
发明人： ANZAI NORIO , YASUOKA HIDEKI
IPC分类号： H01L27/06 , H01L21/205 , H01L21/225 , H01L21/74 , H01L21/76 , H01L21/761 , H01L21/8249 , H01L29/68
摘要： The present invention relates to a method of manufacturing a semiconductor integrated circuit device, especially a Bi-MOS IC. It comprises: 1. introducing an impurity of a first conductivity type into a plurality of parts of one major surface of a substrate containing a first conductivity type impurity, to form a plurality of impurity-doped regions which have an impurity density higher than that of said substrate; 2. forming an epitaxial semiconductor layer containing an impurity of a second conductivity type on the one major surface of said substrate; 3. introducing a first conductivity type impurity simultaneously into those parts of a major surface of said epitaxial semiconductor layer which overlie said plurality of impurity doped regions; and 4. introducing the first conductivity type impurity of said plurality of impurity-doped regions into said epitaxial semiconductor layer by drive-in diffusion, and subjecting to drive-in diffusion the first conductivity type impurity introduced in the major surface of said epitaxial semiconductor layer, to connect diffused layers formed by the respective diffusions and to form an isolation region and a semiconductor region for forming a MOS FET. MOS FETs can be formed in the semiconductor regions and bipolar transistors in a part of the epitaxial semiconductor layer.

6. 发明专利

FR2533751A1 未知
公开(公告)号：FR2533751A1
公开(公告)日：1984-03-30
申请号：FR8309953
申请日：1983-06-16
申请人： HITACHI LTD
发明人： ANZAI NORIO , YASUOKA HIDEKI
IPC分类号： H01L27/06 , H01L21/205 , H01L21/225 , H01L21/74 , H01L21/76 , H01L21/761 , H01L21/8249 , H01L29/68
摘要： The present invention relates to a method of manufacturing a semiconductor integrated circuit device, especially a Bi-MOS IC. It comprises: 1. introducing an impurity of a first conductivity type into a plurality of parts of one major surface of a substrate containing a first conductivity type impurity, to form a plurality of impurity-doped regions which have an impurity density higher than that of said substrate; 2. forming an epitaxial semiconductor layer containing an impurity of a second conductivity type on the one major surface of said substrate; 3. introducing a first conductivity type impurity simultaneously into those parts of a major surface of said epitaxial semiconductor layer which overlie said plurality of impurity doped regions; and 4. introducing the first conductivity type impurity of said plurality of impurity-doped regions into said epitaxial semiconductor layer by drive-in diffusion, and subjecting to drive-in diffusion the first conductivity type impurity introduced in the major surface of said epitaxial semiconductor layer, to connect diffused layers formed by the respective diffusions and to form an isolation region and a semiconductor region for forming a MOS FET. MOS FETs can be formed in the semiconductor regions and bipolar transistors in a part of the epitaxial semiconductor layer.

7. 发明专利

DE2352331A1 未知
公开(公告)号：DE2352331A1
公开(公告)日：1974-05-16
申请号：DE2352331
申请日：1973-10-18
申请人： HITACHI LTD
发明人： ANZAI NORIO , TOMOZAWA AKIHIRO , TSUNEMATSU MASAYASU , KODAIRA TOKIO , MATSUI YASUSHI
IPC分类号： H01L29/78 , H01L21/00 , H01L21/306 , H01L21/32 , H01L21/3205 , H01L21/336 , H01L23/52 , H01L29/00 , H01L7/34
摘要： A method of producing metal-insulator-semiconductor structures, wherein an insulating layer is etched using a conductor layer formed on a selected area of the insulating layer as a mask, and a peripheral edge projection of the conductor layer caused by side etching of the side portion of the insulating layer during the etching step is completely converted into an insulator, whereby the destruction of the gate of the structure is prevented.

8. 发明专利

MY8700610A METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 未知
公开(公告)号：MY8700610A
公开(公告)日：1987-12-31
申请号：MY8700610
申请日：1987-12-30
申请人： HITACHI LTD
发明人： ANZAI NORIO , YASUOKA HIDEKI
IPC分类号： H01L27/06 , H01L21/205 , H01L21/225 , H01L21/74 , H01L21/76 , H01L21/761 , H01L21/8249 , H01L21/70
摘要： The present invention relates to a method of manufacturing a semiconductor integrated circuit device, especially a Bi-MOS IC. It comprises: 1. introducing an impurity of a first conductivity type into a plurality of parts of one major surface of a substrate containing a first conductivity type impurity, to form a plurality of impurity-doped regions which have an impurity density higher than that of said substrate; 2. forming an epitaxial semiconductor layer containing an impurity of a second conductivity type on the one major surface of said substrate; 3. introducing a first conductivity type impurity simultaneously into those parts of a major surface of said epitaxial semiconductor layer which overlie said plurality of impurity doped regions; and 4. introducing the first conductivity type impurity of said plurality of impurity-doped regions into said epitaxial semiconductor layer by drive-in diffusion, and subjecting to drive-in diffusion the first conductivity type impurity introduced in the major surface of said epitaxial semiconductor layer, to connect diffused layers formed by the respective diffusions and to form an isolation region and a semiconductor region for forming a MOS FET. MOS FETs can be formed in the semiconductor regions and bipolar transistors in a part of the epitaxial semiconductor layer.

9. 发明专利

HK71087A METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 未知
公开(公告)号：HK71087A
公开(公告)日：1987-10-09
申请号：HK71087
申请日：1987-10-01
申请人： HITACHI LTD
发明人： ANZAI NORIO , YASUOKA HIDOKI
IPC分类号： H01L27/06 , H01L21/205 , H01L21/225 , H01L21/74 , H01L21/76 , H01L21/761 , H01L21/8249 , H01L21/70
摘要： The present invention relates to a method of manufacturing a semiconductor integrated circuit device, especially a Bi-MOS IC. It comprises: 1. introducing an impurity of a first conductivity type into a plurality of parts of one major surface of a substrate containing a first conductivity type impurity, to form a plurality of impurity-doped regions which have an impurity density higher than that of said substrate; 2. forming an epitaxial semiconductor layer containing an impurity of a second conductivity type on the one major surface of said substrate; 3. introducing a first conductivity type impurity simultaneously into those parts of a major surface of said epitaxial semiconductor layer which overlie said plurality of impurity doped regions; and 4. introducing the first conductivity type impurity of said plurality of impurity-doped regions into said epitaxial semiconductor layer by drive-in diffusion, and subjecting to drive-in diffusion the first conductivity type impurity introduced in the major surface of said epitaxial semiconductor layer, to connect diffused layers formed by the respective diffusions and to form an isolation region and a semiconductor region for forming a MOS FET. MOS FETs can be formed in the semiconductor regions and bipolar transistors in a part of the epitaxial semiconductor layer.

10. 发明专利

HK69587A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES AND METHOD OF MANUFACTURING THE SAME 未知
公开(公告)号：HK69587A
公开(公告)日：1987-10-02
申请号：HK69587
申请日：1987-09-24
申请人： HITACHI LTD
发明人： YASUOKA HIDEKI , TANIZAKI YASUNOBU , MURAMATSU AKIRA , ANZAI NORIO
IPC分类号： H01L29/78 , H01L21/76 , H01L21/8249 , H01L27/00 , H01L27/06 , H01L27/092
摘要： The present invention relates to a Bi-CMOS.IC, characterized by comprising a semiconductor substrate of a first conductivity type, and a semiconductor layer of a second conductivity type which is epitaxially grown on one major surface of said semiconductor substrate and which is electrically isolated into a plurality of semiconductor island regions by a thick surface oxide film formed by local oxidation and a semiconductor diffused layer of the first conductivity type formed between said oxide film and said substrate; a bipolar type semiconductor element being formed in one of said island regions, while CMOS type semiconductor elements are formed in the other island regions; the thick surface oxide film formed by the local oxidation being included between a base region and a collector contact region within said one island region formed with said bipolar type semiconductor element, while gate electrodes made of a semiconductor are disposed over said other island regions formed with said CMOS type semiconductor elements.

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