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1. 发明专利

JPH0478018B2 失效
公开(公告)号：JPH0478018B2
公开(公告)日：1992-12-10
申请号：JP16662483
申请日：1983-09-12
申请人： HITACHI LTD
发明人： MATSUDA TOSHIHIRO
IPC分类号： H01L27/08 , H01L21/8249 , H01L27/06 , H01L27/092 , H01L29/78

2. 发明专利

JPS57155734A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS57155734A
公开(公告)日：1982-09-25
申请号：JP4030181
申请日：1981-03-23
申请人： HITACHI LTD
发明人： ANSAI NORIO , NISHIMURA TAKANORI , MATSUDA TOSHIHIRO
IPC分类号： H01L21/306 , H01L21/768
摘要： PURPOSE:To prevent the step disconnection of Al wiring by a method wherein SiO2 or the like is formed on an Si3N4 film and the overhang of an SiO2 film located under the Si3N4 is prevented. CONSTITUTION:An SiO2 film 2, Si3N4 film 3, and PSG or CVD, SiO2 film 5 are formed on a substrate 1. And photo masks 6 are formed by the application of photoresist and the removal of etching is consecutively applied to the PSG film 5, Si3N4 film 3 and lower-layer SiO2 film 2 by HF-family etchant by the use of the photo masks 6. Side etching is especially big for the PSG and SiO2, and the Si3N4 projects in eaves shape. The overhang of the SiO2 film located under the Si3N4 is preventend. After that, the photoresist, Si3N4 and PSG are removed.

3. 发明专利

JPH03105968A INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH03105968A
公开(公告)日：1991-05-02
申请号：JP24198389
申请日：1989-09-20
申请人： HITACHI LTD
发明人： OKADA YUTAKA , MATSUURA TATSUJI , MATSUDA TOSHIHIRO , SATO HIROSHI
IPC分类号： H01L21/8238 , H01L27/08 , H01L27/092
摘要： PURPOSE:To prevent an interference of both circuits and to prevent a latch-up by a method wherein a power supply of a digital circuit is separated from a power supply for substrate-potential fixation use and a substrate potential is made higher than the power supply of the circuit. CONSTITUTION:A power supply of an analog circuit is separated from that of a digital circuit; at the same time, a substrate potential of the digital circuit is not supplied from the power supply of the digital circuit but is supplied from a power supply, for substrate-potential fixation use, which has been installed separately. When capacities connected to a power-supply terminal AVDD of the analog circuit, a power-supply terminal DVDD of the digital circuit and a power-supply terminal SVDD for substrate-potential fixation use are designated as CA, CD and CS, respectively, the CS is set to be lower than the CA and the CD. Thereby, it is possible to prevent a pnpn parasitic thyristor formed by a p-n junction as well as a source diffusion of a p-well and an n-channel transistor from being turned on and to avoid a latch-up.

4. 发明专利

JPS615545A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS615545A
公开(公告)日：1986-01-11
申请号：JP12516284
申请日：1984-06-20
申请人： HITACHI LTD
发明人： MATSUDA TOSHIHIRO
IPC分类号： H01L27/082 , H01L21/82 , H01L21/8226 , H01L23/528 , H01L27/118 , H03K19/091
摘要： PURPOSE:To enable to perform the wirings among a number of logical elements in an orderly manner without substantially impairing spatial efficiency by a method wherein the wirings are provided by dividing them into two functional groups of common wirings and local wirings and, at the same time, the local wirings are wired with multiplayer wirings. CONSTITUTION:The wirings with which wire connections are performed between logical elements IILs are proided by dividing into two functional groups. One of them is the common wirings L11-L14 which are used to connected between IILs, and the other one is the local wirings L21 and L23 which are used to individually connect a plurality of electrodes B, c1, c2 and c3 located inside each IIL and the common wirings L11-L14. At the same time, a plurality of electrodes B, c1, c2 and c3 in each IIL are arranged two-dimensionally respectively. As a result, the four electrodes B, c1, c2 and c3 in each IIL do not have a positional interference each other, and they can be connected to any desired one of the common wirings L11-L14 through the intermediary of the local wiring L21 or L23.

5. 发明专利

JPS59117150A Semiconductor integrated circuit device and its manufacture 失效
标题翻译：半导体集成电路设备及其制造
公开(公告)号：JPS59117150A
公开(公告)日：1984-07-06
申请号：JP22615282
申请日：1982-12-24
申请人： Hitachi Ltd
发明人： MATSUDA TOSHIHIRO
IPC分类号： H01L29/78 , H01L21/8249 , H01L27/06
CPC分类号： H01L21/8249
摘要： PURPOSE:To improve carrier injection and a transport efficiency by forming the base of a bipolar element in graft base structure in an IC in which a bipolar transistor and an MOSFET coexist. CONSTITUTION:A thin SiO2 film on an n type silicon base body 11 is removed partially through etching, and a polysilicon layer 14 is formed partially to the removed section. The thin SiO2 layer is removed while using the polysilicon layer 14 as a mask. Boron (B) as an impurity is introduced to the surface of the silicon base body 11 through ion implantation and diffused while using a thick SiO2 film 12 as a mask. A section immediately under the polysilicon layer is formed in low impurity concentration and a shallow p type region is formed at that time. The surface is coated with a mask material 17, and arsenic As or phosphorus (P) as an impurity is introduced through the polysilicon layer 14 to form an n region 18. Injection efficiency and the transport factor are improved because base width WB can be reduced and the impurity concentration of an active base is small.
摘要翻译：目的：通过在双极晶体管和MOSFET共存的IC中形成接枝基底结构中的双极元件的基极来改善载流子注入和传输效率。构成：通过蚀刻部分地去除n型硅基体11上的薄SiO 2膜，并且多晶硅层14部分地形成到去除部分。在使用多晶硅层14作为掩模的同时去除薄的SiO 2层。作为杂质的硼（B）通过离子注入引入到硅基体11的表面，并在使用厚SiO 2膜12作为掩模的同时扩散。在多晶硅层的正下方的部分形成为低杂质浓度，此时形成浅的p +型区域。该表面涂覆有掩模材料17，并且作为杂质的砷As或磷（P）通过多晶硅层14引入以形成n +区域18.注入效率和传输因子得到改善，因为基极宽度WB 可以降低活性碱的杂质浓度。

6. 发明专利

JPS57115857A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS57115857A
公开(公告)日：1982-07-19
申请号：JP122181
申请日：1981-01-09
申请人： HITACHI LTD
发明人： INABA TOORU , MATSUDA TOSHIHIRO , TAKAGI TATSUHAYA
IPC分类号： H01L29/78 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/12 , H01L29/73 , H01L29/786
摘要： PURPOSE:To obtain a semiconductor device with a small parasitic capacitance performing a high speed logical operation by a method wherein a semiconductor layer is formed on a substrate hving dielectric property such as sapphire, and on the surface of it a bipolar transistor is provided. CONSTITUTION:On a sapphire substrate 10 whose surface is mirror polished an N type Si layer 11 is grown by epitaxial growth, its surface is covered by an SiO2 film 12 and by removing a part of this an N type buried layer 13 which reaches the substrate 10 is formed by diffusion in a part of the layer 11. Next after the film 12 is removed, on all surface an N type layer 14 is grown epitaxually, and by ion implanted using an SiO2 film 15 as a mask a P type base region 16 for a bipolar transistor element which reaches the layer 13, a P type isolation region 17 which reaches the substrate 10, and a P type region 18 for an N channel MOSFET element are formed. Subsequently a P type base contact region 23 and an N type emitter region 26 in the region 16, an N type emitter region 26 in the region 16, an N collector contact region 27 and P type source-drain regions 24 and 25 in a layer 14 between which the region 17 is put, and an N type source-drain regions 28 and 29 in the region 18 are individually formed by diffusion.

7. 发明专利

JPS6153737A Electronic device assembling method and apparatus thereof 失效
标题翻译：电子装置组装方法及装置
公开(公告)号：JPS6153737A
公开(公告)日：1986-03-17
申请号：JP17496184
申请日：1984-08-24
申请人： Hitachi Ltd
发明人： MATSUDA TOSHIHIRO , MINAMIMURA EIJI , HORIE NOBORU
IPC分类号： H01L21/60
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/04042 , H01L2224/05553 , H01L2224/05624 , H01L2224/45 , H01L2224/45124 , H01L2224/45144 , H01L2224/48 , H01L2224/48091 , H01L2224/48247 , H01L2224/48463 , H01L2224/48464 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/78 , H01L2224/78301 , H01L2224/85 , H01L2224/85214 , H01L2924/01013 , H01L2924/01079 , H01L2924/01082 , H01L2924/10162 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PURPOSE:To realize wire bonding between pad and wire within a short period and improve working efficiency by placing the bonding pad on a semiconductor chip with wire, irradiating such area with laser beam and alloying the metal of such contact area. CONSTITUTION:A bonding pad 2 of aluminum is formed in the periphery of main surface of semiconductor chip 1 and the chip 1 is attached to a tab 3. A wire 5 using gold or aluminum, etc. extended from a lead 4 integraly formed as a metal lead frame is connected to the bonding pad 2. At the time of this connection, the wire 5 and bonding pad 2 are connected with a wire bonder 6 and this connected region is irradiated with the laser beam L and thereby an alloyed portion 7 is formed. When a plurality of wires 5 and lead frames are integrated, and end points of wires 5 are simultaneously placed in contact with the bonding pad 2 and the bonding time is curtailed by irradiation of laser beam L.
摘要翻译：目的：在短时间内实现焊盘和焊丝之间的引线接合，并通过将焊盘放置在半导体芯片上，并用激光束照射这种区域并使这种接触区域的金属合金化，从而提高工作效率。构成：在半导体芯片1的主表面的外围形成有铝焊盘2，将芯片1安装在突片3上。使用从引线4的整数延伸的金或铝等的线5作为金属引线框架连接到接合焊盘2.在该连接时，线5和接合焊盘2与引线接合器6连接，并且该连接区域被激光束L照射，从而合金部分7为形成。当多个电线5和引线框架被集成时，电线5的端点同时放置成与焊盘2接触，并且通过激光束L的照射来限制焊接时间。

8. 发明专利

JPS6052115A INFORMATION SIGNAL CONVERTER 失效
公开(公告)号：JPS6052115A
公开(公告)日：1985-03-25
申请号：JP15899783
申请日：1983-09-01
申请人： HITACHI LTD
发明人： NODA TSUTOMU , ISO YOSHIMI , KAWABATA KENJI , SATOU TETSUO , MATSUDA TOSHIHIRO
IPC分类号： H03M1/02 , H03M1/52
摘要： PURPOSE:To prevent the increase in the scale of circuit by applying a current from a current source to each of integration circuits selectively and switchingly and applying an output voltage of a prescribed integration circuit to a single voltage comparator circuit. CONSTITUTION:When analog signals AR, AL are applied from analog input terminals 1, 1', capacitors 9, 9' are controlled so that they are discharged alternately via switches 3, 3'. Thus, outputs ER, EL of the amplifiers 6, 6' are compared respectively with reference voltages E1, E2 of voltage comparator circuits 12, 13 and when the voltages ER, EL are respectively equal to the E1, E2, the count of the 1st and 2nd counters (not shown in a figure) of a control circuit 16 is stopped. Then the analog signals AR, AL are digitized alternately via a changeover switch 27 and a digital signal corresponding to an output terminal 2 is extracted in time division multiplex. Similarly, when the digital signal is applied from a digital input terminal 17, an analog signal is outputted from a terminal 26 by using a control circuit 18.

9. 发明专利

JPS59193046A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS59193046A
公开(公告)日：1984-11-01
申请号：JP6546583
申请日：1983-04-15
申请人： Hitachi Ltd
发明人： MATSUDA TOSHIHIRO , KONDOU SHIZUO , KURI KAZUHIKO , MINAMIMURA EIJI
IPC分类号： H03M1/08 , H01L21/82 , H01L21/822 , H01L27/02 , H01L27/04
CPC分类号： H01L27/0203 , H01L2224/05554 , H01L2224/49113
摘要： PURPOSE:To eliminate the generation of the malfunction caused by cross-talk between two circuits by a method wherein power source wirings are provided separately and connected to external connection terminals, respectively, when an analog circuit and a digital circuit are provided on one semiconductor substrate, which are then connected to the power source wirings. CONSTITUTION:The digital circuit D composed of a C-MOSIC and the analog circuit A composed of a bi-polar C-MOS semiconductor device are provided in the surface layer part of one semiconductor substrate 1, and a plurality of the wiring terminals 4 for external connection are arranged in the periphery of the substrate 1. Next, an Al powder source wiring 5a1 for operating the circuit D is connected to the wiring terminal 4a1, where a power source voltage VDD is supplied, and a power source wiring 5a2 for operating the circuit A is connected to the other terminal 4a2, where a power source voltage VCC is supplied. Thereafter, these terminals 4a1 and 4a2 are connected to external leads 2 via wires 3, respectively. Earth wirings 5b1 and 5b2 from the circuits D and A are connected to wiring terminals 4b1 and 4b2 corresponding to the terminals 4a1 and 4a2, respectively, and then connected to the leads 2 likewise via the wires 3.
摘要翻译：目的：为了消除由两个电路之间的串扰引起的故障的产生，其中分别提供电源布线并连接到外部连接端子的方法，当模拟电路和数字电路设置在一个半导体衬底上时，然后将其连接到电源布线。构成：由一个C-MOSIC构成的数字电路D和由双极C-MOS半导体器件构成的模拟电路A设置在一个半导体衬底1的表层部分中，并且多个用于外部连接被布置在基板1的周围。接下来，用于操作电路D的Al粉末源布线5a1连接到其中提供电源电压VDD的布线端子4a1和用于操作的电源布线5a2 电路A连接到提供电源电压VCC的另一端子4a2。此后，这些端子4a1和4a2分别经由导线3连接到外部引线2。来自电路D和A的接地布线5b1和5b2分别连接到对应于端子4a1和4a2的布线端子4b1和4b2，然后同样通过导线3连接到引线2。

10. 发明专利

JPS57188860A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS57188860A
公开(公告)日：1982-11-19
申请号：JP7352581
申请日：1981-05-18
申请人： HITACHI LTD
发明人： ARAI YUUJI , MATSUDA TOSHIHIRO
IPC分类号： H01L21/74 , H01L21/331 , H01L21/822 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L29/73 , H01L29/78
摘要： PURPOSE:To facilitate formation of resistance regions for a bipolar MOSIC by a device wherein in a growth layer of reverse conductivity type provided on a substrate and including buried layers is formed a region having the same conductivity type as that of the substrate and reaching the buried layer. CONSTITUTION:N type buried layers are formed in a P type Si substrate and N type layers are formed thereon through epitaxial growth. Then, a P type well for a MOST is formed through diffusion, and at the same time another P type well is formed above the N type buried layer. This P type well above the buried layer is used as a resistance region. By so doing, it becomes possible to attain high resistance without a need of modifying the process and to reduce an area of the resistance correspondingly.

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