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41. 发明专利

JPH02198165A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02198165A
公开(公告)日：1990-08-06
申请号：JP1612489
申请日：1989-01-27
申请人： HITACHI LTD
发明人： AKAZAWA TAKASHI
IPC分类号： H01L21/3205 , H01L21/822 , H01L23/52 , H01L27/04
摘要： PURPOSE:To eliminate electric source noise by a method wherein electric source wiring layers are so arranged as to overlap each other with an insulating film applied in-between. CONSTITUTION:A supply source wiring layer 5 connected to a supply source Vcc and a grounding source wiring layer 6 connected to a grounding source Vcc overlap each other with an insulating film applied in-between. The supply source wiring layer 5 and the grounding source wiring layer 6 overlap each other in a region where slanting lines 5 and 6 overlap each other and the region is provided along the circumference part of a chip 4. With this constitution, an intersource capacitance is formed between those wiring layers and electric source noise can be eliminated without taking problems such as latch-up and mounting into consideration.

42. 发明专利

JPH01138675A MOS STORING CIRCUIT 失效
公开(公告)号：JPH01138675A
公开(公告)日：1989-05-31
申请号：JP29524987
申请日：1987-11-25
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAHASHI TAMOTSU , MASUDA HIROYUKI , SHINPO OSAMU , AKAZAWA TAKASHI
IPC分类号： G11C11/41 , G11C11/34
摘要： PURPOSE:To make storage into a large capacity and to obtain a high-speed action by precharging the data lines of a non-selective column to a constant potential respectively by an MOS transistor for holding potentials and the MOS transistor for moving charges. CONSTITUTION:When data lines 13 and 14 are under a non-selective state, an MOS transistor 17 for moving charges is turned on, and the non-selective data lines 13 and 14 are bypassed mutually and arranged to the same potential. Further, MOS transistors 10 and 11 for holding potentials are turned on, and the data lines 13 and 14 are kept in constant high voltage while they are kept in the same potential mutually. On the other hand, when the data lines 13 and 14 are selected, only the transistors 10 and 11 for holding potentials connected to the selected data lines 13 and 14, and the transistor 17 for moving charges are turned off, and the selected data lines 13 and 14 can be changed immediately according to either the stored data or the writing data of a selective storing cell 12.

43. 发明专利

JPS6352462A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6352462A
公开(公告)日：1988-03-05
申请号：JP19545486
申请日：1986-08-22
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： AKAZAWA TAKASHI , ARAKI MASAMI
IPC分类号： H01L23/50 , H01L23/28 , H01L25/10 , H01L25/11 , H01L25/18
摘要： PURPOSE:To increase the capacity of storing function by providing a first connecting terminal of recess or projecting type on the lower surface of a semiconductor device, providing a second connecting terminal of projecting or recess type of the shape to be engaged with the first terminal on the upper surface of the device, and electrically connecting the first terminal to the second terminal. CONSTITUTION:Each semiconductor device 2 has a plurality of connecting terminals (lead pins) 2A of recess or projecting type on its lower surface (the placing surface of a circuit substrate 1), and a plurality of connecting terminals 2B of projecting or recess type on its upper surface. The terminals 28 are formed in the shape engaged with the terminal 2A provided on the lower surface of the device 2 having the same storing function. The terminals 2A and 2B are constructed to be electrically connected. Thus, a plurality of the devices 2 each having the storing function are stacked to be mounted on the mounting surface of the substrate 1.

44. 发明专利

JPS62223891A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS62223891A
公开(公告)日：1987-10-01
申请号：JP6568486
申请日：1986-03-26
申请人： HITACHI LTD
发明人： AKAZAWA TAKASHI
IPC分类号： G11C11/407 , G11C11/34
摘要： PURPOSE:To provide no complicate circuit forming a timing signal inside by operating an internal circuit in time series by an external clock signal. CONSTITUTION:A timing control circuit TGC receives the inverse of a chip selection signal CE supplied from an external terminal, the inverse of a write enable signal WE and the time series timing signal formed by a shift register SR and forms the timing signal according to the operating mode thereof and other various types of timing signals required for a memory operation. The shift register SR makes the clock signal CLK supplied from the external terminal a shift clock signal, performs the shift operation of high level (logic '1') continuously supplied to a first step circuit, and thereby forms the timing signal supplied in time series to the timing control circuit TGC.

45. 发明专利

JPS6256018A COMPLEMENTARY TYPE SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6256018A
公开(公告)日：1987-03-11
申请号：JP17159286
申请日：1986-07-23
申请人： HITACHI LTD
发明人： AKAZAWA TAKASHI , SHUDO HITOYOSHI , SAKAMOTO TAKASHI
IPC分类号： H03K19/0185 , H03K5/02 , H03K19/096
摘要： PURPOSE:To save the power consumption by providing plural complementary dynamic inverter circuits and a static complementary level converting circuit. CONSTITUTION:An input signal is fed to an input line N2 from a complementary circuit receiving a low power voltage VDD. A clock signal having a large amplitude between zero V and a high power voltage VGG fed to a source of a MISFET Q1 is applied to a clock signal line N1. The large amplitude clock signal is applied from a level converting circuit receiving a signal outputted from a clock signal generating circuit activated by, e.g., a low power voltage. The level converting circuit consists of n-channel MISFETs Q4, Q6, p-channel MISFETs Q5, Q7 and a complementary inverter circuit IV1. Thus, the level conversion circuit with low power consumption is offered.

46. 发明专利

JPS60100229A DATA PROCESSOR 失效
公开(公告)号：JPS60100229A
公开(公告)日：1985-06-04
申请号：JP20825584
申请日：1984-10-05
申请人： HITACHI LTD
发明人： HAGIWARA YOSHIMUNE , MAEDA SHIGEMICHI , AKAZAWA TAKASHI , KOBAYASHI MASAHITO , KIDA YUUZOU , KITA YASUHIRO
IPC分类号： G06F9/30 , G06F15/78
摘要： PURPOSE:To reduce the area of wiring for a control signal by arranging an instruction decoding circuit and an operation timing signal generating circuit dispersedly for every function block. CONSTITUTION:The address of an instruction word to be read is supplied from a program address counter 1 to a program memory 2 to read the instruction word for internal operation control, and the word is outputted as a control signal group to respective function blocks 6-13 formed on an integrated circuit substrate. In this case, instruction decoders i-4, instruction registers i-3, timing signal generating circuits i-5 are arranged dispersedly on the substrate adjacently to the function blocks 6-13. Further, instruction output lines 215 from the program memory 2 are laid as a bus connecting the respective blocks 6-13, and a basic timing signal line 214 is also arranged. Consequently, the occupation area of control signal woring among the blocks is reduced and the number of the signal lines 214 and 215 is decreased greatly.

47. 发明专利

JPS5951014B2 失效
公开(公告)号：JPS5951014B2
公开(公告)日：1984-12-12
申请号：JP5305277
申请日：1977-05-11
申请人： HITACHI LTD
发明人： KAWAGOE HIROHITO , TORII SHUICHI , SAKAMOTO TAKASHI , AKAZAWA TAKASHI
IPC分类号： H03K17/22 , G06F1/00 , G06F1/24 , H03K3/286

48. 发明专利

JPS5994119A LATCH-UP PREVENTING CIRCUIT IN CMOS LSI 失效
公开(公告)号：JPS5994119A
公开(公告)日：1984-05-30
申请号：JP20196182
申请日：1982-11-19
申请人： HITACHI LTD
发明人： MIYAKE NORIO , AKAZAWA TAKASHI
IPC分类号： H03K19/003 , G05F1/56 , H01L27/092
摘要： PURPOSE:To prevent latch-up effectively, by providing a capacitor on the way of a power supply line connecting a power supply terminal and an internal circuit. CONSTITUTION:N type regions 13a and 13b are formed at a proper interval on the surface of a P type well region 12 formed on an N type semiconductor substrate 11. A gate insulating film 14 having about 500Angstrom thickness is formed on the substrate surface between these regions 13a and 13b. A gate electrode 15 is formed on the film 14. This electrode 15 is connected to a power supply line 3, and the P type well region 12 is connected to the earth point of the circuit. Thus, the gate capacity of an MOSFET is used as a capacitor 4 for preventing latch-up.

49. 发明专利

JPS58166813A CHOPPER TYPE COMPARATOR 失效
公开(公告)号：JPS58166813A
公开(公告)日：1983-10-03
申请号：JP4913382
申请日：1982-03-29
申请人： HITACHI LTD
发明人： AKAZAWA TAKASHI
IPC分类号： H03F3/38
摘要： PURPOSE:To assure a high-speed operation with high precision for a chopper type comparator, by keeping the peak value of switching noises due to the mirror capacity at a low level by an MISFET. CONSTITUTION:When a control signal phi is set at a high level, the bias voltage is supplied to nodes N1-N4 of AC amplifying stages. Then an input analog signal Vin is supplied to a capacitor C1 through an MISFETQd. In this case, a noise is produced due to the mirror capacity of a switch MISFETS1. However, the current passing through the MISFETQd having the constant current characteristics receives limitation. Thus the peak value of the noise is limited. When the signal phi is set at a low level, a switch MISFETS2 is turned on to supply the reference voltage Vref to a node N0. In this case, the peak value is also reduced for the noise produced by the mirror capacity of the MISFETS2 when the noise passes through the MISFETQd.

50. 发明专利

JPS5894032A DIGITAL SIGNAL PROCESSOR 失效
公开(公告)号：JPS5894032A
公开(公告)日：1983-06-04
申请号：JP19089281
申请日：1981-11-30
申请人： HITACHI ELECTRONICS , HITACHI LTD
发明人： SUGIYAMA SHIZUO , AKAZAWA TAKASHI
IPC分类号： H03M7/30 , G06F5/00 , G06F17/10 , H04B14/04
摘要： PURPOSE:To decrease the signal transfer time, by performing a parallel transfer of data between a digital signal processor and an analog device and at the same time converting the number of bits for the transfer data. CONSTITUTION:A transfer data of a data bus line of a digital signal processor 50 is fetched into an input register 44 by the signal of an instruction line 23 supplied from an instruction memory 16 and the signal of a timing line 21 supplied from a timing producing circuit 18. The data fetched into the register 44 is supplied to a bit compressor 32 as an output signal 55 of an input register to convert a data of 16 bits into data of 8 bits. Thus the parallel data of 8 bits is delivered from an output control circuit 47. While the data supplied from a data input terminal 57 is supplied to a bit expander 37 via an input controlling circuit 40 and with the signal applied to an input control terminal 58 synchronously with said data. Then this data is transferred to the bus line 25 in the form of a parallel data of 16 bits. As a result, no serial-parallel inversion is required.

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