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1. 发明专利

DE2616648A1 CIRCUIT FOR KEYBOARD FEEDING INFORMATION - by use of input annaand locking keys uses timing pulses on multiplex principle operated by integrated semiconductor logic 未知
公开(公告)号：DE2616648A1
公开(公告)日：1976-11-11
申请号：DE2616648
申请日：1976-04-15
申请人： HITACHI LTD
发明人： NOMIYA KOSEI , TORII SHUICHI , HARA HIDEO
IPC分类号： G06F3/02 , H03M11/20 , H01H13/70 , H04L17/04
摘要： Keyboard input circuit for feeding in information using input keys and locking keys. Control is via timing pulses using multiplex principles. A digital section of the system is made from an integrated semi-conductor circuit with push-button input. This system also contains other digital circuits such as memories, arithmetic operating networks, control networks and generators for the timing pulses. A multi-channel coded signal is produced via the timing pulse. The decoding circuit is connected to the N-ear coding network to convert the output signals into a number of digital pulses. The multi-channel coded signal is fed to a gating circuit, a second gating circuit is connected between the keyboard and the first gating circuit to prevent any faulty digital signals if more than one key is depressed simultaneously.

2. 发明专利

DE3366746D1 CIRCUIT FOR INTEGRATING AN ANALOG SIGNAL AND CONVERTING IT INTO A DIGITAL SIGNAL 未知
公开(公告)号：DE3366746D1
公开(公告)日：1986-11-13
申请号：DE3366746
申请日：1983-07-27
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAGI KATSUAKI , KITA YUZO , HAGIWARA YOSHIMUNE , TORII SHUICHI , OGAWA KAZUYOSHI
IPC分类号： G01R22/00 , G01R21/00 , G01R21/127 , G01R21/133 , G06G7/186 , G01R21/06
摘要： An integrator circuit comprises reset means (RST) by which when it is detected that an integrator output Vp for an input analog signal has coincided with a plus or minus reference value, the integral output is reset to the vicinity of the middle of the plus and minus reference values, in effect, without interrupting the integrating operation; a circuit (OR) which produces a pulse each time the coincidence is detected; and a circuit (FF2) which produces a direction signal indicating whether the coincidence results from the increase or decrease of the integral input. The pulses produced in the state in which the direction signal is indicating the increase are counted up, and the pulses produced in the state in which the direction signal is indicating the decrease are counted down, whereby the precise integral value of the input analog signal can be detected.

3. 发明专利

DE2337070A1 未知
公开(公告)号：DE2337070A1
公开(公告)日：1974-03-21
申请号：DE2337070
申请日：1973-07-20
申请人： HITACHI LTD
发明人： KODAIRA TOKIO , NOMIYA KOSEI , HATSUKANO YOSHIKAZU , TORII SHUICHI
IPC分类号： G11C19/18 , H03K19/096 , H03K19/08

4. 发明专利

DE2654262A1 Light or luminescent indicator driver - has light intensity control connected to pulse generator producing pulse signal 未知
公开(公告)号：DE2654262A1
公开(公告)日：1977-06-16
申请号：DE2654262
申请日：1976-11-30
申请人： HITACHI LTD
发明人： ABE MASAYOSHI , TORII SHUICHI
IPC分类号： G04G9/00 , G09G3/04 , G09G3/10 , G09F9/00
摘要： A light or luminescent indicator driver has a light intensity control device connected to a pulse generator producing pulse signal. The pule generator (PG) produces successive input pulses which are received by the light intensity control (1-4). The pulse duration of the pulse signal differs from the pulse duration of the input pulses and changes in accordance with the brightness of the environment. The pulse signal is passed to the light indicator to control the light intensity of the light indicator in accordance with the brightness of the environment. The light intensity control contains an integrating circuit (1,2) with a variable time constant.

5. 发明专利

DE2358717A1 未知
公开(公告)号：DE2358717A1
公开(公告)日：1974-05-30
申请号：DE2358717
申请日：1973-11-26
申请人： HITACHI LTD
发明人： NOMIYA KOSEI , TORII SHUICHI
IPC分类号： G06F15/02 , G06F3/02 , G06F3/147 , G06F11/00 , G09G3/04 , H03M11/20 , G09F9/32

6. 发明专利

CH604372A5 未知
公开(公告)号：CH604372A5
公开(公告)日：1978-09-15
申请号：CH2677
申请日：1977-01-04
申请人： HITACHI LTD
发明人： NARITA KAZUTAKA , OHBA KENICHI , TORII SHUICHI , ARAI TAMOTU
IPC分类号： H01L21/8236 , G11C17/12 , H01L21/82 , H01L21/8234 , H01L27/088 , H01L27/092 , H01L29/78 , H03K3/356 , H03K19/094 , H03K19/0948 , H03K19/096 , H03K19/177 , H01L27/02 , H03K19/08

7. 发明专利

DE2659221A1 Integrated semiconductor circuit with MIS logic circuit - responds to at least one input signal and delivers output signal using complementary inverting stage 未知
公开(公告)号：DE2659221A1
公开(公告)日：1977-07-21
申请号：DE2659221
申请日：1976-12-28
申请人： HITACHI LTD
发明人： NARITA KAZUTAKA , OHBA KENICHI , TORII SHUICHI , ARAI TAMOTU
IPC分类号： H01L21/8236 , G11C17/12 , H01L21/82 , H01L21/8234 , H01L27/088 , H01L27/092 , H01L29/78 , H03K3/356 , H03K19/094 , H03K19/0948 , H03K19/096 , H03K19/177 , H01L27/04 , G11C17/04
摘要： The output signal level is determined by the presence or absence of charges in a load capacitance. The output wire is crossed by a second signal wire. A complementary inverting stage is connected by one end to a voltage source potential and it is connected by the other end a reference potential. It is inserted into the output wire (11) between the MIS logic circuit and the crossing point between the output wire and the other signal wire.

8. 发明专利

DE2332507A1 未知
公开(公告)号：DE2332507A1
公开(公告)日：1974-01-24
申请号：DE2332507
申请日：1973-06-26
申请人： HITACHI LTD
发明人： NOMIYA KOSEI , MINORIKAWA KAZUO , TORII SHUICHI , HATSUKANO YOSHIKAZU , KODAIRA TOKIO
IPC分类号： G11C19/28 , H03K3/356 , H03K3/286
摘要： A static flip-flop circuit comprising a first inverter including a first insulated gate field-effect transistor (MIS-FET), a second inverter including a second MIS-FET and whose output is feedback-connected to the gate of the first MIS-FET, a third inverter including a third MIS-FET, the gates of the second and third MIS-FET's being interconnected, a transfer gate MIS-FET whose gate is connected to receive a first train of clock pulses, an input MIS-FET whose gate is connected to receive an input signal, a control MIS-FET which is connected in series with the input MIS-FET, the series connection being incorporated in parallel with the first MIS-FET, a further control MIS-FET which is connected in parallel with the second MIS-FET, and a reading MIS-FET which is connected to the output of the third inverter and whose gate is connected to receive a second train of clock pulses differing in phase from the first train of clock pulses, the control MIS-FET's being connected to receive a writing control signal at their gates, the writing control signal being adapted to render the control MIS-FET's conductive when at least the transfer gate MIS-FET is conductive at writing, whereby the same information as stored in the second MIS-FET is stored in the third MIS-FET in order to be read out through the reading MIS-FET.

9. 发明专利

DE2332431A1 未知
公开(公告)号：DE2332431A1
公开(公告)日：1974-01-24
申请号：DE2332431
申请日：1973-06-26
申请人： HITACHI LTD
发明人： HATSUKANO YOSHIKAZU , NOMIYA KOSEI , TORII SHUICHI
IPC分类号： G11C19/28 , H03K3/356 , H03K3/286
摘要： A static flip-flop circuit comprising a first inverter including a first insulated gate field-effect transistor (MIS-FET), a second inverter including a second MIS-FET and whose output is feedback-connected to the gate of the first MIS-FET, a third inverter including a third MIS-FET, the gates of the second and third MIS-FET's being interconnected, a transfer gate MIS-FET whose gate is connected to receive a first train of clock pulses, an input MIS-FET whose gate is connected to receive an input signal, a control MIS-FET which is connected in series with the input MIS-FET, the series connection being incorporated in parallel with the first MIS-FET, a further control MIS-FET which is connected in parallel with the second MIS-FET, and a reading MIS-FET which is connected to the output of the third inverter and whose gate is connected to receive a second train of clock pulses differing in phase from the first train of clock pulses, the control MIS-FET's being connected to receive a writing control signal at their gates, the writing control signal being adapted to render the control MIS-FET's conductive when at least the transfer gate MIS-FET is conductive at writing, whereby the same information as stored in the second MIS-FET is stored in the third MIS-FET in order to be read out through the reading MIS-FET.

10. 发明专利

DE2332413A1 未知
公开(公告)号：DE2332413A1
公开(公告)日：1974-01-24
申请号：DE2332413
申请日：1973-06-26
申请人： HITACHI LTD
发明人： HATSUKANO YOSHIKAZU , NOMIYA KOSEI , TORII SHUICHI
IPC分类号： G11C19/28 , H03K3/356 , H03K3/286
摘要： A static flip-flop circuit comprising a first inverter including a first insulated gate field-effect transistor (MIS-FET), a second inverter including a second MIS-FET and whose output is feedback-connected to the gate of the first MIS-FET, a third inverter including a third MIS-FET, the gates of the second and third MIS-FET's being interconnected, a transfer gate MIS-FET whose gate is connected to receive a first train of clock pulses, an input MIS-FET whose gate is connected to receive an input signal, a control MIS-FET which is connected in series with the input MIS-FET, the series connection being incorporated in parallel with the first MIS-FET, a further control MIS-FET which is connected in parallel with the second MIS-FET, and a reading MIS-FET which is connected to the output of the third inverter and whose gate is connected to receive a second train of clock pulses differing in phase from the first train of clock pulses, the control MIS-FET's being connected to receive a writing control signal at their gates, the writing control signal being adapted to render the control MIS-FET's conductive when at least the transfer gate MIS-FET is conductive at writing, whereby the same information as stored in the second MIS-FET is stored in the third MIS-FET in order to be read out through the reading MIS-FET.

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