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1. 发明专利

DE3176788D1 HIGH SPEED DIGITAL PROCESSOR 未知
公开(公告)号：DE3176788D1
公开(公告)日：1988-07-21
申请号：DE3176788
申请日：1981-10-27
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： HAGIWARA YOSHIMUNE , SUGIYAMA SHIZUO , MAEDA NARIMICHI , YUMOTO OSAMU , AKAZAWA TAKASHI , KOBAYASHI MASAHITO , KITA YASUHIRO , KITA YUZO
IPC分类号： G06F7/00 , G06F5/01 , G06F7/50 , G06F7/57 , G06F7/76 , G06F17/10 , G06F7/48 , G06F7/38
摘要： In a digital signal processor comprising interface means for data input/output with an external device; data buses (21, 22); data memories (5, 6); floating point multiplier (14) for adding exponent parts and multiplying mantissa parts of a pair of data applied; a floating adder/subtracter (15); an accumulator (16); a switching circuit (17) and a control circuit (4), the floating adder/subtracter comprising adjusting means (67 to 69, 63 to 65) for adjusting two floating point data; an adder (75) for adding the two adjusted mantissa parts of the two floating point data; a leftwards shift circuit (76) for shifting output data from the adder; a zero detector (79) to provide a first shift data signal; a correction circuit (85) and a control circuit (89) to generate an underflow signal and provide a normalized exponent part of the sum of the two data; a constant adder circuit (77) and a selector (81) for providing the shift circuit with a second shift data signal, or the first shift data signal depending on whether or not the underflow signal is generated.

2. 发明专利

DE3177238D1 未知
公开(公告)号：DE3177238D1
公开(公告)日：1991-02-07
申请号：DE3177238
申请日：1981-10-27
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： HAGIWARA YOSHIMUNE , SUGIYAMA SHIZUO , MAEDA NARIMICHI , YUMOTO OSAMU , AKAZAWA TAKASHI , KOBAYASHI MASAHITO , KITA YASUHIRO , KITA YUZO
IPC分类号： G06F7/00 , G06F5/01 , G06F7/50 , G06F7/57 , G06F7/76 , G06F17/10 , G06F5/00 , H03M7/24
摘要： In a digital signal processor comprising interface means for data input/output with an external device; data buses (21, 22); data memories (5, 6); floating point multiplier (14) for adding exponent parts and multiplying mantissa parts of a pair of data applied; a floating adder/subtracter (15); an accumulator (16); a switching circuit (17) and a control circuit (4), the floating adder/subtracter comprising adjusting means (67 to 69, 63 to 65) for adjusting two floating point data; an adder (75) for adding the two adjusted mantissa parts of the two floating point data; a leftwards shift circuit (76) for shifting output data from the adder; a zero detector (79) to provide a first shift data signal; a correction circuit (85) and a control circuit (89) to generate an underflow signal and provide a normalized exponent part of the sum of the two data; a constant adder circuit (77) and a selector (81) for providing the shift circuit with a second shift data signal, or the first shift data signal depending on whether or not the underflow signal is generated.

3. 发明专利

DE3143223A1 未知
公开(公告)号：DE3143223A1
公开(公告)日：1982-05-19
申请号：DE3143223
申请日：1981-10-30
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： KOBAYASHI MASAHITO , MAEDA NARIMICHI , HAGIWARA YOSHIMUNE , AKAZAWA TAKASHI , SUGIYAMA SHIZUO
IPC分类号： G06F7/38 , G06F7/00 , G06F7/487 , G06F7/52 , G06F7/533 , G06F7/544 , G06F7/76

4. 发明专利

JPH02224019A ADDING AND SUBTRACTING DEVICE 失效
公开(公告)号：JPH02224019A
公开(公告)日：1990-09-06
申请号：JP18737389
申请日：1989-07-21
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： HAGIWARA YOSHIMUNE , SUGIYAMA SHIZUO , MAEDA SHIGEMICHI , YUMOTO OSAMU , AKAZAWA TAKASHI , KOBAYASHI MASAHITO , KITA YASUHIRO , KIDA YUZO
IPC分类号： G06F7/485 , G06F7/50 , G06F7/527 , G06F7/53 , G06F17/10
摘要： PURPOSE:To prevent an overflow and an underflow which accompany addition and subtraction from occurring by equipping a means which normalize an addition/subtraction result with a means which limits the shift quantity of the mantissa part of the addition/subtraction result so that the value of the exponent part is within a specific range. CONSTITUTION:A zero detecting circuit 79 and a left-directional shifting circuit 76 are provided so as to normalize the output UM of an adder 75 so that its absolute value is maximum. Namely, the zero detecting circuit 79 detects the number of theta1 of successive '0's following the sign bit of the data UM (below the decimal point) and the shifting circuit 76 shifts the data UM left (to the most significant digit bit) by theta1 bits to obtain mantissa part data LM which has the maximum absolute value. When the data UM is minus, on the other hand, the data is shifted only by the number of successive '1's. In this case, a subtracting circuit 78 calculates (gamma-theta1) as to exponent part data gamma and its output UE is regarded as a normalized exponent value. Consequently, a fast, high-accuracy OR arithmetic function is obtained.

5. 发明专利

JPS55156461A PHASE SELECTING CIRCUIT 失效
公开(公告)号：JPS55156461A
公开(公告)日：1980-12-05
申请号：JP6394779
申请日：1979-05-25
申请人： HITACHI ELECTRONICS , HITACHI LTD
发明人： SUGIYAMA SHIZUO , AOKI HIDEO
IPC分类号： H04L27/20
摘要： PURPOSE:To simplify integration by eliminating the need for a resistance and capacitor while simplifying a circuit, by direct adding paralleled data to the previous addition result as to every single-modulation element. CONSTITUTION:A rectangular wave of 2,400Hz is output from oscillating circuit 20 and by its clocks, input data are input to shift register circuits 22 and 23. When signal SD is input as 00011011, the register circuits output parallel data of dibits 00, 01, 10 and 11. Namely, the output signal of FF23 is a digit input of 2 in the opposite code to input data, and that of FF22 is an digit input of 2 as input data are. Further, ''1'' is input from switch circuit 24 as a digit of 2 and set constant at angles of 45 deg., 135 deg., 225 deg. and 315 deg.. Adding circuit 25 adds this paralle-converted code to the previous addition result of one-modulation element. To modulate a carrier of 1,800Hz at a speed of 1,200 baud, anticipation should be taken by 180 deg. and value alpha determined by alpha+0 deg.+180 deg. indicates a shift in phase.

6. 发明专利

JPH02224021A ADDING AND SUBTRACTING DEVICE 失效
公开(公告)号：JPH02224021A
公开(公告)日：1990-09-06
申请号：JP18737589
申请日：1989-07-21
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： HAGIWARA YOSHIMUNE , SUGIYAMA SHIZUO , MAEDA SHIGEMICHI , YUMOTO OSAMU , AKAZAWA TAKASHI , KOBAYASHI MASAHITO , KITA YASUHIRO , KIDA YUZO
IPC分类号： G06F7/485 , G06F7/50 , G06F7/527 , G06F7/53 , G06F17/10
摘要： PURPOSE:To obtain a fast adding and subtracting device which can be used without being aware of whether data to be added or subtracted is floating-point or fixed-point data by converting fixed-point data into floating-point data in response to 3rd floating-point data. CONSTITUTION:When a fixed-point display is converted (FXFL) into a floating- point display, a selecting circuit 61 selects an accumulator output supplied from an A bus 27, i.e. fixed-point data A as outputs alphaM and alphaE. A selecting circuit 60 selects data y2 for conversion, which is read out of a memory 5 or 6 to a (Y) bus 26 by being specified by the address part of an FXFL instruction, as output betaM and betaE. The data y2 for conversion is selected within a range wherein, for example, the mantissa part betaM is zero and the exponent part betaE is +7 - -8 and has a certain reference value. Consequently, the fast, high- accuracy OR arithmetic function is obtained.

7. 发明专利

JPS5894032A DIGITAL SIGNAL PROCESSOR 失效
公开(公告)号：JPS5894032A
公开(公告)日：1983-06-04
申请号：JP19089281
申请日：1981-11-30
申请人： HITACHI ELECTRONICS , HITACHI LTD
发明人： SUGIYAMA SHIZUO , AKAZAWA TAKASHI
IPC分类号： H03M7/30 , G06F5/00 , G06F17/10 , H04B14/04
摘要： PURPOSE:To decrease the signal transfer time, by performing a parallel transfer of data between a digital signal processor and an analog device and at the same time converting the number of bits for the transfer data. CONSTITUTION:A transfer data of a data bus line of a digital signal processor 50 is fetched into an input register 44 by the signal of an instruction line 23 supplied from an instruction memory 16 and the signal of a timing line 21 supplied from a timing producing circuit 18. The data fetched into the register 44 is supplied to a bit compressor 32 as an output signal 55 of an input register to convert a data of 16 bits into data of 8 bits. Thus the parallel data of 8 bits is delivered from an output control circuit 47. While the data supplied from a data input terminal 57 is supplied to a bit expander 37 via an input controlling circuit 40 and with the signal applied to an input control terminal 58 synchronously with said data. Then this data is transferred to the bus line 25 in the form of a parallel data of 16 bits. As a result, no serial-parallel inversion is required.

8. 发明专利

JPH02224020A ADDING AND SUBTRACTING DEVICE 失效
公开(公告)号：JPH02224020A
公开(公告)日：1990-09-06
申请号：JP18737489
申请日：1989-07-21
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： HAGIWARA YOSHIMUNE , SUGIYAMA SHIZUO , MAEDA SHIGEMICHI , YUMOTO OSAMU , AKAZAWA TAKASHI , KOBAYASHI MASAHITO , KITA YASUHIRO , KIDA YUZO
IPC分类号： G06F7/485 , G06F7/50 , G06F7/527 , G06F7/53 , G06F17/10
摘要： PURPOSE:To obtain a fast adding and subtracting device which can be used without being aware of whether data to be added or subtracted is floating-point or fixed-point data by providing a means which converts floating-point data into fixed-point data. CONSTITUTION:When a floating-point display is converted (FLFX) into a fixed- point display, an exponent part satisfies a relation alphaE(alphaE: the exponent part of output data alpha from a selecting circuit 61)

9. 发明专利

JPS62187933A ADDER/SUBTRACTOR 失效
公开(公告)号：JPS62187933A
公开(公告)日：1987-08-17
申请号：JP2458987
申请日：1987-02-06
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： HAGIWARA YOSHIMUNE , SUGIYAMA SHIZUO , MAEDA SHIGEMICHI , YUMOTO OSAMU , AKAZAWA TAKASHI , KOBAYASHI MASAHITO , KITA YASUHIRO , KIDA YUZO
IPC分类号： G06F7/485 , G06F7/00 , G06F7/50 , G06F7/508 , G06F7/53 , G06F7/76 , G06F17/10 , H04B3/23
摘要： PURPOSE:To obtain a wide dynamic range by automatically switching an arithmetic method to a floating-point arithmetic format when the number of internal arithmetic data is large or a fixed point arithmetic format in case of a small number. CONSTITUTION:In case of floating-point arithmetic, operation is executed by a multiplier 14 and an adder/subtractor 15. When the internal data of the adder/ subtractor 15 consist of 16 bits of a mantissa part and 4 bits of an exponential part, the exponential part gamma can process values included in the range of [+7--8] on the basis of the display of 2's complement and the dynamic range becomes 2 -27. In addition, fixed point arithmetic can be also executed on the basis of the specification of a program. Namely, when the number theta of nomalizing bits for the mantissa part of the arithmetic data is included within the range of (gamma-theta)

10. 发明专利

JPS5894033A DIGITAL SIGNAL PROCESSOR 失效
公开(公告)号：JPS5894033A
公开(公告)日：1983-06-04
申请号：JP19089381
申请日：1981-11-30
申请人： HITACHI ELECTRONICS , HITACHI LTD
发明人： SUGIYAMA SHIZUO , AKAZAWA TAKASHI
IPC分类号： H03M7/30 , G06F5/00 , H04B14/04
摘要： PURPOSE:To decrease the signal transfer time, by performing a parallel transfer of data between a digital signal processor and an analog device and at the same time using the transfer data with the switching given between the transfer data to which the number of bits is converted and that with no conversion of the number of bits. CONSTITUTION:A digital signal processor contains the 1st data input/output circuit which is connected via a data bus line and a data processing means which processes the data on a data bus line and then transmits is again to the data bus line. For such a processor, data on the data bus line 25 with the bit compression and data with no bit compression and with use of only partial 8 bits are switched by an output controlling circuit 47 to be delivered. At the same time, the data given from an external device is switched by an output register 43 between data with expansion of bit and that with no expansion of bit to be transferred to the line 25.

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